US11223333B2 - Microwave amplification circuit - Google Patents

Abstract

Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 10-2019-0113984, filed on Sep. 17, 2019, the entire contents of which are hereby incorporated by reference.

BACKGROUND

Embodiments of the inventive concept relate to a microwave amplification circuit.

A microwave amplification circuit may be used in various communication systems such as a microwave wireless communication system, a radio frequency (RF) transmission/reception system, etc. The microwave amplification circuit may amplify an input signal by using both an active element and a passive element. The active element may be used to obtain a gain for the input signal, and the passive element may be used for an impedance matching.

The microwave amplification circuit may amplify the input signal within an operating frequency band, but may also amplify the input signal outside the operating frequency band. The amplification of the input signal outside the operating frequency band by the microwave amplification circuit may cause deterioration of a communication system and additional circuitry such as a filter.

SUMMARY

Embodiments according to the inventive concept provide a microwave amplification circuit.

According to an embodiment of the inventive concept, an amplification circuit for amplifying an input signal includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and wherein the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor, and wherein the first passive element is one of an inductor and a capacitor, and the second passive element is another one of the inductor and the capacitor.

According to another embodiment of the inventive concept, an amplification circuit includes a first amplification stage that receives an input signal, and a second amplification stage connected in series with the first amplification stage, and wherein the first amplification stage includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, and a first transistor that amplifies the input signal provided from the input stage, wherein the input attenuation circuit includes a first resistor and a second resistor connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor, and wherein the first passive element is one of an inductor and a capacitor, and the second passive element is another one of the inductor and the capacitor.

BRIEF DESCRIPTION OF THE FIGURES

The above and other objects and features of the inventive concept will become apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings.

FIG. 1 is an exemplary block diagram of an amplification circuit according to an embodiment of the inventive concept.

FIGS. 2 to 4 are exemplary circuit diagrams of an input attenuation circuit or an output attenuation circuit of FIG. 1.

FIG. 5 is an exemplary graph of impedances of attenuation circuits of FIGS. 2 to 4.

FIG. 6A is a graph illustrating a magnitude of an impedance of an attenuation circuit of FIG. 2 and a magnitude of an impedance of an attenuation circuit of FIG. 3. FIG. 6B is a graph of frequency in which an attenuation circuit of FIG. 3 has the smallest impedance magnitude.

FIG. 7A is a graph illustrating a magnitude of an impedance of an attenuation circuit of FIG. 2 and a magnitude of an impedance of an attenuation circuit of FIG. 4. FIG. 7B is a graph of frequency in which an attenuation circuit of FIG. 4 has the smallest impedance magnitude.

FIGS. 8A to 8G are exemplary block diagrams of an amplification circuit of FIG. 1, respectively.

FIGS. 9A and 9B are graphs illustrating gains for input signals by amplification circuits of FIGS. 8A to 8C.

FIG. 10 is an exemplary block diagram of an amplification circuit according to another embodiment of the inventive concept.

FIG. 11 is an exemplary block diagram of a transmitter to which an amplification circuit according to an embodiment of the inventive concept is applied.

FIG. 12 is an exemplary block diagram of a receiver to which an amplification circuit according to an embodiment of the inventive concept is applied.

FIG. 13 is an exemplary block diagram of a transceiver to which an amplification circuit according to an embodiment of the inventive concept is applied.

DETAILED DESCRIPTION

Hereinafter, embodiments of the inventive concept will be described clearly and in detail such that those skilled in the art may easily carry out the inventive concept.

FIG. 1 is an exemplary block diagram of an amplification circuit according to an embodiment of the inventive concept. An amplification circuit 100 may receive an input signal, may amplify the received input signal, and may output the amplified input signal as an output signal. For example, a frequency of the input signal may be 30 GHz or more, and the input signal may correspond to a microwave signal or a radio frequency (RF) signal. Referring to FIG. 1, the amplification circuit 100 may include an input stage 110, an amplifier 120, and an output stage 130.

The input stage 110 may receive an input signal from an outside of the amplification circuit 100 and may include an input matching circuit 111 and an input attenuation circuit 116. The input matching circuit 111 may receive the input signal and may match (or matching) an input impedance of the amplification circuit 100. For example, the input matching circuit 111 may include a transmission line, a microstrip line, a stub, etc. For another example, the input matching circuit 111 may include one or more passive elements such as an inductor, a capacitor, and a resistor.

The input attenuation circuit 116 may provide a relatively low impedance at a specific frequency. The input attenuation circuit 116 may attenuate (or reduce, or decrease) a degree of transmitting the input signal to the amplifier 120 at the specific frequency and may attenuate a gain for the input signal at the specific frequency. The gain for the input signal may represent a ratio (e.g., S₂₁) of the input signal to the output signal, which is a signal in which the input signal is amplified by the amplification circuit 100. The specific frequency described above may be located outside an operating frequency band of the amplification circuit 100. In addition, the input attenuation circuit 116 may attenuate the gain for the input signal even at a peripheral frequency of the specific frequency. The amplifier 120 described later may amplify the input signal within the operating frequency band of the amplification circuit 100 and may amplify the input signal outside the operating frequency band of the amplification circuit 100. The input attenuation circuit 116 may attenuate the gain for the input signal outside the operating frequency band of the amplification circuit 100.

The amplifier 120 may amplify the input signal that is transmitted (or provided) through the input stage 110. The amplifier 120 may transmit (or provide) the amplified signal to the output stage 130. For example, the amplifier 120 may include a transistor such as a bipolar junction transistor (BJT), a field effect transistor (FET), etc. The transistor may amplify the input signal.

The output stage 130 may receive the amplified signal transmitted from the amplifier 120 and may output the amplified signal as the output signal to the outside of the amplification circuit 100. The output stage 130 may include an output matching circuit 131 and an output attenuation circuit 136. The output matching circuit 131 may receive the amplified signal, may match an output impedance of the amplification circuit 100, and may be implemented similarly to the input matching circuit 111. The output attenuation circuit 136 may be implemented the same as or similar to the input attenuation circuit 116. The output attenuation circuit 136 may provide a relatively low impedance at a specific frequency. The specific frequency of the output attenuation circuit 136 and the specific frequency of the input attenuation circuit 116 may be the same as or different from each other. The output attenuation circuit 136 may attenuate the gain for the input signal outside the operating frequency band of the amplification circuit 100.

Referring to FIG. 1, the amplification circuit 100 may include both the input matching circuit 111 and the output matching circuit 131, and may include both the input attenuation circuit 116 and the output attenuation circuit 136. The number of input matching circuits 111 included in the input stage 110 may be one or more, the number of input attenuation circuits 116 included in the input stage 110 may be one or more, the number of output matching circuits 131 included in the output stage 130 may be one or more, and the number of output attenuation circuits 136 included in the output stage 130 may be one or more. Unlike illustrating of FIG. 1, the amplification circuit 100 may include only one of the input matching circuit 111 and the output matching circuit 131. In addition, the amplification circuit 100 may include only one of the input attenuation circuit 116 and the output attenuation circuit 136.

FIGS. 2 to 4 are exemplary circuit diagrams of an input attenuation circuit or an output attenuation circuit of FIG. 1. Attenuation circuits 116 b to 116 d may be an example of the input attenuation circuit 116 of FIG. 1, respectively. In addition, the attenuation circuits 116 b to 116 d may be an example of the output attenuation circuit 136 of FIG. 1, respectively.

One end of the attenuation circuit 116 b may be connected to the input matching circuit 111 of the input stage 110 or may be connected to the amplifier 120. The other end of the attenuation circuit 116 b may be connected to a ground voltage. The attenuation circuit 116 b may include an inductor L and a capacitor C that are connected in series with each other. The inductor L and the capacitor C connected in series with each other may form an LC resonance circuit.

One end of the attenuation circuit 116 c may be connected to the input matching circuit 111 of the input stage 110 or may be connected to the amplifier 120. The other end (or ends) of the attenuation circuit 116 c may be connected to the ground voltage. The attenuation circuit 116 c may include the inductor L, the capacitor C, a resistor R₁, and a resistor R₂. Here, the inductor L, the capacitor C, the resistor R₁, and the resistor R₂ may each correspond to the passive element. One end of the resistor R₁ and one end of the capacitor C may be connected in series with each other. The other end of the resistor R₁ may be connected to the ground voltage. One end of the resistor R₂ may be connected to a node n1 that is connected to the other end of the capacitor C and one end of the inductor L. The other end of the resistor R₂ may be connected to the ground voltage. The resistor R₁ and the capacitor C connected in series with each other, and the resistor R₂ may be connected in parallel between the node n1 and the ground voltage.

One end of the attenuation circuit 116 d may be connected to the input matching circuit 111 of the input stage 110 or may be connected to the amplifier 120. The other end (or ends) of the attenuation circuit 116 d may be connected to the ground voltage. The attenuation circuit 116 d may include the inductor L, the capacitor C, the resistor R₁, and the resistor R₂. One end of the resistor R₁ and one end of the inductor L may be connected in series with each other. The other end of the resistor R₁ may be connected to the ground voltage. One end of the resistor R₂ may be connected to a node n2 that is connected to the other end of the inductor L and one end of the capacitor C. The other end of the resistor R₂ may be connected to the ground voltage. The resistor R₁ and the inductor L connected in series with each other, and the resistor R₂ may be connected in parallel between the node n2 and the ground voltage.

Equation 1 may represent an impedance Z₁ of the attenuation circuit 116 b, Equation 2 may represent an impedance Z₂ of the attenuation circuit 116 c, and Equation 3 may represent an impedance Z₃ of the attenuation circuit 116 d.

$\begin{array}{cc}{\mathrm{<figure-callout\; id="1"\; label="Z"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00017.png"\; state="\{\{state\}\}">Z</figure-callout>}}_1=j\omega \left(L-\frac{1}{{\mathrm{<figure-callout\; id="2"\; label="\omega "\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">\omega </figure-callout>}}^{2}C}\right)& \left[\mathrm{Equation}1\right]\\ {\mathrm{<figure-callout\; id="2"\; label="Z"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">Z</figure-callout>}}_2=\frac{{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">R</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="\omega "\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">\omega </figure-callout>}}^2{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">C</figure-callout>}}^2{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00017.png"\; state="\{\{state\}\}">R</figure-callout>}}_1{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\left({\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00017.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_2\right)}{1+{\mathrm{<figure-callout\; id="2"\; label="\omega "\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">\omega </figure-callout>}}^2{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">C</figure-callout>}}^2\left({\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00017.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_2\right)}^2}+j\omega \left(L-\frac{C{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">R</figure-callout>}}_2^2}{\begin{array}{c}1+{\mathrm{<figure-callout\; id="2"\; label="\omega "\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">\omega </figure-callout>}}^2{C}^2\\ {\left({\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00017.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_2\right)}^2\end{array}}\right)& \left[\mathrm{Equation}2\right]\\ {\mathrm{<figure-callout\; id="3"\; label="Z"\; filenames="US11223333-20220111-D00017.png"\; state="\{\{state\}\}">Z</figure-callout>}}_3=\frac{\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00017.png"\; state="\{\{state\}\}">R</figure-callout>}}_1{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\left({\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00017.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_2\right)+\\ {\mathrm{<figure-callout\; id="2"\; label="\omega "\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">\omega </figure-callout>}}^2{\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">L</figure-callout>}}^2{R}_2\end{array}}{\begin{array}{c}{\left({\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00017.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_2\right)}^2+\\ {\mathrm{<figure-callout\; id="2"\; label="\omega "\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">\omega </figure-callout>}}^2{\mathrm{<figure-callout\; id="2"\; label="L"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">L</figure-callout>}}^2\end{array}}+j\omega \left(\frac{L{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">R</figure-callout>}}_2^2}{\begin{array}{c}{\left({\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00017.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_2\right)}^2+\\ {\mathrm{<figure-callout\; id="2"\; label="\omega "\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">\omega </figure-callout>}}^2{L}^2\end{array}}-\frac{1}{{\mathrm{<figure-callout\; id="2"\; label="\omega "\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">\omega </figure-callout>}}^{2}C}\right)& \left[\mathrm{Equation}3\right]\end{array}$

In Equations 1 to 3, L may represent an inductance of the inductor L, C may represent a capacitance of the capacitor C, R₁ may represent a resistance of the resistor R₁, and R₂ may represent the resistance of the resistor R₂.

Equation 4 may represent a resonance frequency f_r1 at which the imaginary part of the impedance Z₁ of the attenuation circuit 116 b becomes 0, Equation 5 may represent a resonance frequency f_r2 at which the imaginary part of the impedance Z₂ of the attenuation circuit 116 c becomes 0, and Equation 6 may represent a resonance frequency f_r3 at which the imaginary part of the impedance Z₃ of the attenuation circuit 116 d becomes 0.

$\begin{array}{cc}{f}_{r1}=\frac{1}{2\pi \sqrt{LC}}& \left[\mathrm{Equation}4\right]\\ f_{r2}=\frac{1}{2\pi \left({\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00017.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_2\right)}\sqrt{\frac{C{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">R</figure-callout>}}_2^2-L}{L{C}^2}}& \left[\mathrm{Equation}5\right]\\ f_{r3}=\frac{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00017.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">R</figure-callout>}}_2}{2\pi \sqrt{L\left({\mathrm{<figure-callout\; id="2"\; label="CR"\; filenames="US11223333-20220111-D00004.png,US11223333-20220111-D00006.png"\; state="\{\{state\}\}">CR</figure-callout>}}_2^2-L\right)}}& \left[\mathrm{Equation}6\right]\end{array}$

Unlike the attenuation circuit 116 b, the attenuation circuits 116 c and 116 d may further include the resistors R₁ and R₂. Referring to Equation 5 and Equation 6, the resistance of the resistor R₂ may be limited by the inductance of the inductor L and the capacitance of the capacitor C (e.g., C·R₂ ²−L>0).

Referring to FIG. 2 and Equation 4, the attenuation circuit 116 b may provide the impedance Z₁ that is theoretically zero at the resonance frequency f_r1. In practice, since the inductor L, the capacitor C, the transmission line, etc. may have parasitic resistance components, the impedance Z₁ at the resonance frequency f_r1 may be very small, but may not be zero. At the resonance frequency f_r1, most of the input signal may flow to the ground voltage through the attenuation circuit 116 b, and the input signal may hardly be transmitted to the amplifier 120. The attenuation circuit 116 b may attenuate the gain for the input signal at the resonance frequency f_r1 and the peripheral frequency of the resonance frequency f_r1. For example, the resonance frequency f_r1 that is determined based on the inductance of the inductor L and the capacitance of the capacitor C may be located outside the operating frequency band of the amplification circuit 100. To obtain the resonance frequency f_r1 lower than the operating frequency band, a relatively large inductor L and capacitor C may be required. To obtain the resonance frequency f_r1 higher than the operating frequency band, a relatively small inductor L and capacitor C may be required. When the gain for the input signal is attenuated by using the attenuation circuit 116 b, a size of the inductor L and a size of the capacitor C may be restricted such that the resonance frequency f_r1 is located outside the operating frequency band. As described above, the attenuation circuit 116 b provides the impedance Z₁ that is theoretically zero at the resonance frequency f_r1. Since a degree to which the gain of the input signal is attenuated at the resonance frequency f_r1 may be very large, the attenuation circuit 116 b may attenuate the gain for the input signal not only outside the operating frequency band but also within the operating frequency band. Such gain attenuation is difficult to adjust even when the size of the inductor L or the capacitor C is adjusted.

Referring to FIG. 3, Equation 2, and Equation 5, the attenuation circuit 116 c may provide an impedance Z₂ that is greater than the impedance Z₁ of the resonance frequency f_r1 at the resonance frequency f_r2 and corresponds to a real part of Equation 2. Compared to the attenuation circuit 116 b, the impedance Z₂ at the resonance frequency f_r2 may be adjusted, varied, or changed by the resistances of the resistors R₁ and R₂. Since the impedance Z₂ at the resonance frequency f_r2 is adjusted by the resistances of the resistors R₁ and R₂, the degree to which the gain for the input signal is attenuated by the attenuation circuit 116 c may also be adjusted by the resistances of the resistors R₁ and R₂.

Referring to FIG. 4, Equation 3, and Equation 6, the attenuation circuit 116 d may provide the impedance Z₃ that is greater than the impedance Z₃ of the resonance frequency f_r1 at the resonance frequency f_r3 and corresponds to the real part of Equation 3. Compared to the attenuation circuit 116 b, the impedance Z₃ at the resonance frequency f_r3 may be adjusted, varied, or changed by the resistances of the resistors R₁ and R₂. Since the impedance Z₃ at the resonance frequency f_r3 is adjusted by the resistances of the resistors R₁ and R₂, the degree to which the gain for the input signal is attenuated by the attenuation circuit 116 d may also be adjusted by the resistances of the resistors R₁ and R₂.

Unlike the attenuation circuit 116 b, each of the attenuation circuits 116 c and 116 d may include resistors R₁ and R₂. By adjusting the resistances of the resistors R₁ and R₂, the degree to which the gain for the input signal is attenuated may be adjusted by the attenuation circuits 116 c and 116 d. In addition, by adjusting the resistances of the resistors R₁ and R₂, the resonance frequencies f_r2 and f_r3 may be located outside the operating frequency band of the amplification circuit 100. Accordingly, size constraints of the inductor L and the capacitor C of the attenuation circuit 116 b described above may be resolved or alleviated by the resistors R₁ and R₂. Compared to the attenuation circuit 116 b, the degree to which the gain for the input signal is attenuated and the resonance frequencies f_r2 and f_r3 may be adjusted by adjusting the resistance of at least one of the resistors R₁ and R₂ of the attenuation circuits 116 c and 116 d.

For example, due to the resistors R1 and R2 of the impedances Z₂ and Z₃ of Equations 5 and 6, a frequency having a minimum impedance Z₂ may be similar to or different from the resonance frequency f_r2. A frequency having a minimum impedance Z₃ may be similar to or different from the resonance frequency f_r3. In contrast, a frequency having the smallest impedance Z₁ may be the resonance frequency f_r1.

FIG. 5 is an exemplary graph of impedances of attenuation circuits of FIGS. 2 to 4. A horizontal axis may represent a frequency, and a vertical axis may represent a magnitude of an impedance. In FIG. 5, the inductance of the inductor L is 5 nH, the capacitance of the capacitor C is 50 fF, the resistance of the resistor R₁ is 1Ω or 10Ω, and the resistance of the resistor R₂ may be 2 kΩ or 20 kΩ.

When the inductance of the inductor L is 5 nH and the capacitance of the capacitor C is 50 fF, the resonance frequency f_r1 is about 10 GHz and a magnitude |Z₁| of an impedance at the resonance frequency f_r1 is about 1.3 E-7Ω. The magnitude |Z₁| of an impedance at the resonance frequency f_r1 may be relatively less than the magnitude |Z₁| of the impedance at different frequencies.

When the inductance of the inductor L is 5 nH, the capacitance of the capacitor C is 50 fF, the resistance of the resistor R₁ is 1Ω, and the resistance of the resistor R₂ is 2 kΩ, the resonance frequencies f_r2 and f_r3 may each be about 10 GHz, and the magnitudes |Z₂| and |Z₃| of the impedances at the resonance frequencies f_r2 and f_r3 may each be about 50Ω. When the inductance of the inductor L is 5 nH, the capacitance of the capacitor C is 50 fF, the resistance of the resistor R₁ is 10Ω, and the resistance of the resistor R₂ is 20 kΩ, the resonance frequencies f_r2 and f_r3 may each be about 10 GHz, and the magnitudes |Z₂| and |Z₃| of the impedances at the resonance frequencies f_r2 and f_r3 may each be about 15Ω. When the inductance of the inductor L is 5 nH, the capacitance of the capacitor C is 50 fF, the resistance of the resistor R₁ is 1Ω, and the resistance of the resistor R₂ is 20 kΩ2, the resonance frequencies f_r2 and f_r3 may each be about 10 GHz, and the magnitudes |Z₂| and |Z₃| of the impedances at the resonance frequencies f_r2 and f_r3 may each be about 6Ω. The magnitudes |Z₂| and |Z₃| of the impedances at the resonance frequencies f_r2 and f_r3 may be relatively less than the magnitudes |Z₂| and |Z₃| of the impedances at different frequencies.

The attenuation circuit 116 b may provide the impedance Z₁ that is close to zero at the resonance frequency f_r1, most components of the input signal may flow to the ground voltage through the attenuation circuit 116 b, and there are almost no components of the input signal transmitted to the amplifier 120. In contrast, when the resistances of the resistors R₁ and R₂ are adjusted, the attenuation circuits 116 c and 116 d may variously provide the magnitudes |Z₂| and |Z₃| of the impedances at resonance frequencies f_r2 and f_r3 to about 6 to 50Ω, may adjust an amount (magnitude) of the input signal flowing to the ground voltage through the attenuation circuit 116 b and an amount (magnitude) of the input signal transferred to the amplifier 120. The attenuation circuits 116 c and 116 d may adjust the gain for the input signal, and may adjust the degree to which the gain for the input signal is attenuated.

FIG. 6A is a graph illustrating a magnitude of an impedance of an attenuation circuit of FIG. 2 and a magnitude of an impedance of an attenuation circuit of FIG. 3. A horizontal axis represents a frequency and a vertical axis represents a magnitude of an impedance. FIG. 6B is a graph of frequency in which an attenuation circuit of FIG. 3 has the smallest impedance magnitude. A horizontal axis represents the resistance of the resistor R₂, and a vertical axis represents a frequency.

Referring to FIG. 6A, when the inductance of the inductor L is 5 nH and the capacitance of the capacitor C is 50 fF, the resonance frequency f_r1 is about 10 GHz and a magnitude |Z₁| of the impedance at the resonance frequency f_r1 may be close to zero. When the inductance of the inductor L is 5 nH, the capacitance of the capacitor C is 50 fF, the resistance of the resistor R₁ is 10Ω, and the resistance of the resistor R₂ is 2 kΩ, 400 Ω, 300Ω, and 220Ω, the attenuation circuit 116 c may have various resonance frequencies f_r2 depending on the resistor R₂ and various impedance magnitudes |Z₂|. Referring to FIG. 6B, as the resistance of the resistor R₂ decreases, a frequency at which the magnitude |Z₂| of the impedance is minimum or the resonance frequency f_r2 may also decrease.

FIG. 7A is a graph illustrating a magnitude of an impedance of an attenuation circuit of FIG. 2 and a magnitude of an impedance of an attenuation circuit of FIG. 4. A horizontal axis represents a frequency and a vertical axis represents a magnitude of an impedance. FIG. 7B is a graph of frequency in which an attenuation circuit of FIG. 4 has the smallest impedance magnitude. A horizontal axis represents the resistance of the resistor R₂, and a vertical axis represents a frequency.

Referring to FIG. 7A, when the inductance of the inductor L is 5 nH and the capacitance of the capacitor C is 50 fF, the resonance frequency f_r1 is about 10 GHz and the magnitude |Z₁| of the impedance at the resonance frequency f_r1 may be close to zero. When the inductance of the inductor L is 5 nH, the capacitance of the capacitor C is 50 fF, the resistance of the resistor R₁ is 10Ω, and the resistance of the resistor R₂ is 2 kΩ, 400 Ω, 300Ω, and 220Ω, the attenuation circuit 116 d may have various resonance frequencies f_r3 depending on the resistor R₂ and various impedance magnitudes |Z₃|. Referring to FIG. 7B, as the resistance of the resistor R₂ decreases, a frequency at which the magnitude |Z₃| of the impedance is minimum or the resonance frequency f_r3 may also increase.

Various values in FIGS. 5 to 7B are presented by way of example, but the scope of the inventive concept is not limited to the above-described values.

FIGS. 8A to 8G are exemplary block diagrams of an amplification circuit of FIG. 1, respectively. Amplification circuits 100 a to 100 g of FIGS. 8A to 8G may be examples of the amplification circuit 100 of FIG. 1, respectively.

Referring to FIG. 8A, the amplification circuit 100 a may include an input stage 110 a, the amplifier 120, an output stage 130 a, an input terminal 141 receiving an input signal, and an output terminal 142 outputting an output signal. The amplification circuit 100 a may not include the input attenuation circuit 116 and the output attenuation circuit 136 of FIG. 1.

The input stage 110 a may include a first input matching circuit 111 connected between the input terminal 141 and a node n3 and a second input matching circuit 112 connected between the node n3 and the amplifier 120. Each of the first input matching circuit 111 and the second input matching circuit 112 may be substantially the same as the input matching circuit 111 of FIG. 1. The first input matching circuit 111 and the second input matching circuit 112 may be the same as or different from each other. The number of input matching circuits included in the input stage 110 a is not limited to that illustrated in FIG. 8A and may be one or more. As described above in FIG. 1, the amplifier 120 may include a transistor. The transistor may include a terminal connected to the input stage 110 a, a terminal connected to the ground voltage, and a terminal connected to the output stage 130 a. The output stage 130 a may include a first output matching circuit 131 connected between the amplifier 120 and a node n4 and a second output matching circuit 132 connected between the node n4 and the output terminal 142. Each of the first output matching circuit 131 and the second output matching circuit 132 may be substantially the same as the output matching circuit 131 of FIG. 1. The first output matching circuit 131 and the second output matching circuit 132 may be the same as or different from each other. The number of output matching circuits included in the output stage 130 a is not limited to that illustrated in FIG. 8A and may be one or more.

A difference between the amplification circuit 100 b in FIG. 8B and the amplification circuit 100 a in FIG. 8A will be mainly described. Compared to the amplification circuit 100 a, an input stage 110 b may further include the input attenuation circuit 116 b, and an output stage 130 b may further include an output attenuation circuit 136 b. Each of the input attenuation circuit 116 b and the output attenuation circuit 136 b may be the attenuation circuit 116 b of FIG. 2. The input attenuation circuit 116 b may be connected between the node n3 and the ground voltage. The input attenuation circuit 116 b may provide the above-described impedance Z₁ to the input signal that passes through the node n3 or the first input matching circuit 111. The output attenuation circuit 136 b may be connected between the node n4 and the ground voltage. The output attenuation circuit 136 b may provide the above-described impedance Z₁ to the amplified signal that passes through the node n4 or the first output matching circuit 131. The input attenuation circuit 116 b and the output attenuation circuit 136 b may attenuate the gain for the input signal outside the operating frequency band of the amplification circuit 100 b, respectively. The amplification circuit 100 b may attenuate the gain for the input signal to a maximum at a frequency at which the magnitude |Z₁| of the impedance of the input attenuation circuit 116 b is minimum, and the amplification circuit 100 b may attenuate the gain of the input signal to a maximum at a frequency at which the magnitude |Z₁| of the impedance of the output attenuation circuit 136 b is minimum.

In an embodiment, the inductance of the input attenuation circuit 116 b may be the same as or different from the inductance of the output attenuation circuit 136 b. The capacitance of the input attenuation circuit 116 b may be the same as or different from the capacitance of the output attenuation circuit 136 b. The magnitude |Z₁| of the impedance of the input attenuation circuit 116 b may be the same as or different from the magnitude |Z₁| of the impedance of the output attenuation circuit 136 b. The frequency at which the magnitude |Z₁| of the impedance of the input attenuation circuit 116 b becomes minimum may be the same as or different from the frequency at which the magnitude |Z₁| of the impedance of the output attenuation circuit 136 b becomes minimum. The degree to which the gain for the input signal is attenuated by the input attenuation circuit 116 b may be the same as or different from the degree to which the gain for the input signal is attenuated by the output attenuation circuit 136 b.

A difference between the amplification circuit 100 c of FIG. 8C and the amplification circuit 100 b of FIG. 8B will be mainly described. An input stage 110 c may include the input attenuation circuit 116 c instead of the input attenuation circuit 116 b. An output stage 130 c may include an output attenuation circuit 136 c instead of the output attenuation circuit 136 b. Each of the input attenuation circuit 116 c and the output attenuation circuit 136 c may be the attenuation circuit 116 c of FIG. 3. The input attenuation circuit 116 c may provide the above-described impedance Z₂ to the input signal that passes through the node n3 or the first input matching circuit 111. The output attenuation circuit 136 c may provide the above-described impedance Z₂ to the amplified signal that passes through the node n4 or the first output matching circuit 131. The input attenuation circuit 116 c and the output attenuation circuit 136 c may attenuate the gain for the input signal outside the operating frequency band of the amplification circuit 100 c, respectively. The amplification circuit 100 c may attenuate the gain for the input signal to a maximum at the frequency at which the magnitude |Z₂| of the impedance of the input attenuation circuit 116 c becomes minimum, and the amplification circuit 100 c may attenuate the gain of the input signal to a maximum at the frequency at which the magnitude |Z₂| of the impedance of the output attenuation circuit 136 c becomes minimum.

In an embodiment, the inductance of the input attenuation circuit 116 c may be the same as or different from the inductance of the output attenuation circuit 136 c. The capacitance of the input attenuation circuit 116 c may be the same as or different from the capacitance of the output attenuation circuit 136 c. The resistance of the resistor R₁ of the input attenuation circuit 116 c may be the same as or different from the resistance of the resistor R₁ of the output attenuation circuit 136 c. The resistance of the resistor R₂ of the input attenuation circuit 116 c may be the same as or different from the resistance of the resistor R₂ of the output attenuation circuit 136 c. The magnitude |Z₂| of the impedance of the input attenuation circuit 116 c may be the same as or different from the magnitude |Z₂| of the impedance of the output attenuation circuit 136 c. The frequency at which the magnitude |Z₂| of the impedance of the input attenuation circuit 116 c becomes minimum may be the same as or different from the frequency at which the magnitude |Z₂| of the impedance of the output attenuation circuit 136 c becomes the minimum. The degree to which the gain for the input signal is attenuated by the input attenuation circuit 116 c may be the same as or different from the degree to which the gain for the input signal is attenuated by the output attenuation circuit 136 c.

A difference between the amplification circuit 100 d in FIG. 8D and the amplification circuit 100 b in FIG. 8B will be mainly described. An input stage 110 d may include the input attenuation circuit 116 d instead of the input attenuation circuit 116 b. An output stage 130 d may include an output attenuation circuit 136 d instead of the output attenuation circuit 136 b. Each of the input attenuation circuit 116 d and the output attenuation circuit 136 d may be the attenuation circuit 116 d of FIG. 4. The input attenuation circuit 116 d may provide the above-described impedance Z₃ to the input signal that passes through the node n3 or the first input matching circuit 111. The output attenuation circuit 136 d may provide the above-described impedance Z₃ to the amplified signal that passes through the node n4 or the first output matching circuit 131. The input attenuation circuit 116 d and the output attenuation circuit 136 d may attenuate the gain for the input signal outside the operating frequency band of the amplification circuit 100 d, respectively. The amplification circuit 100 d may attenuate the gain for the input signal to a maximum at a frequency at which the magnitude |Z₃| of the impedance of the input attenuation circuit 116 d becomes minimum, and the amplification circuit 100 d may attenuate the gain of the input signal to a maximum at the frequency at which the magnitude |Z₃| of the impedance of the output attenuation circuit 136 d becomes minimum.

In an embodiment, the inductance of the input attenuation circuit 116 d may be the same as or different from the inductance of the output attenuation circuit 136 d. The capacitance of the input attenuation circuit 116 d may be the same as or different from the capacitance of the output attenuation circuit 136 d. The resistance of the resistor R₁ of the input attenuation circuit 116 d may be the same as or different from the resistance of the resistor R₁ of the output attenuation circuit 136 d. The resistance of the resistor R₂ of the input attenuation circuit 116 d may be the same as or different from the resistance of the resistor R₂ of the output attenuation circuit 136 d. The magnitude |Z₃| of the impedance of the input attenuation circuit 116 d may be the same as or different from the magnitude |Z₃| of the impedance of the output attenuation circuit 136 d. The frequency at which the magnitude |Z₃| of the impedance of the input attenuation circuit 116 d becomes minimum may be the same as or different from the frequency at which the magnitude |Z₃| of the impedance of the output attenuation circuit 136 d becomes the minimum. The degree to which the gain for the input signal is attenuated by the input attenuation circuit 116 d may be the same as or different from the degree to which the gain for the input signal is attenuated by the output attenuation circuit 136 d.

A difference between the amplification circuit 100 e of FIG. 8E and the amplification circuit 100 b of FIG. 8B will be mainly described. An input stage 110 e may include the input attenuation circuit 116 c instead of the input attenuation circuit 116 b. An output stage 130 e may include the output attenuation circuit 136 d instead of the output attenuation circuit 136 b. The input attenuation circuit 116 c may be the attenuation circuit 116 c of FIG. 3, and the output attenuation circuit 136 d may be the attenuation circuit 116 d of FIG. 4. The input attenuation circuit 116 c may provide the above-described impedance Z₂ to the input signal that passes through the node n3 or the first input matching circuit 111. The output attenuation circuit 136 d may provide the above-described impedance Z₃ to the amplified signal that passes through the node n4 or the first output matching circuit 131. The input attenuation circuit 116 c and the output attenuation circuit 136 d may attenuate the gain for the input signal outside the operating frequency band of the amplification circuit 100 e, respectively. The amplification circuit 100 e may attenuate the gain for the input signal to a maximum at the frequency at which the magnitude |Z₂| of the impedance of the input attenuation circuit 116 c becomes minimum, and the amplification circuit 100 e may attenuate the gain of the input signal to a maximum at the frequency at which the magnitude |Z₃| of the impedance of the output attenuation circuit 136 d becomes minimum.

In an embodiment, the inductance, the capacitance, and the resistance of the input attenuation circuit 116 c may be set to various values. The inductance, capacitance, and resistance of the output attenuation circuit 136 d may be set to various values. The magnitude |Z₂| of the impedance of the input attenuation circuit 116 c may be the same as or different from the magnitude |Z₃| of the impedance of the output attenuation circuit 136 d. The frequency at which the magnitude |Z₂| of the impedance of the input attenuation circuit 116 c becomes the minimum may be the same as or different from the frequency at which the magnitude |Z₃| of the impedance of the output attenuation circuit 136 d is the minimum. The degree to which the gain for the input signal is attenuated by the input attenuation circuit 116 c may be the same as or different from the degree to which the gain for the input signal is attenuated by the output attenuation circuit 136 d.

A difference between the amplification circuit 100 f of FIG. 8F and the amplification circuit 100 b of FIG. 8B will be mainly described. An input stage 110 f may include the input attenuation circuit 116 d instead of the input attenuation circuit 116 b. An output stage 130 f may include the output attenuation circuit 136 c instead of the output attenuation circuit 136 b. The input attenuation circuit 116 d may be the attenuation circuit 116 d of FIG. 4, and the output attenuation circuit 136 c may be the attenuation circuit 116 c of FIG. 3. The input attenuation circuit 116 d may provide the above-described impedance Z₃ to the input signal that passes through the node n3 or the first input matching circuit 111. The output attenuation circuit 136 c may provide the above-described impedance Z₂ to the amplified signal that passes through the node n4 or the first output matching circuit 131. The input attenuation circuit 116 d and the output attenuation circuit 136 c may attenuate the gain for the input signal outside the operating frequency band of the amplification circuit 100 f, respectively. The amplification circuit 100 f may attenuate the gain for the input signal to a maximum at the frequency at which the magnitude |Z₃| of the impedance of the input attenuation circuit 116 d becomes minimum. The amplification circuit 100 f may attenuate the gain of the input signal to a maximum at the frequency at which the magnitude |Z₂| of the impedance of the output attenuation circuit 136 c becomes minimum.

In an embodiment, the inductance, the capacitance, and the resistance of the input attenuation circuit 116 d may be set to various values. The inductance, the capacitance, and the resistance of the output attenuation circuit 136 c may be set to various values. The magnitude |Z₃| of the impedance of the input attenuation circuit 116 d may be the same as or different from the magnitude |Z₂| of the impedance of the output attenuation circuit 136 c. The frequency at which the magnitude |Z₃| of the impedance of the input attenuation circuit 116 d becomes minimum may be the same as or different from the frequency at which the magnitude |Z₂| of the impedance of the output attenuation circuit 136 c becomes minimum. The degree to which the gain for the input signal is attenuated by the input attenuation circuit 116 d may be the same as or different from the degree to which the gain for the input signal is attenuated by the output attenuation circuit 136 c.

A difference among the amplification circuit 100 g of FIG. 8G and the amplification circuits 100 b to 100 f of FIGS. 8B to 8F will be mainly described. An input stage 110 g may be one of the input stages 110 b to 110 f. An output stage 130 g may be one of the output stages 130 b to 130 f The amplification circuit 100 g may further include a voltage generator 150 g. The voltage generator 150 g may be supplied with a power supply voltage and the ground voltage, and may generate bias voltages VB1 and VB2, based on the power supply voltage and the ground voltage. The voltage generator 150 g may supply the bias voltage VB1 to a terminal of a transistor that is connected to the first output matching circuit 131. The voltage generator 150 g may supply the bias voltage VB2 to a terminal of a transistor that is connected to the second input matching circuit 112. Although not illustrated, the voltage generator 150 g may further supply various bias voltages to arbitrary nodes (e.g., n1 to n4, etc.) of the amplification circuit 100 g.

FIGS. 9A and 9B are graphs illustrating gains for input signals by amplification circuits of FIGS. 8A to 8C. A horizontal axis may represent a frequency, and a vertical axis may represent a gain in dB. In FIG. 9A, a range of the gain corresponds to −100 to 10 dB, and in FIG. 9B, a range of the gain corresponds to −10 to 6 dB.

In FIG. 9A and FIG. 9B, the operating frequency range of the amplification circuits 100 a to 100 c may be 70 to 100 GHz. The amplification circuit 100 a may have the gain of about 4.3 to 5.5 dB within the operating frequency range. The amplification circuit 100 a may have a gain of about 6 dB at a frequency of 50 GHz that is located outside the operating frequency range. The amplification circuit 100 a may have a gain of about 0.5 to 1.7 dB greater than the gain within the operating frequency range at a frequency of 50 GHz. This is because the transistor of the amplifier 120, which is an active element, exhibits a relatively high gain at a relatively low frequency and a relatively low gain at a relatively high frequency. The gain for the input signal outside the operating frequency range is an undesired gain, which may cause deterioration of the communication system and additional circuitry such as filters. Various attenuation circuits described above in FIGS. 2 to 8G may be used to attenuate the gain for the input signal outside the operating frequency range.

The amplification circuit 100 b may include the input attenuation circuit 116 b and the output attenuation circuit 136 b. The amplification circuit 100 b may attenuate the gain by about 105 dB at a frequency of 50 GHz compared to the amplification circuit 100 a by using the input attenuation circuit 116 b and the output attenuation circuit 136 b. Since the input attenuation circuit 116 b and the output attenuation circuit 136 b do not include the resistors R₁ and R₂, the degree (about 105 dB) to which the gain for the input signal is attenuated outside the operating frequency range may not be adjusted. As the gain is rapidly attenuated at a frequency of 50 GHz, the input attenuation circuit 116 b and the output attenuation circuit 136 b may attenuate the gain even within the operating frequency range. The amplification circuit 100 b may attenuate the gain by about 8.5 dB at a frequency of 70 GHz compared to the amplification circuit 100 a.

The amplification circuit 100 c may include the input attenuation circuit 116 c and the output attenuation circuit 136 c. The amplification circuit 100 c may attenuate the gain by about 3 dB at a frequency of 50 GHz compared to the amplification circuit 100 a by using the input attenuation circuit 116 c and the output attenuation circuit 136 c. Since the input attenuation circuit 116 c and the output attenuation circuit 136 c include the resistors R₁ and R₂, the degree to which the gain of the input signal is attenuated outside the operating frequency range may be adjusted (i.e., adjusted from 105 dB attenuation to 3 dB attenuation). The amplification circuit 100 c may attenuate the gain by about 2 dB at a frequency of 70 GHz compared to the amplification circuit 100 a, but the amplification circuit 100 c may have a gain of about 3.5 to 4.5 dB within the operating frequency range similar to the amplification circuit 100 a. The amplification circuit 100 c may adjust the degree of attenuating the gain outside the operating frequency range by using the input attenuation circuit 116 c and the output attenuation circuit 136 c. As at least one of the resistances of the resistors R₁ and R₂ of the input attenuation circuit 116 c and the output attenuation circuit 136 c is adjusted, the degree to which the gain in the operating frequency range is attenuated may be minimized, and the gain outside the operating frequency range may be made less than the gain within the operating frequency range. Other amplification circuits 100 d to 100 f not illustrated in FIGS. 9A and 9B may also have aforementioned advantages of the amplification circuit 100 c.

In FIGS. 9A and 9B, various values are given by way of example, but the scope of the inventive concept is not limited to the above-described values.

FIG. 10 is an exemplary block diagram of an amplification circuit according to another embodiment of the inventive concept. An amplification circuit 200 may include first to n-th amplification stages 211 to 21 n (where “n” is a natural number of 2 or more). The first amplification stage 211 may receive the input signal, and the n-th amplification stage 21 n may output the amplified signal as the output signal. In FIG. 1 to FIG. 9B, the amplification circuit 100 is described as one stage, but as illustrated in FIG. 10, the amplification circuit 200 may include multiple stages.

In an embodiment, each of the first to n-th amplification stages 211 to 21 n may include the input stage 110, the amplifier 120, and the output stage 130 described above with reference to FIGS. 1 to 9B. In another embodiment, the first amplification stage 211 may include only the input stage 110 and the amplifier 120 described above with reference to FIGS. 1 to 9B. The second amplification stage 212 may include only the amplifier 120 described above with reference to FIGS. 1 to 9B. The n-th amplification stage 21 n may include only the amplifier 120 and the output stage 130 described above with reference to FIGS. 1 to 9B. Matching circuits (refer to circuits 111, 112, 131, and 132 in FIGS. 1 to 9B) may not be disposed among the first to n-th amplification stages 211 to 21 n, or one or more matching circuits may be disposed.

FIG. 11 is an exemplary block diagram of a transmitter to which an amplification circuit according to an embodiment of the inventive concept is applied. A transmitter 1000 may include an oscillator 1100, a mixer 1200, a filter 1300, an amplification circuit 1400, and an antenna 1500.

The oscillator 1100 may generate a frequency for frequency synthesis and may provide the frequency to the mixer 1200. The mixer 1200 may convert a transmission signal of the intermediate frequency (IF) band into a signal of a high frequency band or an RF band by using the frequency that is provided from the oscillator 1100 (frequency up-conversion). The filter 1300 may perform a filtering operation on the signal converted by the mixer 1200 to pass only a desired frequency component. The amplification circuit 1400 as a driving amplifier or a power amplifier may amplify a signal that passes through the filter 1300. For example, the amplification circuit 1400 may include the amplification circuit 100 and/or 200 described above with reference to FIGS. 1 to 10. The antenna 1500 may receive the amplified signal from the amplification circuit 1400, may convert the received signal into an electromagnetic wave signal, and may output the electromagnetic wave signal.

FIG. 12 is an exemplary block diagram of a receiver to which an amplification circuit according to an embodiment of the inventive concept is applied. A receiver 2000 may include an antenna 2100, an amplification circuit 2200, a filter 2300, an oscillator 2400, and a mixer 2500.

The antenna 2100 may receive the electromagnetic wave signal, may convert the received signal into an electrical signal, and may provide the converted signal to the amplification circuit 2200. The amplification circuit 2200 as a low noise amplifier may amplify a signal provided from the antenna 2100. For example, the amplification circuit 2200 may include the amplification circuit 100 and/or 200 described above with reference to FIGS. 1 to 10. The filter 2300 may perform a filtering operation on the signal amplified by the amplification circuit 2200 to pass only a desired frequency component. The oscillator 2400 may generate a frequency for frequency synthesis and may provide the frequency to the mixer 2500. The mixer 2500 may convert a frequency band of a signal that passes through the filter 2300 into an intermediate frequency (IF) band by using the frequency that is provided from the oscillator 2400 (frequency down-conversion). The mixer 2500 may output the converted signal as a received signal.

FIG. 13 is an exemplary block diagram of a transceiver to which an amplification circuit according to an embodiment of the inventive concept is applied. A transceiver 3000 may include an oscillator 3100, a mixer 3200, a filter 3300, an amplification circuit 3400, an antenna 3500, an amplification circuit 3600, a filter 3700, a mixer 3800, and a transmission/reception switch 3900.

The oscillator 3100, the mixer 3200, the filter 3300, the amplification circuit 3400, and the antenna 3500 may be similar to the oscillator 1100, the mixer 1200, the filter 1300, the amplification circuit 1400, and the antenna 1500 that are illustrated in FIG. 11, respectively. The antenna 3500, the amplification circuit 3600, the filter 3700, the oscillator 3100, and the mixer 3800 may be similar to the antenna 2100, the amplification circuit 2200, the filter 2300, and the oscillator 2400, and mixer 2500 that are illustrated in FIG. 12, respectively. The oscillator 3100 may generate a frequency used by the mixer 3200 and a frequency used by the mixer 3800, respectively, or may generate the frequency in common when both are the same. The antenna 3500 may convert a signal amplified by the amplification circuit 3400 into an electromagnetic wave signal and may output the signal, or may receive an electromagnetic wave signal and may provide the received signal to the amplification circuit 3600. The transmission/reception switch 3900 may be connected to the antenna 3500. The transmission/reception switch 3900 may branch a transmitter including the oscillator 3100, the mixer 3200, the filter 3300, and the amplification circuit 3400 and a receiver including the amplification circuit 2200, the filter 2300, the oscillator 2400, and the mixer 2500. The transmission/reception switch 3900 may include a filter that passes the frequency of the transmitter and a filter that passes the frequency of the receiver.

According to an embodiment of the inventive concept, a microwave amplification circuit capable of adjusting a degree of attenuation of a gain for an input signal may be provided.

The contents described above are specific embodiments for implementing the inventive concept. The inventive concept may include not only the embodiments described above but also embodiments in which a design is simply or easily capable of being changed. In addition, the inventive concept may also include technologies easily changed to be implemented using embodiments.

Claims (14)

What is claimed is:

1. An amplification circuit for amplifying an input signal comprising:

an input stage including an input matching circuit configured to receive the input signal and an input attenuation circuit configured to attenuate a gain for the input signal outside an operating frequency band of the amplification circuit;

a transistor configured to amplify the input signal provided from the input stage; and

an output stage including an output matching circuit configured to receive a signal amplified by the transistor and an output attenuation circuit configured to attenuate the gain for the input signal outside the operating frequency band of the amplification circuit, and

wherein the input attenuation circuit includes a first resistor and a second resistor that are respectively connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor, and

wherein the first passive element is one of an inductor and a capacitor, and the second passive element is another one of the inductor and the capacitor.

2. The amplification circuit of claim 1, wherein the output attenuation circuit includes a third resistor and a fourth resistor that are respectively connected to the ground voltage, a third passive element connected between the output matching circuit and the fourth resistor, and a fourth passive element connected between the third passive element and the third resistor, and

wherein the third passive element is one of the inductor and the capacitor, and the fourth passive element is another one of the inductor and the capacitor.

3. The amplification circuit of claim 2, wherein the first resistor and the second passive element which are connected in series with each other and the second resistor are connected in parallel between the ground voltage and the first passive element, and

wherein the third resistor and the fourth passive element which are connected in series with each other and the fourth resistor are connected in parallel between the ground voltage and the third passive element.

4. The amplification circuit of claim 2, wherein a first frequency at which the input attenuation circuit has a first minimum impedance is adjusted by the first passive element, the second passive element, the first resistor, and the second resistor, and

wherein a second frequency at which the output attenuation circuit has a second minimum impedance is adjusted by the third passive element, the fourth passive element, the third resistor, and the fourth resistor.

5. The amplification circuit of claim 4, wherein the input attenuation circuit is configured to attenuate the gain for the input signal at the first frequency to a maximum, and

wherein the output attenuation circuit is configured to attenuate the gain for the input signal at the second frequency to a maximum.

6. The amplification circuit of claim 4, wherein a first resonance frequency of the input attenuation circuit is different from the first frequency, and

wherein a second resonance frequency of the output attenuation circuit is different from the second frequency.

7. The amplification circuit of claim 2, wherein the input matching circuit is a first input matching circuit,

wherein the output matching circuit is a first output matching circuit,

wherein the input stage further includes a second input matching circuit connected between the first input matching circuit and the transistor, and

wherein the output stage further includes a second output matching circuit connected to both the first output matching circuit and the output attenuation circuit.

8. The amplification circuit of claim 7, wherein the input attenuation circuit is connected between a first node that is connected to both the first input matching circuit and the second input matching circuit and the ground voltage, and

wherein the output attenuation circuit is connected between a second node that is connected to both the first output matching circuit and the second output matching circuit and the ground voltage.

9. The amplification circuit of claim 1, wherein the transistor includes a first terminal connected to the input stage, a second terminal connected to the ground voltage, and a third terminal connected to the output stage.

10. An amplification circuit comprising:

a first amplification stage that receives an input signal; and

a second amplification stage connected in series with the first amplification stage, and

wherein the first amplification stage includes:

an input stage including an input matching circuit configured to receive the input signal and an input attenuation circuit configured to attenuate a gain for the input signal outside an operating frequency band of the amplification circuit; and

a first transistor configured to amplify the input signal provided from the input stage,

wherein the input attenuation circuit includes a first resistor and a second resistor connected respectively to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor, and

wherein the first passive element is one of an inductor and a capacitor, and the second passive element is another one of the inductor and the capacitor.

11. The amplification circuit of claim 10, wherein the second amplification stage includes a second transistor configured to amplify an intermediate signal that is provided from the first amplification stage.

12. The amplification circuit of claim 11, further comprising:

a third amplification stage connected in series with the second amplification stage.

13. The amplification circuit of claim 11, wherein the second amplification stage further includes an output stage including an output matching circuit configured to receive a signal amplified by the second transistor and an output attenuation circuit configured to attenuate the gain for the input signal outside the operating frequency band of the amplification circuit.

14. The amplification circuit of claim 13, wherein the output attenuation circuit includes a third resistor and a fourth resistor connected respectively to the ground voltage, a third passive element connected between the output matching circuit and the fourth resistor, and a fourth passive element connected between the third passive element and the third resistor, and

wherein the third passive element is one of the inductor and the capacitor, and the fourth passive element is another one of the inductor and the capacitor.

Images