US11043575B2 - Field-effect transistor and fabrication method of field-effect transistor - Google Patents

Field-effect transistor and fabrication method of field-effect transistor Download PDF

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US11043575B2
US11043575B2 US16/417,544 US201916417544A US11043575B2 US 11043575 B2 US11043575 B2 US 11043575B2 US 201916417544 A US201916417544 A US 201916417544A US 11043575 B2 US11043575 B2 US 11043575B2
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semiconductor material
material layer
layer
gate
effect transistor
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Xiaolong Ma
Riqing Zhang
Stephane BADEL
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Huawei Technologies Co Ltd
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    • H01L29/66545—
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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    • H01L29/42392—
    • H01L29/66469—
    • H01L29/66787—
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/026—Manufacture or treatment of FETs having insulated gates [IGFET] having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/402—Single electron transistors; Coulomb blockade transistors
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Definitions

  • Embodiments of the present invention relate to the field of semiconductor technologies, and in particular, to a field-effect transistor and a fabrication method of a field-effect transistor.
  • FIG. 1 when a field-effect transistor (FET) is fabricated, in an example of a MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor), as shown in FIG. 1 , generally, a first semiconductor material layer 11 and a second semiconductor material layer 12 are alternately stacked in a channel 100 , a dummy gate structure 13 is located on the second semiconductor material layer 12 , and a source 14 and a drain 15 are formed in a source drain area on two sides of the channel 100 by using a doping process. Then, the second semiconductor material layer 12 and the dummy gate structure 13 may be removed by using an etching process. Further, as shown in FIG.
  • FET field-effect transistor
  • MOSFET Metal-Oxide Semiconductor Field-Effect Transistor
  • locations of the first semiconductor material layer 11 and the dummy gate structure 13 are filled with a gate material by using an RMG (replacement metal gate) process, for example, a high dielectric constant (High-K) material, to form a real gate 21 .
  • RMG replacement metal gate
  • High-K high dielectric constant
  • the source 14 and the drain 15 are formed by using the doping process, as shown in FIG. 1 , the source 14 (or the drain 15 ) is in direct contact with the first semiconductor material layer 11 and the second semiconductor material layer 12 in the channel 100 . Consequently, some impurity atoms diffuse into the second semiconductor material layer 12 and the first semiconductor material layer 11 to form an extension area 22 . As a result, a parasitic parameter such as a parasitic capacitance of a subsequently formed MOSFET is increased, and a GIDL (gate-induced drain leakage) of the MOSFET is also increased, severely affecting performance and reliability of the MOSFET.
  • GIDL gate-induced drain leakage
  • Embodiments of the present invention provide a field-effect transistor and a fabrication method of a field-effect transistor, to reduce a parasitic parameter of a field-effect transistor, thereby improving performance and reliability of the field-effect transistor.
  • an embodiment of the present invention provides a fabrication method of a field-effect transistor, including: forming a fin support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction (the gate length direction is used to indicate a transport direction of a carrier in the field-effect transistor) is less than a length of the first semiconductor material layer in the gate length direction; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove, where the sacrificial layer is a projection area of the dummy gate structure in the first semiconductor material layer along a target direction (to be specific, a direction perpendicular to
  • a gate material (to be specific, a material with a relatively high dielectric constant) filled at a location of the sacrificial layer can also be isolated from the source and the drain through the insulation groove, to reduce a parasitic parameter such as a parasitic capacitance formed when the source and the drain are in direct contact with the gate material, thereby improving performance and reliability of the field-effect transistor.
  • the removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove includes: performing, along the gate length direction, a selective oxidation process on the first semiconductor material layer, so that the area other than the sacrificial layer in the first semiconductor material layer is oxidized to form the insulation groove, where the dielectric filled in the insulation groove is an oxide of the first semiconductor material layer, and the oxide usually has a relatively low dielectric constant.
  • the insulation groove can isolate the subsequently formed source (or drain) from a high-K (high dielectric constant) dielectric material filled in the sacrificial layer, to avoid a parasitic capacitance generated after the source (or the drain) is in direct contact with the high-K dielectric material.
  • the removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove includes: performing, along the gate length direction, a selective etching process on the first semiconductor material layer, so that the area other than the sacrificial layer in the first semiconductor material layer is removed to form the insulation groove.
  • the dielectric filled in the insulation groove is air with a relatively low dielectric constant. Therefore, the insulation groove can isolate the subsequently formed source (or drain) from the high-K dielectric material filled in the sacrificial layer, to avoid a parasitic capacitance generated after the source (or the drain) is in direct contact with the high-K dielectric material.
  • the method further includes: filling the insulation groove with a dielectric material whose dielectric constant is less than 3.9.
  • the insulation groove is filled with the dielectric material whose dielectric constant is less than 3.9, to be specific, filled with a low-K dielectric material. Therefore, the insulation groove can isolate the subsequently formed source (or drain) from the high-K dielectric material filled in the sacrificial layer, to avoid a parasitic capacitance generated after the source (or the drain) is in direct contact with the high-K dielectric material.
  • the method before the filling the insulation groove with a dielectric material whose dielectric constant is less than 3.9, the method further includes: forming, along the gate length direction, an etching stop layer on a surface of the insulation groove by using an atomic layer deposition (ALD) process.
  • ALD atomic layer deposition
  • the method further includes: removing the dummy gate structure and the sacrificial layer; and adjusting a thickness of the second semiconductor material layer along a gate structure cross-sectional direction, where the gate structure cross-sectional direction is perpendicular to the gate length direction. Because a channel effect of the field-effect transistor is related to the thickness of the second semiconductor material layer, the channel effect of the field-effect transistor can be alleviated by adjusting the thickness of the second semiconductor material layer, to flexibly adjust the channel effect.
  • the adjusting a thickness of the second semiconductor material layer includes: reducing the thickness of the second semiconductor material layer from 8 nm to 4 nm by using an etching process.
  • the method further includes: forming a gate at locations of the removed dummy gate structure and the removed sacrificial layer by using an RMG process.
  • the forming a support structure with a superlattice feature on a semiconductor substrate includes: growing a periodic superlattice structure including the first semiconductor material layer and the second semiconductor material layer that are alternately disposed on the semiconductor substrate, where a thickness of the first semiconductor material layer and the thickness of the second semiconductor material layer are both less than 50 nm; and etching the superlattice structure to form the fin support structure.
  • the forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure includes: forming an oxide layer on the exposed support structure; and forming, on the oxide layer, the dummy gate structure that covers the support structure.
  • a length of the dummy gate structure in the gate structure cross-sectional direction is less than a length of the isolation layer; and after the dummy gate structure that covers the support structure is formed on the isolation layer, the method further includes: depositing an insulation layer on a periphery of the dummy gate structure, where a side wall of the insulation layer is flush with a side wall of the isolation layer.
  • an embodiment of the present invention provides a field-effect transistor, including a source and a drain.
  • a gate is disposed in a channel between the source and the drain, the gate is isolated from the source and the drain through an insulation groove, a dielectric constant of a dielectric filled in the insulation groove is less than a dielectric constant of a first semiconductor material layer, and the first semiconductor material layer is a superlattice material film formed when the field-effect transistor is fabricated.
  • FIG. 1 is a schematic diagram 1 of a fabrication principle of a field-effect transistor in the prior art
  • FIG. 2 is a schematic diagram 2 of a fabrication principle of a field-effect transistor in the prior art
  • FIG. 3 is a schematic structural diagram of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic flowchart of a fabrication method of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram 1 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram 2 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram 3 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram 4 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram 5 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram 6 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram 7 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram 8 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram 9 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram 10 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 15 is a schematic diagram 11 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 16 is a schematic diagram 12 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • FIG. 17 is a schematic diagram 13 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
  • the embodiments of the present invention provide a field-effect transistor.
  • the field-effect transistor may be a MOSFET such as a stacked gate-all-around nanowire transistor or a fin field-effect transistor (FinFET), or may be a tunneling field-effect transistor (TFET) or the like. This is not limited in the embodiments of the present invention.
  • FIG. 3 is a schematic structural diagram of a field-effect transistor according to an embodiment of the present invention.
  • a gate 32 is disposed on a semiconductor substrate 31
  • a source drain area is located on two sides of the gate 32
  • a fin source 33 and a fin drain 34 are respectively disposed on the two sides of the gate 32 .
  • an XX′ direction is used to indicate a gate length direction of the field-effect transistor, to be specific, a transport direction of a carrier in the field-effect transistor;
  • a YY′ direction is used to indicate a gate structure cross-sectional direction of the field-effect transistor, where the gate length direction and the gate structure cross-sectional direction are perpendicular to each other.
  • FIG. 3 shows merely a structure including a group of the gate 32 , the source 33 , and the drain 34 in the field-effect transistor. It can be understood that the field-effect transistor may further include a plurality of groups of gates, sources, and drains that have similar structures as the foregoing gate, source, and drain. This is not limited in this embodiment of the present invention.
  • an embodiment of the present invention provides a fabrication method of a field-effect transistor. As shown in FIG. 4 , the method includes the following steps.
  • Block 401 Form a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure.
  • the semiconductor substrate may be an SOI (silicon-on-insulator) substrate, a bulk silicon substrate, an ETSOI (extremely thin SOI) substrate, an SGOI (SiGe-on-insulator) substrate, an III-V-OI (III-V-on-insulator) substrate, or the like. This is not limited in this embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view along a gate length direction
  • FIG. 5 ( b ) is a schematic cross-sectional view along a gate structure cross-sectional direction
  • a periodic superlattice (superlattice) structure including a first semiconductor material layer 52 and a second semiconductor material layer 53 that are alternately disposed may be first grown on a semiconductor substrate 51 .
  • the superlattice structure is a strictly periodic multi-layer film that includes two different types of elements that are alternately stacked in forms of thin layers whose thicknesses range from several nanometers to tens of nanometers.
  • a thickness of the first semiconductor material layer 52 and a thickness of the second semiconductor material layer 53 may be both less than 50 nm.
  • the first semiconductor material layer 52 is made of a silicon material
  • the second semiconductor material layer 53 may be made of a silicon germanium material.
  • the superlattice structure including the first semiconductor material layer 52 and the second semiconductor material layer 53 may be etched to form a support structure 61 shown in FIG. 6 .
  • the support structure 61 may be disposed on the semiconductor substrate 51 in a fin form.
  • FIG. 6 ( a ) is a schematic cross-sectional view along a gate length direction
  • FIG. 6 ( b ) is a schematic cross-sectional view along a gate structure cross-sectional direction.
  • an isolation layer 71 may be further formed on the two sides of the support structure 61 by using a CMP (chemical-mechanical polishing) process and a recess process.
  • CMP chemical-mechanical polishing
  • a thickness of the isolation layer 71 is the same as a thickness of the etched semiconductor substrate 51 .
  • the isolation layer 71 may be specifically made of an oxide such as silicon oxide. This is not limited in this embodiment of the present invention.
  • Block 402 Form, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than a length of the first semiconductor material layer in the gate length direction.
  • a dummy gate structure 81 that covers the support structure 61 may be further formed on the isolation layer 71 .
  • the support structure 61 is embedded in a gap formed between the isolation layer 71 and the dummy gate structure 81 .
  • FIG. 9 ( a ) a length of the dummy gate structure 81 in the gate length direction is less than a length of the first semiconductor material layer 52 in the gate length direction.
  • FIG. 9 ( a ) is a schematic cross-sectional view along a gate length direction
  • FIG. 9 ( b ) is a schematic cross-sectional view along a gate structure cross-sectional direction.
  • the dummy gate structure 81 may be specifically made of a polycrystalline silicon material or an amorphous silicon material. This is not limited in this embodiment of the present invention.
  • an oxide layer may be first formed on the exposed support structure 61 , and then the dummy gate structure 81 that covers the support structure 61 may be formed on the oxide layer.
  • an insulation layer 91 may be further deposited on a periphery of the dummy gate structure 81 , so that a side wall of the insulation layer 91 is flush with a side wall of the isolation layer 71 in the gate structure cross-sectional direction.
  • FIG. 10 ( a ) is a schematic cross-sectional view along a gate length direction
  • FIG. 10 ( b ) is a schematic cross-sectional view along a gate structure cross-sectional direction.
  • the dummy gate structure 81 when the dummy gate structure 81 is formed, etching anisotropy is ensured as much as possible, and an etching selection ratio of polycrystalline silicon and silicon oxide is adjusted to be as high as possible, to form the dummy gate structure 81 in a relatively steep shape.
  • the dummy gate structure 81 in the relatively steep shape facilitates subsequent forming of the insulation layer 91 . Therefore, the dummy gate structure 81 can well fit with the insulation layer 91 , thereby ensuring that the dummy gate structure 81 is effectively isolated.
  • Block 403 Remove, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove.
  • the foregoing sacrificial layer is a projection area of the dummy gate structure 81 in the first semiconductor material layer 52 along a target direction (the target direction is a direction perpendicular to a bottom of the semiconductor substrate 51 , to be specific, an orthographic projection direction of the dummy gate structure 81 in the first semiconductor material layer 52 ).
  • a dielectric constant of a dielectric filled in the insulation groove is less than a dielectric constant of the first semiconductor material layer.
  • the first semiconductor material layer 52 and the second semiconductor material layer 53 may be first etched along the side wall of the insulation layer 91 in the gate length direction, so that side walls of the first semiconductor material layer 52 and the second semiconductor material layer 53 are flush with the side wall of the insulation layer 91 (as shown in FIG. 11 ( a ) ).
  • FIG. 11 ( a ) is a schematic cross-sectional view along a gate length direction
  • FIG. 11 ( b ) is a schematic cross-sectional view along a gate structure cross-sectional direction.
  • a selective oxidation (selective oxidation) process is performed on the first semiconductor material layer 52 shown in FIG. 11 ( a ) . Therefore, in the first semiconductor material layer 52 , the area other than the projection area of the dummy gate structure 81 in the first semiconductor material layer 52 is oxidized, and an oxidized part forms an insulation groove 101 shown in FIG. 12 ( a ) ; the projection area of the dummy gate structure 81 in the first semiconductor material layer 52 is not oxidized to form a sacrificial layer 102 shown in FIG. 12 ( a ) .
  • the insulation groove 101 is filled with an oxide (for example, silicon oxide) of the first semiconductor material layer 52 , and the oxide of the first semiconductor material layer 52 usually has a relatively low dielectric constant. Therefore, the insulation groove 101 can isolate the subsequently formed source (or drain) from a gate material filled in the sacrificial layer 102 , for example, a high-K (high dielectric constant) dielectric material, to avoid a parasitic capacitance generated after the subsequently formed source (or drain) is in direct contact with the gate formed by the gate material.
  • FIG. 12 ( a ) is a schematic cross-sectional view along a gate length direction
  • FIG. 12 ( b ) is a schematic cross-sectional view along a gate structure cross-sectional direction.
  • the first semiconductor material layer 52 is made of silicon
  • silicon oxide is formed in the insulation groove 101 .
  • a dielectric constant of the silicon oxide is approximately 3.9
  • a dielectric constant of silicon is approximately 11.5, which is far greater than the dielectric constant of the silicon oxide.
  • a selective etching process may be performed on the first semiconductor material layer 52 shown in FIG. 11 ( a ) along the gate length direction. Therefore, in the first semiconductor material layer 52 , the area other than the projection area of the dummy gate structure 81 in the first semiconductor material layer 52 is removed to form the insulation groove 101 shown in FIG. 13 ( a ) ; the projection area of the dummy gate structure 81 in the first semiconductor material layer 52 is retained to form the sacrificial layer 102 shown in FIG. 13 ( a ) .
  • the insulation groove 101 is filled with air.
  • the air is a dielectric with a relatively low dielectric constant (a dielectric constant of the air is approximately 1).
  • FIG. 13 ( a ) is a schematic cross-sectional view along a gate length direction
  • FIG. 13 ( b ) is a schematic cross-sectional view along a gate structure cross-sectional direction.
  • an etching stop layer 111 may be formed on a surface of the insulation groove 101 by using an ALD (atomic layer deposition) process. In this way, when the sacrificial layer 102 is subsequently removed, the etching stop layer 111 can prevent an etching solution from etching an area other than the sacrificial layer 102 .
  • ALD atomic layer deposition
  • the insulation groove 101 may be filled with a dielectric material whose dielectric constant is less than 3.9, for example, a low-K (low dielectric constant) dielectric material 121 , so that the insulation groove 101 has a lower K (dielectric constant) value, to avoid a parasitic capacitance generated after the subsequently formed source (or drain) is in direct contact with the gate formed by the gate material filled in the sacrificial layer 102 .
  • a dielectric material whose dielectric constant is less than 3.9 for example, a low-K (low dielectric constant) dielectric material 121 , so that the insulation groove 101 has a lower K (dielectric constant) value, to avoid a parasitic capacitance generated after the subsequently formed source (or drain) is in direct contact with the gate formed by the gate material filled in the sacrificial layer 102 .
  • a dielectric material whose dielectric constant is less than 2.5 may be used as a low-K dielectric material, for example, SiCOH (a hydrogenated silicon carbon oxide).
  • a dielectric material whose dielectric constant is greater than 4 may be used as a high-K dielectric material, for example, HfO 2 (hafnium dioxide).
  • the dielectric constant of the first semiconductor material layer 52 or the second semiconductor material layer 53 is approximately 10 to 12.
  • Block 404 Form a source and a drain in a preset source drain area along the gate length direction, where the source and the drain are isolated from the sacrificial layer through the insulation groove.
  • a material such as silicon or silicon germanium may epitaxially grow in a preset source drain area by using a selective epitaxy technology. Further, a doping process is used, so that the source drain area has a specified doping density, to form a source 131 and a drain 132 shown in FIG. 15 ( FIG. 15 ( a ) is a schematic cross-sectional view along a gate length direction, and FIG. 15 ( b ) is a schematic cross-sectional view along a gate structure cross-sectional direction).
  • the source 131 and the drain 132 are isolated from the sacrificial layer 102 through the insulation groove 101 . Subsequently, after the sacrificial layer 102 is removed, a high-K dielectric material may be filled at a location of the sacrificial layer 102 to form a gate. In this way, the source 131 and the drain 132 can still be isolated from the gate through the insulation groove 101 , to reduce a parasitic capacitance generated when the source 131 and the drain 132 are in direct contact with the gate.
  • an impurity atom diffuses into the second semiconductor material layer 53 to form an extension area 133 .
  • a size of the extension area is related to a parasitic resistance of a field-effect transistor. A larger extension area indicates a smaller value of the parasitic resistance, and a smaller extension area indicates a larger value of the parasitic resistance.
  • the thickness of the second semiconductor material layer 53 may be set as large as possible, to form a relatively large extension area.
  • the larger thickness of the second semiconductor material layer 53 reduces a capability of the field-effect transistor to suppress a short-channel effect. For example, a leakage current of the field-effect transistor is increased.
  • the foregoing problem may be resolved by using the following block 406 .
  • Block 405 Remove the dummy gate structure and the sacrificial layer.
  • FIG. 16 As shown in FIG. 16 ( FIG. 16 ( a ) is a schematic cross-sectional view along a gate length direction, and FIG. 16 ( b ) is a schematic cross-sectional view along a gate structure cross-sectional direction), the foregoing dummy gate structure 81 and the sacrificial layer 102 may be removed by using an etching process.
  • Block 406 Adjust a thickness of the second semiconductor material layer along a gate structure cross-sectional direction.
  • the thickness of the second semiconductor material layer 53 in a channel area may be adjusted.
  • the thickness of the second semiconductor material layer 53 may be reduced from T 1 of 8 nm to T 2 of 4 nm through adjustment by using an etching process or the like.
  • the channel effect of the field-effect transistor is related to the thickness of the second semiconductor material layer 53 , the short-channel effect of the field-effect transistor can be alleviated by adjusting the thickness of the second semiconductor material layer 53 , so that the short-channel effect is flexibly adjusted without increasing a parasitic resistance.
  • Block 407 Form a gate at locations of the removed dummy gate structure and the removed sacrificial layer by using an RMG process.
  • a gate 151 shown in FIG. 17 may be formed at locations of the removed dummy gate structure 81 and the removed sacrificial layer 102 by using an RMG (replacement metal gate) process, to finally form a field-effect transistor.
  • FIG. 17 ( a ) is a schematic cross-sectional view along a gate length direction
  • FIG. 17 ( b ) is a schematic cross-sectional view along a gate structure cross-sectional direction.
  • the location at which the first semiconductor material layer 51 is originally disposed in the gate 151 may be isolated from the source 131 (or the drain 132 ) by using a material with a relatively low dielectric constant in the insulation groove 101 ; the location at which the dummy gate structure 81 is originally disposed in the gate 151 may be isolated from the source 131 (or the drain 132 ) by using the insulation layer 91 .
  • the gate 151 is almost completely isolated from the source 131 (or the drain 132 ) through the insulation groove 101 and the insulation layer 91 , to reduce a parasitic capacitance of the entire field-effect transistor, thereby improving performance and reliability of the field-effect transistor.
  • an embodiment of the present invention further provides a field-effect transistor.
  • the field-effect transistor may be a MOSFET, a tunneling field-effect transistor, or the like. This is not limited in this embodiment of the present invention.
  • the gate 151 is disposed in a channel formed between the source 131 and the drain 132 , and the gate 151 is not in direct contact with the source 131 (or the drain 132 ) but is isolated from the source 131 (or the drain 132 ) through the insulation groove 101 .
  • the insulation groove 101 is filled with a material with a relatively low dielectric constant. Therefore, a parasitic capacitance generated when the gate 151 is in direct contact with the source 131 (or the drain 132 ) can be avoided, and performance and reliability of the field-effect transistor can be improved.
  • the embodiments of the present invention provide the field-effect transistor and the fabrication method of the field-effect transistor.
  • the fabrication method includes: first forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; further forming, on the isolation layer, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than a length of the first semiconductor material layer in the gate length direction; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove, where the insulation groove is formed in the area other than the sacrificial layer in the first semiconductor material layer, and the sacrificial layer is a projection area of the dummy gate structure in the first semiconductor material layer along a target direction (to be specific, a direction perpendicular to a surface
  • the functions described in the present invention may be implemented by using hardware, software, firmware, or any combination thereof.
  • these functions may be stored in a computer readable medium or transmitted as one or more instructions or code in the computer readable medium.
  • the computer readable medium includes a computer storage medium and a communications medium, where the communications medium includes any medium that enables a computer program to be transmitted from one place to another.
  • the storage medium may be any available medium accessible to a general-purpose or dedicated computer.

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Abstract

The invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove,; and forming a source and a drain in a preset source drain area along the gate length direction.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of International Application No. PCT/CN2017/088086, filed on Jun. 13, 2017, which claims priority to Chinese Patent Application No. 201611022835.2, filed on Nov. 21, 2016. The disclosures of the aforementioned applications are hereby incorporated by reference in their entireties.
TECHNICAL FIELD
Embodiments of the present invention relate to the field of semiconductor technologies, and in particular, to a field-effect transistor and a fabrication method of a field-effect transistor.
BACKGROUND
Currently, when a field-effect transistor (FET) is fabricated, in an example of a MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor), as shown in FIG. 1, generally, a first semiconductor material layer 11 and a second semiconductor material layer 12 are alternately stacked in a channel 100, a dummy gate structure 13 is located on the second semiconductor material layer 12, and a source 14 and a drain 15 are formed in a source drain area on two sides of the channel 100 by using a doping process. Then, the second semiconductor material layer 12 and the dummy gate structure 13 may be removed by using an etching process. Further, as shown in FIG. 2, locations of the first semiconductor material layer 11 and the dummy gate structure 13 are filled with a gate material by using an RMG (replacement metal gate) process, for example, a high dielectric constant (High-K) material, to form a real gate 21.
In the foregoing fabrication method, when the source 14 and the drain 15 are formed by using the doping process, as shown in FIG. 1, the source 14 (or the drain 15) is in direct contact with the first semiconductor material layer 11 and the second semiconductor material layer 12 in the channel 100. Consequently, some impurity atoms diffuse into the second semiconductor material layer 12 and the first semiconductor material layer 11 to form an extension area 22. As a result, a parasitic parameter such as a parasitic capacitance of a subsequently formed MOSFET is increased, and a GIDL (gate-induced drain leakage) of the MOSFET is also increased, severely affecting performance and reliability of the MOSFET.
SUMMARY
Embodiments of the present invention provide a field-effect transistor and a fabrication method of a field-effect transistor, to reduce a parasitic parameter of a field-effect transistor, thereby improving performance and reliability of the field-effect transistor.
The following technical solutions are used in the embodiments of the present invention to achieve the foregoing objective.
According to a first aspect, an embodiment of the present invention provides a fabrication method of a field-effect transistor, including: forming a fin support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction (the gate length direction is used to indicate a transport direction of a carrier in the field-effect transistor) is less than a length of the first semiconductor material layer in the gate length direction; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove, where the sacrificial layer is a projection area of the dummy gate structure in the first semiconductor material layer along a target direction (to be specific, a direction perpendicular to a bottom of the semiconductor substrate), and a dielectric constant of a dielectric filled in the insulation groove is less than a dielectric constant of the first semiconductor material layer; and forming a source and a drain in a preset source drain area along the gate length direction, where the source and the drain are isolated from the sacrificial layer through the insulation groove. In this way, after the sacrificial layer is subsequently removed, a gate material (to be specific, a material with a relatively high dielectric constant) filled at a location of the sacrificial layer can also be isolated from the source and the drain through the insulation groove, to reduce a parasitic parameter such as a parasitic capacitance formed when the source and the drain are in direct contact with the gate material, thereby improving performance and reliability of the field-effect transistor.
In one embodiment, the removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove includes: performing, along the gate length direction, a selective oxidation process on the first semiconductor material layer, so that the area other than the sacrificial layer in the first semiconductor material layer is oxidized to form the insulation groove, where the dielectric filled in the insulation groove is an oxide of the first semiconductor material layer, and the oxide usually has a relatively low dielectric constant. Therefore, the insulation groove can isolate the subsequently formed source (or drain) from a high-K (high dielectric constant) dielectric material filled in the sacrificial layer, to avoid a parasitic capacitance generated after the source (or the drain) is in direct contact with the high-K dielectric material.
In one embodiment, the removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove includes: performing, along the gate length direction, a selective etching process on the first semiconductor material layer, so that the area other than the sacrificial layer in the first semiconductor material layer is removed to form the insulation groove. In this case, the dielectric filled in the insulation groove is air with a relatively low dielectric constant. Therefore, the insulation groove can isolate the subsequently formed source (or drain) from the high-K dielectric material filled in the sacrificial layer, to avoid a parasitic capacitance generated after the source (or the drain) is in direct contact with the high-K dielectric material.
In one embodiment, after the insulation groove is formed, the method further includes: filling the insulation groove with a dielectric material whose dielectric constant is less than 3.9. In this case, the insulation groove is filled with the dielectric material whose dielectric constant is less than 3.9, to be specific, filled with a low-K dielectric material. Therefore, the insulation groove can isolate the subsequently formed source (or drain) from the high-K dielectric material filled in the sacrificial layer, to avoid a parasitic capacitance generated after the source (or the drain) is in direct contact with the high-K dielectric material.
In one embodiment, before the filling the insulation groove with a dielectric material whose dielectric constant is less than 3.9, the method further includes: forming, along the gate length direction, an etching stop layer on a surface of the insulation groove by using an atomic layer deposition (ALD) process. In this way, when the sacrificial layer is subsequently removed, the etching stop layer can prevent an etching solution from etching an area other than the sacrificial layer.
In one embodiment, after the forming a source and a drain in a preset source drain area along the gate length direction, the method further includes: removing the dummy gate structure and the sacrificial layer; and adjusting a thickness of the second semiconductor material layer along a gate structure cross-sectional direction, where the gate structure cross-sectional direction is perpendicular to the gate length direction. Because a channel effect of the field-effect transistor is related to the thickness of the second semiconductor material layer, the channel effect of the field-effect transistor can be alleviated by adjusting the thickness of the second semiconductor material layer, to flexibly adjust the channel effect.
In one embodiment, the adjusting a thickness of the second semiconductor material layer includes: reducing the thickness of the second semiconductor material layer from 8 nm to 4 nm by using an etching process.
In one embodiment, after the adjusting a thickness of the second semiconductor material layer along a gate structure cross-sectional direction, the method further includes: forming a gate at locations of the removed dummy gate structure and the removed sacrificial layer by using an RMG process.
In one embodiment, the forming a support structure with a superlattice feature on a semiconductor substrate includes: growing a periodic superlattice structure including the first semiconductor material layer and the second semiconductor material layer that are alternately disposed on the semiconductor substrate, where a thickness of the first semiconductor material layer and the thickness of the second semiconductor material layer are both less than 50 nm; and etching the superlattice structure to form the fin support structure.
In one embodiment, the forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure includes: forming an oxide layer on the exposed support structure; and forming, on the oxide layer, the dummy gate structure that covers the support structure.
In one embodiment, a length of the dummy gate structure in the gate structure cross-sectional direction is less than a length of the isolation layer; and after the dummy gate structure that covers the support structure is formed on the isolation layer, the method further includes: depositing an insulation layer on a periphery of the dummy gate structure, where a side wall of the insulation layer is flush with a side wall of the isolation layer.
According to a second aspect, an embodiment of the present invention provides a field-effect transistor, including a source and a drain. A gate is disposed in a channel between the source and the drain, the gate is isolated from the source and the drain through an insulation groove, a dielectric constant of a dielectric filled in the insulation groove is less than a dielectric constant of a first semiconductor material layer, and the first semiconductor material layer is a superlattice material film formed when the field-effect transistor is fabricated.
These aspects or other aspects of the present invention are more concise and understandable in the description of the following embodiments.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a schematic diagram 1 of a fabrication principle of a field-effect transistor in the prior art;
FIG. 2 is a schematic diagram 2 of a fabrication principle of a field-effect transistor in the prior art;
FIG. 3 is a schematic structural diagram of a field-effect transistor according to an embodiment of the present invention;
FIG. 4 is a schematic flowchart of a fabrication method of a field-effect transistor according to an embodiment of the present invention;
FIG. 5 is a schematic diagram 1 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention;
FIG. 6 is a schematic diagram 2 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention;
FIG. 7 is a schematic diagram 3 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention;
FIG. 8 is a schematic diagram 4 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention;
FIG. 9 is a schematic diagram 5 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention;
FIG. 10 is a schematic diagram 6 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention;
FIG. 11 is a schematic diagram 7 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention;
FIG. 12 is a schematic diagram 8 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention;
FIG. 13 is a schematic diagram 9 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention;
FIG. 14 is a schematic diagram 10 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention;
FIG. 15 is a schematic diagram 11 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention;
FIG. 16 is a schematic diagram 12 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention; and
FIG. 17 is a schematic diagram 13 of a fabrication principle of a field-effect transistor according to an embodiment of the present invention.
 DESCRIPTION OF EMBODIMENTS
The following describes in detail the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are merely some but not all of the embodiments of the present invention.
The embodiments of the present invention provide a field-effect transistor. The field-effect transistor may be a MOSFET such as a stacked gate-all-around nanowire transistor or a fin field-effect transistor (FinFET), or may be a tunneling field-effect transistor (TFET) or the like. This is not limited in the embodiments of the present invention.
In addition, the embodiments of the present invention provide a field-effect transistor and a fabrication method of a field-effect transistor. For ease of description, cross-sectional directions of the field-effect transistor are first explained. FIG. 3 is a schematic structural diagram of a field-effect transistor according to an embodiment of the present invention. A gate 32 is disposed on a semiconductor substrate 31, a source drain area is located on two sides of the gate 32, and a fin source 33 and a fin drain 34 are respectively disposed on the two sides of the gate 32. In this case, an XX′ direction is used to indicate a gate length direction of the field-effect transistor, to be specific, a transport direction of a carrier in the field-effect transistor; a YY′ direction is used to indicate a gate structure cross-sectional direction of the field-effect transistor, where the gate length direction and the gate structure cross-sectional direction are perpendicular to each other.
It should be noted that FIG. 3 shows merely a structure including a group of the gate 32, the source 33, and the drain 34 in the field-effect transistor. It can be understood that the field-effect transistor may further include a plurality of groups of gates, sources, and drains that have similar structures as the foregoing gate, source, and drain. This is not limited in this embodiment of the present invention.
Based on the gate length direction and the gate structure cross-sectional direction shown in FIG. 3, an embodiment of the present invention provides a fabrication method of a field-effect transistor. As shown in FIG. 4, the method includes the following steps.
Block 401. Form a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure.
The semiconductor substrate may be an SOI (silicon-on-insulator) substrate, a bulk silicon substrate, an ETSOI (extremely thin SOI) substrate, an SGOI (SiGe-on-insulator) substrate, an III-V-OI (III-V-on-insulator) substrate, or the like. This is not limited in this embodiment of the present invention.
Specifically, as shown in FIG. 5 (FIG. 5 (a) is a schematic cross-sectional view along a gate length direction, and FIG. 5 (b) is a schematic cross-sectional view along a gate structure cross-sectional direction), a periodic superlattice (superlattice) structure including a first semiconductor material layer 52 and a second semiconductor material layer 53 that are alternately disposed may be first grown on a semiconductor substrate 51. The superlattice structure is a strictly periodic multi-layer film that includes two different types of elements that are alternately stacked in forms of thin layers whose thicknesses range from several nanometers to tens of nanometers.
For example, a thickness of the first semiconductor material layer 52 and a thickness of the second semiconductor material layer 53 may be both less than 50 nm. When the first semiconductor material layer 52 is made of a silicon material, the second semiconductor material layer 53 may be made of a silicon germanium material.
Further, the superlattice structure including the first semiconductor material layer 52 and the second semiconductor material layer 53 may be etched to form a support structure 61 shown in FIG. 6. For example, the support structure 61 may be disposed on the semiconductor substrate 51 in a fin form. Herein, FIG. 6 (a) is a schematic cross-sectional view along a gate length direction, and FIG. 6 (b) is a schematic cross-sectional view along a gate structure cross-sectional direction.
Further, as shown in FIG. 7, an isolation layer 71 may be further formed on the two sides of the support structure 61 by using a CMP (chemical-mechanical polishing) process and a recess process.
Optionally, a thickness of the isolation layer 71 is the same as a thickness of the etched semiconductor substrate 51.
For example, the isolation layer 71 may be specifically made of an oxide such as silicon oxide. This is not limited in this embodiment of the present invention.
Block 402. Form, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than a length of the first semiconductor material layer in the gate length direction.
As shown in FIG. 8, after the isolation layer 71 is formed, a dummy gate structure 81 that covers the support structure 61 may be further formed on the isolation layer 71. In this case, the support structure 61 is embedded in a gap formed between the isolation layer 71 and the dummy gate structure 81.
As shown in FIG. 9 (a), a length of the dummy gate structure 81 in the gate length direction is less than a length of the first semiconductor material layer 52 in the gate length direction. Herein, FIG. 9 (a) is a schematic cross-sectional view along a gate length direction, and FIG. 9 (b) is a schematic cross-sectional view along a gate structure cross-sectional direction.
For example, the dummy gate structure 81 may be specifically made of a polycrystalline silicon material or an amorphous silicon material. This is not limited in this embodiment of the present invention.
Specifically, an oxide layer may be first formed on the exposed support structure 61, and then the dummy gate structure 81 that covers the support structure 61 may be formed on the oxide layer.
Further, as shown in FIG. 10, an insulation layer 91 may be further deposited on a periphery of the dummy gate structure 81, so that a side wall of the insulation layer 91 is flush with a side wall of the isolation layer 71 in the gate structure cross-sectional direction. Herein, FIG. 10 (a) is a schematic cross-sectional view along a gate length direction, and FIG. 10 (b) is a schematic cross-sectional view along a gate structure cross-sectional direction.
In addition, when the dummy gate structure 81 is formed, etching anisotropy is ensured as much as possible, and an etching selection ratio of polycrystalline silicon and silicon oxide is adjusted to be as high as possible, to form the dummy gate structure 81 in a relatively steep shape. The dummy gate structure 81 in the relatively steep shape facilitates subsequent forming of the insulation layer 91. Therefore, the dummy gate structure 81 can well fit with the insulation layer 91, thereby ensuring that the dummy gate structure 81 is effectively isolated.
Block 403. Remove, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove.
The foregoing sacrificial layer is a projection area of the dummy gate structure 81 in the first semiconductor material layer 52 along a target direction (the target direction is a direction perpendicular to a bottom of the semiconductor substrate 51, to be specific, an orthographic projection direction of the dummy gate structure 81 in the first semiconductor material layer 52).
A dielectric constant of a dielectric filled in the insulation groove is less than a dielectric constant of the first semiconductor material layer.
In a possible design manner, the first semiconductor material layer 52 and the second semiconductor material layer 53 may be first etched along the side wall of the insulation layer 91 in the gate length direction, so that side walls of the first semiconductor material layer 52 and the second semiconductor material layer 53 are flush with the side wall of the insulation layer 91 (as shown in FIG. 11 (a)). Herein, FIG. 11 (a) is a schematic cross-sectional view along a gate length direction, and FIG. 11 (b) is a schematic cross-sectional view along a gate structure cross-sectional direction.
Further, a selective oxidation (selective oxidation) process is performed on the first semiconductor material layer 52 shown in FIG. 11 (a). Therefore, in the first semiconductor material layer 52, the area other than the projection area of the dummy gate structure 81 in the first semiconductor material layer 52 is oxidized, and an oxidized part forms an insulation groove 101 shown in FIG. 12 (a); the projection area of the dummy gate structure 81 in the first semiconductor material layer 52 is not oxidized to form a sacrificial layer 102 shown in FIG. 12 (a). In this case, the insulation groove 101 is filled with an oxide (for example, silicon oxide) of the first semiconductor material layer 52, and the oxide of the first semiconductor material layer 52 usually has a relatively low dielectric constant. Therefore, the insulation groove 101 can isolate the subsequently formed source (or drain) from a gate material filled in the sacrificial layer 102, for example, a high-K (high dielectric constant) dielectric material, to avoid a parasitic capacitance generated after the subsequently formed source (or drain) is in direct contact with the gate formed by the gate material. Herein, FIG. 12 (a) is a schematic cross-sectional view along a gate length direction, and FIG. 12 (b) is a schematic cross-sectional view along a gate structure cross-sectional direction.
For example, when the first semiconductor material layer 52 is made of silicon, after the foregoing selective oxidation process is performed, silicon oxide is formed in the insulation groove 101. A dielectric constant of the silicon oxide is approximately 3.9, and a dielectric constant of silicon is approximately 11.5, which is far greater than the dielectric constant of the silicon oxide.
In another embodiment, a selective etching process may be performed on the first semiconductor material layer 52 shown in FIG. 11 (a) along the gate length direction. Therefore, in the first semiconductor material layer 52, the area other than the projection area of the dummy gate structure 81 in the first semiconductor material layer 52 is removed to form the insulation groove 101 shown in FIG. 13 (a); the projection area of the dummy gate structure 81 in the first semiconductor material layer 52 is retained to form the sacrificial layer 102 shown in FIG. 13 (a). In this case, the insulation groove 101 is filled with air. The air is a dielectric with a relatively low dielectric constant (a dielectric constant of the air is approximately 1). Therefore, the air can isolate the subsequently formed source (or drain) from the gate material filled in the sacrificial layer 102, to avoid a parasitic capacitance generated after the subsequently formed source (or drain) is in direct contact with the gate formed by the gate material. Herein, FIG. 13 (a) is a schematic cross-sectional view along a gate length direction, and FIG. 13 (b) is a schematic cross-sectional view along a gate structure cross-sectional direction.
In addition, after the insulation groove 101 shown in FIG. 13 (a) is formed, as shown in FIG. 14 (FIG. 14 (a) is a schematic cross-sectional view along a gate length direction, and FIG. 14 (b) is a schematic cross-sectional view along a gate structure cross-sectional direction), an etching stop layer 111 may be formed on a surface of the insulation groove 101 by using an ALD (atomic layer deposition) process. In this way, when the sacrificial layer 102 is subsequently removed, the etching stop layer 111 can prevent an etching solution from etching an area other than the sacrificial layer 102.
Further, still as shown in FIG. 14 (a), the insulation groove 101 may be filled with a dielectric material whose dielectric constant is less than 3.9, for example, a low-K (low dielectric constant) dielectric material 121, so that the insulation groove 101 has a lower K (dielectric constant) value, to avoid a parasitic capacitance generated after the subsequently formed source (or drain) is in direct contact with the gate formed by the gate material filled in the sacrificial layer 102.
Generally, a dielectric material whose dielectric constant is less than 2.5 may be used as a low-K dielectric material, for example, SiCOH (a hydrogenated silicon carbon oxide).
Similarly, a dielectric material whose dielectric constant is greater than 4 may be used as a high-K dielectric material, for example, HfO2 (hafnium dioxide).
The dielectric constant (ε) described in this embodiment of the present invention is a product of a relative permittivity (εr) and an absolute vacuum permittivity (ε0), to be specific, ε=εr*ε0, where ε0=8.85*10−12 F/m.
For example, the dielectric constant of the first semiconductor material layer 52 or the second semiconductor material layer 53 is approximately 10 to 12.
Block 404. Form a source and a drain in a preset source drain area along the gate length direction, where the source and the drain are isolated from the sacrificial layer through the insulation groove.
In an example in which a low-K dielectric material 121 is filled in the insulation groove 101 shown in FIG. 14, in block 404, a material such as silicon or silicon germanium may epitaxially grow in a preset source drain area by using a selective epitaxy technology. Further, a doping process is used, so that the source drain area has a specified doping density, to form a source 131 and a drain 132 shown in FIG. 15 (FIG. 15 (a) is a schematic cross-sectional view along a gate length direction, and FIG. 15 (b) is a schematic cross-sectional view along a gate structure cross-sectional direction).
In this case, the source 131 and the drain 132 are isolated from the sacrificial layer 102 through the insulation groove 101. Subsequently, after the sacrificial layer 102 is removed, a high-K dielectric material may be filled at a location of the sacrificial layer 102 to form a gate. In this way, the source 131 and the drain 132 can still be isolated from the gate through the insulation groove 101, to reduce a parasitic capacitance generated when the source 131 and the drain 132 are in direct contact with the gate.
In addition, still as shown in FIG. 15 (a), when the source 131 and the drain 132 are formed, an impurity atom diffuses into the second semiconductor material layer 53 to form an extension area 133. A size of the extension area is related to a parasitic resistance of a field-effect transistor. A larger extension area indicates a smaller value of the parasitic resistance, and a smaller extension area indicates a larger value of the parasitic resistance.
Therefore, to reduce the parasitic resistance, the thickness of the second semiconductor material layer 53 may be set as large as possible, to form a relatively large extension area. However, the larger thickness of the second semiconductor material layer 53 reduces a capability of the field-effect transistor to suppress a short-channel effect. For example, a leakage current of the field-effect transistor is increased. In this case, the foregoing problem may be resolved by using the following block 406.
Block 405. Remove the dummy gate structure and the sacrificial layer.
As shown in FIG. 16 (FIG. 16 (a) is a schematic cross-sectional view along a gate length direction, and FIG. 16 (b) is a schematic cross-sectional view along a gate structure cross-sectional direction), the foregoing dummy gate structure 81 and the sacrificial layer 102 may be removed by using an etching process.
Block 406. Adjust a thickness of the second semiconductor material layer along a gate structure cross-sectional direction.
In step 406, as shown in FIG. 16 (b), the thickness of the second semiconductor material layer 53 in a channel area may be adjusted. For example, the thickness of the second semiconductor material layer 53 may be reduced from T1 of 8 nm to T2 of 4 nm through adjustment by using an etching process or the like. In this way, because the channel effect of the field-effect transistor is related to the thickness of the second semiconductor material layer 53, the short-channel effect of the field-effect transistor can be alleviated by adjusting the thickness of the second semiconductor material layer 53, so that the short-channel effect is flexibly adjusted without increasing a parasitic resistance.
Block 407. Form a gate at locations of the removed dummy gate structure and the removed sacrificial layer by using an RMG process.
Subsequently, based on the prior art, a gate 151 shown in FIG. 17 (the gate 151 includes a structure of at least two layers, where one layer is made of a high-K dielectric material, and the other layer is made of a metal material with a specific work function) may be formed at locations of the removed dummy gate structure 81 and the removed sacrificial layer 102 by using an RMG (replacement metal gate) process, to finally form a field-effect transistor. FIG. 17 (a) is a schematic cross-sectional view along a gate length direction, and FIG. 17 (b) is a schematic cross-sectional view along a gate structure cross-sectional direction.
As shown in FIG. 17, in the formed field-effect transistor, the location at which the first semiconductor material layer 51 is originally disposed in the gate 151 may be isolated from the source 131 (or the drain 132) by using a material with a relatively low dielectric constant in the insulation groove 101; the location at which the dummy gate structure 81 is originally disposed in the gate 151 may be isolated from the source 131 (or the drain 132) by using the insulation layer 91. In other words, the gate 151 is almost completely isolated from the source 131 (or the drain 132) through the insulation groove 101 and the insulation layer 91, to reduce a parasitic capacitance of the entire field-effect transistor, thereby improving performance and reliability of the field-effect transistor.
In addition, an embodiment of the present invention further provides a field-effect transistor. The field-effect transistor may be a MOSFET, a tunneling field-effect transistor, or the like. This is not limited in this embodiment of the present invention.
For a fabrication method of a field-effect transistor further provided in an embodiment of the present invention, refer to related content of blocks 401 to 407 in the foregoing embodiment. Therefore, details are not described herein again.
For example, as shown in FIG. 17 (a), in the field-effect transistor provided in this embodiment of the present invention, the gate 151 is disposed in a channel formed between the source 131 and the drain 132, and the gate 151 is not in direct contact with the source 131 (or the drain 132) but is isolated from the source 131 (or the drain 132) through the insulation groove 101. The insulation groove 101 is filled with a material with a relatively low dielectric constant. Therefore, a parasitic capacitance generated when the gate 151 is in direct contact with the source 131 (or the drain 132) can be avoided, and performance and reliability of the field-effect transistor can be improved.
The embodiments of the present invention provide the field-effect transistor and the fabrication method of the field-effect transistor. The fabrication method includes: first forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; further forming, on the isolation layer, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than a length of the first semiconductor material layer in the gate length direction; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove, where the insulation groove is formed in the area other than the sacrificial layer in the first semiconductor material layer, and the sacrificial layer is a projection area of the dummy gate structure in the first semiconductor material layer along a target direction (to be specific, a direction perpendicular to a surface of the isolation layer in which the support structure is disposed), and a dielectric constant of a dielectric filled in the insulation groove is less than a dielectric constant of the first semiconductor material layer; and forming a source and a drain in a preset source drain area along the gate length direction, where the source and the drain may be isolated, through the insulation groove, from a gate material (for example, a high-K dielectric material) filled in the sacrificial layer. Therefore, a parasitic capacitance generated when the source (or the drain) is in direct contact with the gate material can be avoided, a parasitic capacitance of the entire field-effect transistor can be reduced, and performance and reliability of the field-effect transistor can be improved.
A person skilled in the art should be aware that in one or more of the foregoing examples, the functions described in the present invention may be implemented by using hardware, software, firmware, or any combination thereof. When the functions are implemented by software, these functions may be stored in a computer readable medium or transmitted as one or more instructions or code in the computer readable medium. The computer readable medium includes a computer storage medium and a communications medium, where the communications medium includes any medium that enables a computer program to be transmitted from one place to another. The storage medium may be any available medium accessible to a general-purpose or dedicated computer.
The objectives, technical solutions, and beneficial effects of the present invention are further described in detail in the foregoing specific embodiments. It should be understood that the foregoing descriptions are merely specific embodiments of the present invention, but are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, or improvement made based on the technical solutions of the present invention shall fall within the protection scope of the present invention.

Claims (20)

What is claimed is:
1. A fabrication method of a field-effect transistor, comprising:
forming a support structure with a superlattice feature on a semiconductor substrate, wherein the support structure comprises a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure;
forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, wherein a length of the dummy gate structure in a gate length direction is less than a length of the first semiconductor material layer in the gate length direction, and the gate length direction is used to indicate a transport direction of a carrier in the field-effect transistor;
removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove, wherein the sacrificial layer is a projection area of the dummy gate structure in the first semiconductor material layer along a target direction, the insulation groove is filled by insulated dielectric material, and wherein the target direction is a direction perpendicular to a bottom of the semiconductor substrate;
forming a source and a drain in a preset source drain area along the gate length direction, wherein the source and the drain are isolated from the sacrificial layer through the insulation groove;
removing the dummy gate structure and the sacrificial layer; and
adjusting a thickness of the second semiconductor material layer along a gate structure cross-sectional direction, wherein the gate structure cross-sectional direction is perpendicular to the gate length direction.
2. The fabrication method according to claim 1, wherein the removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove comprises:
performing, along the gate length direction, a selective oxidation process on the first semiconductor material layer, so that the area other than the sacrificial layer in the first semiconductor material layer is oxidized to form the insulation groove, wherein the dielectric material filled in the insulation groove is an oxide of the first semiconductor material layer.
3. The fabrication method according to claim 1, wherein the removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove comprises:
performing, along the gate length direction, a selective etching process on the first semiconductor material layer, so that the area other than the sacrificial layer in the first semiconductor material layer is removed to form the insulation groove.
4. The fabrication method according to claim 3, after the insulation groove is formed, further comprising:
filling the insulation groove with a dielectric material whose dielectric constant is less than 3.9.
5. The fabrication method according to claim 4, before the filling the insulation groove with a dielectric material whose dielectric constant is less than 3.9, further comprising:
forming, along the gate length direction, an etching stop layer on a surface of the insulation groove by using an atomic layer deposition (ALD) process.
6. The fabrication method according to claim 1, wherein the adjusting a thickness of the second semiconductor material layer comprises:
reducing the thickness of the second semiconductor material layer from 8 nm to 4 nm by using an etching process.
7. The fabrication method according to claim 1, after the adjusting a thickness of the second semiconductor material layer along a gate structure cross-sectional direction, further comprising:
forming a gate at locations of the removed dummy gate structure and the removed sacrificial layer by using a replacement metal gate (RMG) process.
8. The fabrication method according to claim 1, wherein the forming a support structure with a superlattice feature on a semiconductor substrate comprises:
growing a periodic superlattice structure comprising the first semiconductor material layer and the second semiconductor material layer that are alternately disposed on the semiconductor substrate, wherein a thickness of the first semiconductor material layer and a thickness of the second semiconductor material layer are both less than 50 nm; and
etching the superlattice structure to form a fin support structure.
9. The fabrication method according to claim 1, wherein the forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure comprises:
forming an oxide layer on the support structure; and
forming, on the oxide layer, the dummy gate structure that covers the support structure.
10. The fabrication method according to claim 1, wherein a length of the dummy gate structure in a gate structure cross-sectional direction is less than a length of the isolation layer, wherein the gate structure cross-sectional direction is perpendicular to the gate length direction; and
after the dummy gate structure that covers the support structure is formed on the isolation layer, the method further comprises:
depositing an insulation layer on a periphery of the dummy gate structure, wherein a side wall of the insulation layer is flush with a side wall of the isolation layer.
11. The fabrication method according to claim 1, wherein the insulation groove is filled by air.
12. A field-effect transistor, comprising:
a source and a drain; and
a stack structure, wherein, the stack structure is disposed between the source and the drain, and a gate is alternatively disposed with a semiconductor material layer in the stack structure;
wherein the gate is isolated from the source and the drain through an insulation groove, the insulation groove is filled by insulated dielectric material including air,
the semiconductor material layer has two ends respectively coupled to the source and drain, and a central part between the two ends;
a thickness of the central part is smaller than a thickness of the two ends.
13. The field-effect transistor of claim 12, wherein the dielectric material filled in the insulation groove is an oxide.
14. The field-effect transistor of claim 12, wherein a dielectric constant of the dielectric material in the insulation groove is less than 3.9.
15. The field-effect transistor of claim 12, wherein a surface of the insulation groove comprises an etching stop layer.
16. The field-effect transistor of claim 12, wherein semiconductor material layer is less than 50 nm.
17. The field-effect transistor of claim 12, wherein an isolation layer is disposed on two sides of the gate in a cross-sectional direction, wherein the cross-sectional direction is perpendicular to a gate length direction of the gate.
18. The field-effect transistor of claim 17, wherein a length of the gate in the cross-sectional direction is less than a length of the isolation layer.
19. The field-effect transistor of claim 12, wherein the semiconductor material layer comprises two extension areas and a channel area, the central part is in the channel area, and the two ends are in the two extension areas,
along a gate structure cross-sectional direction, a thickness of the channel area is smaller than a thickness of the two extension areas.
20. The field-effect transistor of claim 19, wherein the two extension areas are formed by diffusion of an impurity atom from the source and the drain.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210313451A1 (en) * 2016-11-21 2021-10-07 Huawei Technologies Co., Ltd. Field-effect transistor and fabrication method of field-effect transistor
US20220384572A1 (en) * 2019-08-30 2022-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor Devices and Methods of Manufacturing

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10211307B2 (en) * 2017-07-18 2019-02-19 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of manufacturing inner spacers in a gate-all-around (GAA) FET through multi-layer spacer replacement
DE102017124637B4 (en) 2017-08-30 2025-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Manufacturing method for a semiconductor device and a semiconductor device
CN109904074B (en) * 2017-12-11 2022-04-08 中芯国际集成电路制造(北京)有限公司 Fully Surrounded Gate Field Effect Transistor and Method of Manufacturing the Same
CN110828541B (en) * 2018-08-14 2023-05-16 中芯国际集成电路制造(北京)有限公司 Semiconductor structures and methods of forming them
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WO2022032488A1 (en) * 2020-08-11 2022-02-17 华为技术有限公司 Field-effect transistor and manufacturing method therefor
US11289586B2 (en) * 2020-08-11 2022-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. Spacer structure for semiconductor device
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CN112397581B (en) * 2020-11-18 2022-06-10 光华临港工程应用技术研发(上海)有限公司 Tunnel field effect transistor and manufacturing method thereof
EP4300549A4 (en) * 2021-03-31 2024-06-19 Huawei Technologies Co., Ltd. FIELD EFFECT TRANSISTOR AND PRODUCTION METHOD THEREOF, AS WELL AS CIRCUIT AND PRINTED CIRCUIT BOARD
CN113284806B (en) * 2021-05-18 2022-04-05 复旦大学 Ring gate device, source-drain preparation method thereof, device preparation method and electronic equipment
CN115692461A (en) * 2021-07-22 2023-02-03 北方集成电路技术创新中心(北京)有限公司 Semiconductor structures and methods of forming them
US12224312B2 (en) * 2021-08-25 2025-02-11 International Business Machines Corporation Field effect transistors with bottom dielectric isolation
CN116072542A (en) * 2022-11-30 2023-05-05 中国科学院微电子研究所 The preparation method of Huanshan TFET device
CN121240497A (en) * 2024-06-24 2025-12-30 华为技术有限公司 Chip, preparation method thereof and electronic equipment
CN119342892B (en) * 2024-09-19 2025-07-11 北京大学 Preparation method of stacked transistor, stacked transistor and semiconductor device

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1702843A (en) 2004-05-25 2005-11-30 三星电子株式会社 Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels
US20080076216A1 (en) 2006-09-25 2008-03-27 Sangwoo Pae Method to fabricate high-k/metal gate transistors using a double capping layer process
CN101197405A (en) 2007-11-30 2008-06-11 华南师范大学 III-V metal oxide semiconductor light-emitting field-effect transistor and preparation method thereof
US7648883B2 (en) * 2004-05-25 2010-01-19 Samsung Electronics Co., Ltd. Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels
US8384069B2 (en) * 2009-05-19 2013-02-26 Commissariat à l'énergie atomique et aux énergies alternatives Semiconductor structure having blocks connected by nanowires
CN103311297A (en) 2012-03-16 2013-09-18 台湾积体电路制造股份有限公司 Finfet having superlattice stressor
US20140001441A1 (en) 2012-06-29 2014-01-02 Seiyon Kim Integration methods to fabricate internal spacers for nanowire devices
CN103730502A (en) 2012-10-10 2014-04-16 三星电子株式会社 Semiconductor device and manufacturing method thereof
US8753942B2 (en) * 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
CN104137265A (en) 2011-12-22 2014-11-05 英特尔公司 Semiconductor device with neck-shaped semiconductor body and method of forming semiconductor body of different width
US20150069328A1 (en) 2013-09-12 2015-03-12 International Business Machines Corporation Stacked nanowire device with variable number of nanowire channels
US9184269B2 (en) * 2013-08-20 2015-11-10 Taiwan Semiconductor Manufacturing Company Limited Silicon and silicon germanium nanowire formation
US20160111337A1 (en) * 2014-10-21 2016-04-21 Samsung Electronics Co., Ltd. Strained stacked nanosheet fets and/or quantum well stacked nanosheet
US20160111495A1 (en) 2014-10-20 2016-04-21 Applied Materials, Inc. Methods and apparatus for forming horizontal gate all around device structures
US9362355B1 (en) 2015-11-13 2016-06-07 International Business Machines Corporation Nanosheet MOSFET with full-height air-gap spacer
US20160211322A1 (en) 2013-10-03 2016-07-21 Intel Corporation Internal spacers for nanowire transistors and method of fabrication thereof
CN106024890A (en) 2015-03-31 2016-10-12 国际商业机器公司 Transistor device and manufacturing method thereof
CN106784001A (en) 2016-11-21 2017-05-31 华为技术有限公司 A kind of field effect transistor and its manufacturing method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9281378B2 (en) * 2012-01-24 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Fin recess last process for FinFET fabrication
KR102033579B1 (en) * 2013-01-25 2019-10-17 삼성전자주식회사 A semiconductor device having nanowire channel structure and method of manufacturing the same
WO2014142952A1 (en) * 2013-03-15 2014-09-18 Intel Corporation Nanowire transistor with underlayer etch stops
US9431512B2 (en) * 2014-06-18 2016-08-30 Globalfoundries Inc. Methods of forming nanowire devices with spacers and the resulting devices
US9748404B1 (en) * 2016-02-29 2017-08-29 International Business Machines Corporation Method for fabricating a semiconductor device including gate-to-bulk substrate isolation
US9997519B1 (en) * 2017-05-03 2018-06-12 International Business Machines Corporation Dual channel structures with multiple threshold voltages
US10074575B1 (en) * 2017-06-21 2018-09-11 International Business Machines Corporation Integrating and isolating nFET and pFET nanosheet transistors on a substrate
US10957601B2 (en) * 2018-10-11 2021-03-23 International Business Machines Corporation Self-aligned fin recesses in nanosheet field effect transistors
US10734286B1 (en) * 2019-02-07 2020-08-04 International Business Machines Corporation Multiple dielectrics for gate-all-around transistors
US10700064B1 (en) * 2019-02-15 2020-06-30 International Business Machines Corporation Multi-threshold voltage gate-all-around field-effect transistor devices with common gates
US10998234B2 (en) * 2019-05-14 2021-05-04 International Business Machines Corporation Nanosheet bottom isolation and source or drain epitaxial growth

Patent Citations (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7648883B2 (en) * 2004-05-25 2010-01-19 Samsung Electronics Co., Ltd. Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels
CN1702843A (en) 2004-05-25 2005-11-30 三星电子株式会社 Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels
US20080076216A1 (en) 2006-09-25 2008-03-27 Sangwoo Pae Method to fabricate high-k/metal gate transistors using a double capping layer process
CN101197405A (en) 2007-11-30 2008-06-11 华南师范大学 III-V metal oxide semiconductor light-emitting field-effect transistor and preparation method thereof
US8384069B2 (en) * 2009-05-19 2013-02-26 Commissariat à l'énergie atomique et aux énergies alternatives Semiconductor structure having blocks connected by nanowires
US8753942B2 (en) * 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
CN104137265A (en) 2011-12-22 2014-11-05 英特尔公司 Semiconductor device with neck-shaped semiconductor body and method of forming semiconductor body of different width
CN103311297A (en) 2012-03-16 2013-09-18 台湾积体电路制造股份有限公司 Finfet having superlattice stressor
US20150162447A1 (en) 2012-03-16 2015-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET Having Superlattice Stressor
US20140001441A1 (en) 2012-06-29 2014-01-02 Seiyon Kim Integration methods to fabricate internal spacers for nanowire devices
CN103730502A (en) 2012-10-10 2014-04-16 三星电子株式会社 Semiconductor device and manufacturing method thereof
US20160056236A1 (en) 2013-08-20 2016-02-25 Taiwan Semiconductor Manufacturing Company Limited Silicon and silicon germanium nanowire formation
US9184269B2 (en) * 2013-08-20 2015-11-10 Taiwan Semiconductor Manufacturing Company Limited Silicon and silicon germanium nanowire formation
US20150069328A1 (en) 2013-09-12 2015-03-12 International Business Machines Corporation Stacked nanowire device with variable number of nanowire channels
US20160211322A1 (en) 2013-10-03 2016-07-21 Intel Corporation Internal spacers for nanowire transistors and method of fabrication thereof
US20160111495A1 (en) 2014-10-20 2016-04-21 Applied Materials, Inc. Methods and apparatus for forming horizontal gate all around device structures
US20160111337A1 (en) * 2014-10-21 2016-04-21 Samsung Electronics Co., Ltd. Strained stacked nanosheet fets and/or quantum well stacked nanosheet
CN106024890A (en) 2015-03-31 2016-10-12 国际商业机器公司 Transistor device and manufacturing method thereof
US20170207404A1 (en) 2015-03-31 2017-07-20 International Business Machines Corporation Transistor device with vertical carbon nanotube (cnt) arrays or non-vertical tapered cnt arrays
US9362355B1 (en) 2015-11-13 2016-06-07 International Business Machines Corporation Nanosheet MOSFET with full-height air-gap spacer
CN106784001A (en) 2016-11-21 2017-05-31 华为技术有限公司 A kind of field effect transistor and its manufacturing method

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
H. Mertens et al, Gate-All-Around MOSFETs based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Si Substrates. 2016 Symposium on VLSI Technology Digest of Technical Papers, 2 pages.
Isaac Lauer et al, Si Nanowire CMOS Fabricated with Minimal Deviation from RMG FinFET Technology Showing Record Performance. 2015 Symposium on VLSI Technology Digest of Technical Papers, 2 pages.
Kelin J. Kuhn, Considerations for Ultimate CMOS Scaling. IEEE Transactions on Electron Devices, vol. 59, No. 7, Jul. 2012, 16 pages.
Poortmans J et al: "Theoretical calculation and experimental evidence of the real and apparent bandgap narrowing due to heavy doping in p-type Si and strained Si"1"—"xGe"x layers", Solid State Electronics, Elsevier Science Publishers, Barking, GB, vol. 36, No. 12, Dec. 1, 1993, pp. 1763-1771, XP025749016, 9 pages.
POORTMANS, J. ; JAIN, S.C. ; TOTTERDELL, D.H.J. ; CAYMAX, M. ; NIJS, J.F. ; MERTENS, R.P. ; VAN OVERSTRAETEN, R.: "Theoretical calculation and experimental evidence of the real and apparent bandgap narrowing due to heavy doping in p-type Si and strained Si"1"-"xGe"x layers", SOLID STATE ELECTRONICS., ELSEVIER SCIENCE PUBLISHERS, BARKING., GB, vol. 36, no. 12, 1 December 1993 (1993-12-01), GB, pages 1763 - 1771, XP025749016, ISSN: 0038-1101, DOI: 10.1016/0038-1101(93)90224-E
S. Bangsaruntip et al, Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond. 2013 IEEE, 4 pages.
S. G. Hur et al., "A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies," 2013 IEEE International Electron Devices Meeting, Washington, DC, 2013, 4 pages.

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210313451A1 (en) * 2016-11-21 2021-10-07 Huawei Technologies Co., Ltd. Field-effect transistor and fabrication method of field-effect transistor
US11664440B2 (en) * 2016-11-21 2023-05-30 Huawei Technologies Co., Ltd. Field-effect transistor and fabrication method of field-effect transistor
US20220384572A1 (en) * 2019-08-30 2022-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor Devices and Methods of Manufacturing

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