US11032543B2

US11032543B2 - Method and apparatus for video coding

Info

Publication number: US11032543B2
Application number: US16/824,440
Authority: US
Inventors: Xin Zhao; Xiang Li; Shan Liu
Original assignee: Tencent America LLC
Current assignee: Tencent America LLC
Priority date: 2019-03-22
Filing date: 2020-03-19
Publication date: 2021-06-08
Anticipated expiration: 2040-03-19
Also published as: CN113994676A; JP7271675B2; EP3871413A4; US20200304789A1; WO2020197996A1; JP2022515799A; EP3871413A1

Abstract

An apparatus for video decoding that includes processing circuitry. The processing circuitry can be configured to receive a coding block having a width of W pixels and a height of H pixels, and partition the coding block into sub processing units (SPUs) each having a width of a lesser of W or K pixels and a height of a lesser of H or K pixels, where K is a dimension of a virtual pipeline data unit (VPDU) having an area of K×K pixels. Each SPU is partitioned into transform units with each transform unit having a maximum allowable transform unit size of M pixels.

Description

INCORPORATION BY REFERENCE

This present application claims the benefit of priority to U.S. Provisional Application No. 62/822,757, “VPDU Compatible Max Transform Control” filed on Mar. 22, 2019, which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present disclosure describes embodiments generally related to video coding.

BACKGROUND

The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

Video coding and decoding can be performed using inter-picture prediction with motion compensation. Uncompressed digital video can include a series of pictures, each picture having a spatial dimension of, for example, 1920×1080 luminance samples and associated chrominance samples. The series of pictures can have a fixed or variable picture rate (informally also known as frame rate), of, for example 60 pictures per second or 60 Hz. Uncompressed video has significant bitrate requirements. For example, 1080p60 4:2:0 video at 8 bit per sample (1920×1080 luminance sample resolution at 60 Hz frame rate) requires close to 1.5 Gbit/s bandwidth. An hour of such video requires more than 600 GBytes of storage space.

One purpose of video coding and decoding can be the reduction of redundancy in the input video signal, through compression. Compression can help reduce the aforementioned bandwidth or storage space requirements, in some cases by two orders of magnitude or more. Both lossless and lossy compression, as well as a combination thereof can be employed. Lossless compression refers to techniques where an exact copy of the original signal can be reconstructed from the compressed original signal. When using lossy compression, the reconstructed signal may not be identical to the original signal, but the distortion between original and reconstructed signals is small enough to make the reconstructed signal useful for the intended application. In the case of video, lossy compression is widely employed. The amount of distortion tolerated depends on the application; for example, users of certain consumer streaming applications may tolerate higher distortion than users of television distribution applications. The compression ratio achievable can reflect that: higher allowable/tolerable distortion can yield higher compression ratios.

A video encoder and decoder can utilize techniques from several broad categories, including, for example, motion compensation, transform, quantization, and entropy coding.

Video codec technologies can include techniques known as intra coding. In intra coding, sample values are represented without reference to samples or other data from previously reconstructed reference pictures. In some video codecs, the picture is spatially subdivided into blocks of samples. When all blocks of samples are coded in intra mode, that picture can be an intra picture. Intra pictures and their derivations such as independent decoder refresh pictures, can be used to reset the decoder state and can, therefore, be used as the first picture in a coded video bitstream and a video session, or as a still image. The samples of an intra block can be exposed to a transform, and the transform coefficients can be quantized before entropy coding. Intra prediction can be a technique that minimizes sample values in the pre-transform domain In some cases, the smaller the DC value after a transform is, and the smaller the AC coefficients are, the fewer the bits that are required at a given quantization step size to represent the block after entropy coding.

Traditional intra coding such as known from, for example MPEG-2 generation coding technologies, does not use intra prediction. However, some newer video compression technologies include techniques that attempt, from, for example, surrounding sample data and/or metadata obtained during the encoding/decoding of spatially neighboring, and preceding in decoding order, blocks of data. Such techniques are henceforth called “intra prediction” techniques. Note that in at least some cases, intra prediction is only using reference data from the current picture under reconstruction and not from reference pictures.

There can be many different forms of intra prediction. When more than one of such techniques can be used in a given video coding technology, the technique in use can be coded in an intra prediction mode. In certain cases, modes can have submodes and/or parameters, and those can be coded individually or included in the mode codeword. Which codeword to use for a given mode/submode/parameter combination can have an impact in the coding efficiency gain through intra prediction, and so can the entropy coding technology used to translate the codewords into a bitstream.

A certain mode of intra prediction was introduced with H.264, refined in H.265, and further refined in newer coding technologies such as joint exploration model (JEM), versatile video coding (VVC), and benchmark set (BMS). A predictor block can be formed using neighboring sample values belonging to already available samples. Sample values of neighboring samples are copied into the predictor block according to a direction. A reference to the direction in use can be coded in the bitstream or may itself be predicted.

Motion compensation can be a lossy compression technique and can relate to techniques where a block of sample data from a previously reconstructed picture or part thereof (reference picture), after being spatially shifted in a direction indicated by a motion vector (MV henceforth), is used for the prediction of a newly reconstructed picture or picture part. In some cases, the reference picture can be the same as the picture currently under reconstruction. MVs can have two dimensions X and Y, or three dimensions, the third being an indication of the reference picture in use (the latter, indirectly, can be a time dimension).

In some video compression techniques, an MV applicable to a certain area of sample data can be predicted from other MVs, for example from those related to another area of sample data spatially adjacent to the area under reconstruction, and preceding that MV in decoding order. Doing so can substantially reduce the amount of data required for coding the MV, thereby removing redundancy and increasing compression. MV prediction can work effectively, for example, because when coding an input video signal derived from a camera (known as natural video) there is a statistical likelihood that areas larger than the area to which a single MV is applicable move in a similar direction and, therefore, can in some cases be predicted using a similar motion vector derived from MVs of neighboring area. That results in the MV found for a given area to be similar or the same as the MV predicted from the surrounding MVs, and that in turn can be represented, after entropy coding, in a smaller number of bits than what would be used if coding the MV directly. In some cases, MV prediction can be an example of lossless compression of a signal (namely: the MVs) derived from the original signal (namely: the sample stream). In other cases, MV prediction itself can be lossy, for example because of rounding errors when calculating a predictor from several surrounding MVs.

Various MV prediction mechanisms are described in H.265/HEVC (ITU-T Rec. H.265, “High Efficiency Video Coding”, December 2016). Out of the many MV prediction mechanisms that H.265 offers, described here is a technique henceforth referred to as “spatial merge”.

Referring to FIG. 1, a current block (101) comprises samples that have been found by the encoder during the motion search process to be predictable from a previous block of the same size that has been spatially shifted. Instead of coding that MV directly, the MV can be derived from metadata associated with one or more reference pictures, for example from the most recent (in decoding order) reference picture, using the MV associated with either one of five surrounding samples, denoted A0, A1, and B0, B1, B2 (102 through 106, respectively). In H.265, the MV prediction can use predictors from the same reference picture that the neighboring block is using.

SUMMARY

Aspects of the disclosure provide methods and apparatuses for video encoding/decoding. In some examples, an apparatus for video decoding includes receiving circuitry and processing circuitry. The processing circuitry can be configured to receive a coding block having a width of W pixels and a height of H pixels, and partition the coding block into sub processing units (SPUs), each having a width of a lesser of W or K pixels and a height of a lesser of H or K pixels, where K is a dimension of a virtual pipeline data unit (VPDU) having an area of K×K pixels. Each SPU is partitioned into transform units with each transform unit having a maximum allowable transform unit size of M pixels.

In an embodiment, a syntax element can be received in a bitstream indicating the maximum allowable transform unit size of M pixels. The transform units of the SPUs can be processed according to an SPU processing order. In an example, the SPU processing order for processing the SPUs is one of a raster scan order, a vertical scan order, a zig-zag order, or a diagonal scan order. Additionally, an order for processing the transform units within each SPU is one of a raster scan order, a vertical scan order, a zig-zag order, or a diagonal scan order. In an example, the SPU processing order and an order for processing the transform units within each SPU are both a raster scan order. Further, in an embodiment, K is 64 and M is 32.

Aspects of the disclosure also provide a non-transitory computer-readable medium storing instructions which when executed by a computer for video decoding cause the computer to perform the method for video decoding.

BRIEF DESCRIPTION OF THE DRAWINGS

Further features, the nature, and various advantages of the disclosed subject matter will be more apparent from the following detailed description and the accompanying drawings in which:

FIG. 1 is a schematic illustration of a current block and its surrounding spatial merge candidates in one example.

FIG. 2 is a schematic illustration of a simplified block diagram of a communication system (200) in accordance with an embodiment.

FIG. 3 is a schematic illustration of a simplified block diagram of a communication system (300) in accordance with an embodiment.

FIG. 4 is a schematic illustration of a simplified block diagram of a decoder in accordance with an embodiment.

FIG. 5 is a schematic illustration of a simplified block diagram of an encoder in accordance with an embodiment.

FIG. 6 shows a block diagram of an encoder in accordance with another embodiment.

FIG. 7 shows a block diagram of a decoder in accordance with another embodiment.

FIG. 8A shows a CTU that is partitioned with a quadtree plus binary tree (QTBT) structure (820).

FIG. 8B shows the QTBT structure (820).

FIG. 9A shows a horizontal center-side triple-tree.

FIG. 9B shows a vertical center-side triple-tree.

FIGS. 10A-10D show transform core matrices of 4-point, 8-point, 16-point and 32-point DCT-2 transform, respectively.

FIGS. 11A-11E shows a 64×64 transform core matrix of the 64-point DCT-2 transform.

FIG. 12 shows transform basis functions of the selected discrete sine transform (DST)/discrete cosine transform (DCT) transforms of an adaptive multiple transform (AMT).

FIG. 13 shows a table (1300) illustrating a mapping relationship between an mts_idx value and respective horizontal or vertical transforms.

FIGS. 14A-14D show transform core matrices of DST-7 transform.

FIGS. 15A-15D show transform core matrices of DCT-8 transform.

FIG. 16 shows the number of sub-partitions depending on the block size.

FIG. 17 shows the scenario where a block is partitioned into two sub-partitions.

FIG. 18 shows the scenario where a block is partitioned into four sub-partitions.

FIGS. 19A-19B shows an example syntax table (1900) that includes related syntax elements signaled for an intra sub-partition (ISP) coding mode.

FIGS. 20A-20D show sub-block types, sizes and positions supported in a sub-block transform (SBT).

FIGS. 21A-21I show changes to a specification text of a video coding standard when SBT is used.

FIG. 22 shows different YUV formats (e.g., 4:4:4, 4:2:2, 4:1:1, and 4:2:0) used in some embodiments.

FIG. 23 shows examples of disallowed ternary tree (TT) and binary tree (BT) partitioning.

FIG. 24 shows a coding block (2410) having a size of 128×64 samples.

FIG. 25 shows a coding block (2510) having a size of 128×32 samples.

FIG. 26 shows a coding block (2610) having a size of 128×32 samples.

FIG. 27 shows a flow chart outlining a transform block partitioning and processing process (2700) according to an embodiment of the disclosure.

FIG. 28 is a schematic illustration of a computer system in accordance with an embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS I. Video Coding Encoder and Decoder

FIG. 2 illustrates a simplified block diagram of a communication system (200) according to an embodiment of the present disclosure. The communication system (200) includes a plurality of terminal devices that can communicate with each other, via, for example, a network (250). For example, the communication system (200) includes a first pair of terminal devices (210) and (220) interconnected via the network (250). In the FIG. 2 example, the first pair of terminal devices (210) and (220) performs unidirectional transmission of data. For example, the terminal device (210) may code video data (e.g., a stream of video pictures that are captured by the terminal device (210)) for transmission to the other terminal device (220) via the network (250). The encoded video data can be transmitted in the form of one or more coded video bitstreams. The terminal device (220) may receive the coded video data from the network (250), decode the coded video data to recover the video pictures and display video pictures according to the recovered video data. Unidirectional data transmission may be common in media serving applications and the like.

In another example, the communication system (200) includes a second pair of terminal devices (230) and (240) that performs bidirectional transmission of coded video data that may occur, for example, during videoconferencing. For bidirectional transmission of data, in an example, each terminal device of the terminal devices (230) and (240) may code video data (e.g., a stream of video pictures that are captured by the terminal device) for transmission to the other terminal device of the terminal devices (230) and (240) via the network (250). Each terminal device of the terminal devices (230) and (240) also may receive the coded video data transmitted by the other terminal device of the terminal devices (230) and (240), and may decode the coded video data to recover the video pictures and may display video pictures at an accessible display device according to the recovered video data.

In the FIG. 2 example, the terminal devices (210), (220), (230) and (240) may be illustrated as servers, personal computers and smart phones but the principles of the present disclosure may be not so limited. Embodiments of the present disclosure find application with laptop computers, tablet computers, media players and/or dedicated video conferencing equipment. The network (250) represents any number of networks that convey coded video data among the terminal devices (210), (220), (230) and (240), including for example wireline (wired) and/or wireless communication networks. The communication network (250) may exchange data in circuit-switched and/or packet-switched channels. Representative networks include telecommunications networks, local area networks, wide area networks and/or the Internet. For the purposes of the present discussion, the architecture and topology of the network (250) may be immaterial to the operation of the present disclosure unless explained herein below.

FIG. 3 illustrates, as an example for an application for the disclosed subject matter, the placement of a video encoder and a video decoder in a streaming environment. The disclosed subject matter can be equally applicable to other video enabled applications, including, for example, video conferencing, digital TV, storing of compressed video on digital media including CD, DVD, memory stick and the like, and so on.

A streaming system may include a capture subsystem (313), that can include a video source (301), for example a digital camera, creating for example a stream of video pictures (302) that are uncompressed. In an example, the stream of video pictures (302) includes samples that are taken by the digital camera. The stream of video pictures (302), depicted as a bold line to emphasize a high data volume when compared to encoded video data (304) (or coded video bitstreams), can be processed by an electronic device (320) that includes a video encoder (303) coupled to the video source (301). The video encoder (303) can include hardware, software, or a combination thereof to enable or implement aspects of the disclosed subject matter as described in more detail below. The encoded video data (304) (or encoded video bitstream (304)), depicted as a thin line to emphasize the lower data volume when compared to the stream of video pictures (302), can be stored on a streaming server (305) for future use. One or more streaming client subsystems, such as client subsystems (306) and (308) in FIG. 3 can access the streaming server (305) to retrieve copies (307) and (309) of the encoded video data (304). A client subsystem (306) can include a video decoder (310), for example, in an electronic device (330). The video decoder (310) decodes the incoming copy (307) of the encoded video data and creates an outgoing stream of video pictures (311) that can be rendered on a display (312) (e.g., display screen) or other rendering device (not depicted). In some streaming systems, the encoded video data (304), (307), and (309) (e.g., video bitstreams) can be encoded according to certain video coding/compression standards. Examples of those standards include ITU-T Recommendation H.265. In an example, a video coding standard under development is informally known as Versatile Video Coding (VVC). The disclosed subject matter may be used in the context of VVC.

It is noted that the electronic devices (320) and (330) can include other components (not shown). For example, the electronic device (320) can include a video decoder (not shown) and the electronic device (330) can include a video encoder (not shown) as well.

FIG. 4 shows a block diagram of a video decoder (410) according to an embodiment of the present disclosure. The video decoder (410) can be included in an electronic device (430). The electronic device (430) can include a receiver (431) (e.g., receiving circuitry). The video decoder (410) can be used in the place of the video decoder (310) in the FIG. 3 example.

The receiver (431) may receive one or more coded video sequences to be decoded by the video decoder (410); in the same or another embodiment, one coded video sequence at a time, where the decoding of each coded video sequence is independent from other coded video sequences. The coded video sequence may be received from a channel (401), which may be a hardware/software link to a storage device which stores the encoded video data. The receiver (431) may receive the encoded video data with other data, for example, coded audio data and/or ancillary data streams, that may be forwarded to their respective using entities (not depicted). The receiver (431) may separate the coded video sequence from the other data. To combat network jitter, a buffer memory (415) may be coupled in between the receiver (431) and an entropy decoder/parser (420) (“parser (420)” henceforth). In certain applications, the buffer memory (415) is part of the video decoder (410). In others, it can be outside of the video decoder (410) (not depicted). In still others, there can be a buffer memory (not depicted) outside of the video decoder (410), for example to combat network jitter, and in addition another buffer memory (415) inside the video decoder (410), for example to handle playout timing. When the receiver (431) is receiving data from a store/forward device of sufficient bandwidth and controllability, or from an isosynchronous network, the buffer memory (415) may not be needed, or can be small. For use on best effort packet networks such as the Internet, the buffer memory (415) may be required, can be comparatively large and can be advantageously of adaptive size, and may at least partially be implemented in an operating system or similar elements (not depicted) outside of the video decoder (410).

The video decoder (410) may include the parser (420) to reconstruct symbols (421) from the coded video sequence. Categories of those symbols include information used to manage operation of the video decoder (410), and potentially information to control a rendering device such as a render device (412) (e.g., a display screen) that is not an integral part of the electronic device (430) but can be coupled to the electronic device (430), as was shown in FIG. 4. The control information for the rendering device(s) may be in the form of Supplemental Enhancement Information (SEI messages) or Video Usability Information (VUI) parameter set fragments (not depicted). The parser (420) may parse/entropy-decode the coded video sequence that is received. The coding of the coded video sequence can be in accordance with a video coding technology or standard, and can follow various principles, including variable length coding, Huffman coding, arithmetic coding with or without context sensitivity, and so forth. The parser (420) may extract from the coded video sequence, a set of subgroup parameters for at least one of the subgroups of pixels in the video decoder, based upon at least one parameter corresponding to the group. Subgroups can include Groups of Pictures (GOPs), pictures, tiles, slices, macroblocks, Coding Units (CUs), blocks, Transform Units (TUs), Prediction Units (PUs) and so forth. The parser (420) may also extract from the coded video sequence information such as transform coefficients, quantizer parameter values, motion vectors, and so forth.

The parser (420) may perform an entropy decoding/parsing operation on the video sequence received from the buffer memory (415), so as to create symbols (421).

Reconstruction of the symbols (421) can involve multiple different units depending on the type of the coded video picture or parts thereof (such as: inter and intra picture, inter and intra block), and other factors. Which units are involved, and how, can be controlled by the subgroup control information that was parsed from the coded video sequence by the parser (420). The flow of such subgroup control information between the parser (420) and the multiple units below is not depicted for clarity.

Beyond the functional blocks already mentioned, the video decoder (410) can be conceptually subdivided into a number of functional units as described below. In a practical implementation operating under commercial constraints, many of these units interact closely with each other and can, at least partly, be integrated into each other. However, for the purpose of describing the disclosed subject matter, the conceptual subdivision into the functional units below is appropriate.

A first unit is the scaler/inverse transform unit (451). The scaler/inverse transform unit (451) receives a quantized transform coefficient as well as control information, including which transform to use, block size, quantization factor, quantization scaling matrices, etc. as symbol(s) (421) from the parser (420). The scaler/inverse transform unit (451) can output blocks comprising sample values, that can be input into aggregator (455).

In some cases, the output samples of the scaler/inverse transform (451) can pertain to an intra coded block; that is: a block that is not using predictive information from previously reconstructed pictures, but can use predictive information from previously reconstructed parts of the current picture. Such predictive information can be provided by an intra picture prediction unit (452). In some cases, the intra picture prediction unit (452) generates a block of the same size and shape of the block under reconstruction, using surrounding already reconstructed information fetched from the current picture buffer (458). The current picture buffer (458) buffers, for example, partly reconstructed current picture and/or fully reconstructed current picture. The aggregator (455), in some cases, adds, on a per sample basis, the prediction information the intra prediction unit (452) has generated to the output sample information as provided by the scaler/inverse transform unit (451).

In other cases, the output samples of the scaler/inverse transform unit (451) can pertain to an inter coded, and potentially motion compensated block. In such a case, a motion compensation prediction unit (453) can access reference picture memory (457) to fetch samples used for prediction. After motion compensating the fetched samples in accordance with the symbols (421) pertaining to the block, these samples can be added by the aggregator (455) to the output of the scaler/inverse transform unit (451) (in this case called the residual samples or residual signal) so as to generate output sample information. The addresses within the reference picture memory (457) from where the motion compensation prediction unit (453) fetches prediction samples can be controlled by motion vectors, available to the motion compensation prediction unit (453) in the form of symbols (421) that can have, for example X, Y, and reference picture components. Motion compensation also can include interpolation of sample values as fetched from the reference picture memory (457) when sub-sample exact motion vectors are in use, motion vector prediction mechanisms, and so forth.

The output samples of the aggregator (455) can be subject to various loop filtering techniques in the loop filter unit (456). Video compression technologies can include in-loop filter technologies that are controlled by parameters included in the coded video sequence (also referred to as coded video bitstream) and made available to the loop filter unit (456) as symbols (421) from the parser (420), but can also be responsive to meta-information obtained during the decoding of previous (in decoding order) parts of the coded picture or coded video sequence, as well as responsive to previously reconstructed and loop-filtered sample values.

The output of the loop filter unit (456) can be a sample stream that can be output to the render device (412) as well as stored in the reference picture memory (457) for use in future inter-picture prediction.

Certain coded pictures, once fully reconstructed, can be used as reference pictures for future prediction. For example, once a coded picture corresponding to a current picture is fully reconstructed and the coded picture has been identified as a reference picture (by, for example, the parser (420)), the current picture buffer (458) can become a part of the reference picture memory (457), and a fresh current picture buffer can be reallocated before commencing the reconstruction of the following coded picture.

The video decoder (410) may perform decoding operations according to a predetermined video compression technology in a standard, such as ITU-T Rec. H.265. The coded video sequence may conform to a syntax specified by the video compression technology or standard being used, in the sense that the coded video sequence adheres to both the syntax of the video compression technology or standard and the profiles as documented in the video compression technology or standard. Specifically, a profile can select certain tools as the only tools available for use under that profile from all the tools available in the video compression technology or standard. Also necessary for compliance can be that the complexity of the coded video sequence is within bounds as defined by the level of the video compression technology or standard. In some cases, levels restrict the maximum picture size, maximum frame rate, maximum reconstruction sample rate (measured in, for example megasamples per second), maximum reference picture size, and so on. Limits set by levels can, in some cases, be further restricted through Hypothetical Reference Decoder (HRD) specifications and metadata for HRD buffer management signaled in the coded video sequence.

In an embodiment, the receiver (431) may receive additional (redundant) data with the encoded video. The additional data may be included as part of the coded video sequence(s). The additional data may be used by the video decoder (410) to properly decode the data and/or to more accurately reconstruct the original video data. Additional data can be in the form of, for example, temporal, spatial, or signal noise ratio (SNR) enhancement layers, redundant slices, redundant pictures, forward error correction codes, and so on.

FIG. 5 shows a block diagram of a video encoder (503) according to an embodiment of the present disclosure. The video encoder (503) is included in an electronic device (520). The electronic device (520) includes a transmitter (540) (e.g., transmitting circuitry). The video encoder (503) can be used in the place of the video encoder (303) in the FIG. 3 example.

The video encoder (503) may receive video samples from a video source (501) (that is not part of the electronic device (520) in the FIG. 5 example) that may capture video image(s) to be coded by the video encoder (503). In another example, the video source (501) is a part of the electronic device (520).

The video source (501) may provide the source video sequence to be coded by the video encoder (503) in the form of a digital video sample stream that can be of any suitable bit depth (for example: 8 bit, 10 bit, 12 bit, . . . ), any colorspace (for example, BT.601 Y CrCB, RGB, . . . ), and any suitable sampling structure (for example Y CrCb 4:2:0, Y CrCb 4:4:4). In a media serving system, the video source (501) may be a storage device storing previously prepared video. In a videoconferencing system, the video source (501) may be a camera that captures local image information as a video sequence. Video data may be provided as a plurality of individual pictures that impart motion when viewed in sequence. The pictures themselves may be organized as a spatial array of pixels, wherein each pixel can comprise one or more samples depending on the sampling structure, color space, etc. in use. A person skilled in the art can readily understand the relationship between pixels and samples. The description below focuses on samples.

According to an embodiment, the video encoder (503) may code and compress the pictures of the source video sequence into a coded video sequence (543) in real time or under any other time constraints as required by the application. Enforcing appropriate coding speed is one function of a controller (550). In some embodiments, the controller (550) controls other functional units as described below and is functionally coupled to the other functional units. The coupling is not depicted for clarity. Parameters set by the controller (550) can include rate control related parameters (picture skip, quantizer, lambda value of rate-distortion optimization techniques, . . . ), picture size, group of pictures (GOP) layout, maximum motion vector search range, and so forth. The controller (550) can be configured to have other suitable functions that pertain to the video encoder (503) optimized for a certain system design.

In some embodiments, the video encoder (503) is configured to operate in a coding loop. As an oversimplified description, in an example, the coding loop can include a source coder (530) (e.g., responsible for creating symbols, such as a symbol stream, based on an input picture to be coded, and a reference picture(s)), and a (local) decoder (533) embedded in the video encoder (503). The decoder (533) reconstructs the symbols to create the sample data in a similar manner as a (remote) decoder also would create (as any compression between symbols and coded video bitstream is lossless in the video compression technologies considered in the disclosed subject matter). The reconstructed sample stream (sample data) is input to the reference picture memory (534). As the decoding of a symbol stream leads to bit-exact results independent of decoder location (local or remote), the content in the reference picture memory (534) is also bit exact between the local encoder and remote encoder. In other words, the prediction part of an encoder “sees” as reference picture samples exactly the same sample values as a decoder would “see” when using prediction during decoding. This fundamental principle of reference picture synchronicity (and resulting drift, if synchronicity cannot be maintained, for example because of channel errors) is used in some related arts as well.

The operation of the “local” decoder (533) can be the same as of a “remote” decoder, such as the video decoder (410), which has already been described in detail above in conjunction with FIG. 4. Briefly referring also to FIG. 4, however, as symbols are available and encoding/decoding of symbols to a coded video sequence by an entropy coder (545) and the parser (420) can be lossless, the entropy decoding parts of the video decoder (410), including the buffer memory (415), and parser (420) may not be fully implemented in the local decoder (533).

An observation that can be made at this point is that any decoder technology except the parsing/entropy decoding that is present in a decoder also necessarily needs to be present, in substantially identical functional form, in a corresponding encoder. For this reason, the disclosed subject matter focuses on decoder operation. The description of encoder technologies can be abbreviated as they are the inverse of the comprehensively described decoder technologies. Only in certain areas a more detail description is required and provided below.

During operation, in some examples, the source coder (530) may perform motion compensated predictive coding, which codes an input picture predictively with reference to one or more previously-coded picture from the video sequence that were designated as “reference pictures”. In this manner, the coding engine (532) codes differences between pixel blocks of an input picture and pixel blocks of reference picture(s) that may be selected as prediction reference(s) to the input picture.

The local video decoder (533) may decode coded video data of pictures that may be designated as reference pictures, based on symbols created by the source coder (530). Operations of the coding engine (532) may advantageously be lossy processes. When the coded video data may be decoded at a video decoder (not shown in FIG. 5), the reconstructed video sequence typically may be a replica of the source video sequence with some errors. The local video decoder (533) replicates decoding processes that may be performed by the video decoder on reference pictures and may cause reconstructed reference pictures to be stored in the reference picture cache (534). In this manner, the video encoder (503) may store copies of reconstructed reference pictures locally that have common content as the reconstructed reference pictures that will be obtained by a far-end video decoder (absent transmission errors).

The predictor (535) may perform prediction searches for the coding engine (532). That is, for a new picture to be coded, the predictor (535) may search the reference picture memory (534) for sample data (as candidate reference pixel blocks) or certain metadata such as reference picture motion vectors, block shapes, and so on, that may serve as an appropriate prediction reference for the new pictures. The predictor (535) may operate on a sample block-by-pixel block basis to find appropriate prediction references. In some cases, as determined by search results obtained by the predictor (535), an input picture may have prediction references drawn from multiple reference pictures stored in the reference picture memory (534).

The controller (550) may manage coding operations of the source coder (530), including, for example, setting of parameters and subgroup parameters used for encoding the video data.

Output of all aforementioned functional units may be subjected to entropy coding in the entropy coder (545). The entropy coder (545) translates the symbols as generated by the various functional units into a coded video sequence, by lossless compressing the symbols according to technologies such as Huffman coding, variable length coding, arithmetic coding, and so forth.

The transmitter (540) may buffer the coded video sequence(s) as created by the entropy coder (545) to prepare for transmission via a communication channel (560), which may be a hardware/software link to a storage device which would store the encoded video data. The transmitter (540) may merge coded video data from the video coder (503) with other data to be transmitted, for example, coded audio data and/or ancillary data streams (sources not shown).

The controller (550) may manage operation of the video encoder (503). During coding, the controller (550) may assign to each coded picture a certain coded picture type, which may affect the coding techniques that may be applied to the respective picture. For example, pictures often may be assigned as one of the following picture types:

An Intra Picture (I picture) may be one that may be coded and decoded without using any other picture in the sequence as a source of prediction. Some video codecs allow for different types of intra pictures, including, for example Independent Decoder Refresh (“IDR”) Pictures. A person skilled in the art is aware of those variants of I pictures and their respective applications and features.

A predictive picture (P picture) may be one that may be coded and decoded using intra prediction or inter prediction using at most one motion vector and reference index to predict the sample values of each block.

A bi-directionally predictive picture (B Picture) may be one that may be coded and decoded using intra prediction or inter prediction using at most two motion vectors and reference indices to predict the sample values of each block. Similarly, multiple-predictive pictures can use more than two reference pictures and associated metadata for the reconstruction of a single block.

Source pictures commonly may be subdivided spatially into a plurality of sample blocks (for example, blocks of 4×4, 8×8, 4×8, or 16×16 samples each) and coded on a block-by-block basis. Blocks may be coded predictively with reference to other (already coded) blocks as determined by the coding assignment applied to the blocks' respective pictures. For example, blocks of I pictures may be coded non-predictively or they may be coded predictively with reference to already coded blocks of the same picture (spatial prediction or intra prediction). Pixel blocks of P pictures may be coded predictively, via spatial prediction or via temporal prediction with reference to one previously coded reference picture. Blocks of B pictures may be coded predictively, via spatial prediction or via temporal prediction with reference to one or two previously coded reference pictures.

The video encoder (503) may perform coding operations according to a predetermined video coding technology or standard, such as ITU-T Rec. H.265. In its operation, the video encoder (503) may perform various compression operations, including predictive coding operations that exploit temporal and spatial redundancies in the input video sequence. The coded video data, therefore, may conform to a syntax specified by the video coding technology or standard being used.

In an embodiment, the transmitter (540) may transmit additional data with the encoded video. The source coder (530) may include such data as part of the coded video sequence. Additional data may comprise temporal/spatial/SNR enhancement layers, other forms of redundant data such as redundant pictures and slices, SEI messages, VUI parameter set fragments, and so on.

A video may be captured as a plurality of source pictures (video pictures) in a temporal sequence. Intra-picture prediction (often abbreviated to intra prediction) makes use of spatial correlation in a given picture, and inter-picture prediction makes uses of the (temporal or other) correlation between the pictures. In an example, a specific picture under encoding/decoding, which is referred to as a current picture, is partitioned into blocks. When a block in the current picture is similar to a reference block in a previously coded and still buffered reference picture in the video, the block in the current picture can be coded by a vector that is referred to as a motion vector. The motion vector points to the reference block in the reference picture, and can have a third dimension identifying the reference picture, in case multiple reference pictures are in use.

In some embodiments, a bi-prediction technique can be used in the inter-picture prediction. According to the bi-prediction technique, two reference pictures, such as a first reference picture and a second reference picture that are both prior in decoding order to the current picture in the video (but may be in the past and future, respectively, in display order) are used. A block in the current picture can be coded by a first motion vector that points to a first reference block in the first reference picture, and a second motion vector that points to a second reference block in the second reference picture. The block can be predicted by a combination of the first reference block and the second reference block.

Further, a merge mode technique can be used in the inter-picture prediction to improve coding efficiency.

According to some embodiments of the disclosure, predictions, such as inter-picture predictions and intra-picture predictions are performed in the unit of blocks. For example, according to the HEVC standard, a picture in a sequence of video pictures is partitioned into coding tree units (CTU) for compression, the CTUs in a picture have the same size, such as 64×64 pixels, 32×32 pixels, or 16×16 pixels. In general, a CTU includes three coding tree blocks (CTBs), which are one luma CTB and two chroma CTBs. Each CTU can be recursively quadtree split into one or multiple coding units (CUs). For example, a CTU of 64×64 pixels can be split into one CU of 64×64 pixels, or 4 CUs of 32×32 pixels, or 16 CUs of 16×16 pixels. In an example, each CU is analyzed to determine a prediction type for the CU, such as an inter prediction type or an intra prediction type. The CU is split into one or more prediction units (PUs) depending on the temporal and/or spatial predictability. Generally, each PU includes a luma prediction block (PB), and two chroma PBs. In an embodiment, a prediction operation in coding (encoding/decoding) is performed in the unit of a prediction block. Using a luma prediction block as an example of a prediction block, the prediction block includes a matrix of values (e.g., luma values) for pixels, such as 8×8 pixels, 16×16 pixels, 8×16 pixels, 16×8 pixels, and the like.

FIG. 6 shows a diagram of a video encoder (603) according to another embodiment of the disclosure. The video encoder (603) is configured to receive a processing block (e.g., a prediction block) of sample values within a current video picture in a sequence of video pictures, and encode the processing block into a coded picture that is part of a coded video sequence. In an example, the video encoder (603) is used in the place of the video encoder (303) in the FIG. 3 example.

In an HEVC example, the video encoder (603) receives a matrix of sample values for a processing block, such as a prediction block of 8×8 samples, and the like. The video encoder (603) determines whether the processing block is best coded using intra mode, inter mode, or bi-prediction mode using, for example, rate-distortion optimization. When the processing block is to be coded in intra mode, the video encoder (603) may use an intra prediction technique to encode the processing block into the coded picture; and when the processing block is to be coded in inter mode or bi-prediction mode, the video encoder (603) may use an inter prediction or bi-prediction technique, respectively, to encode the processing block into the coded picture. In certain video coding technologies, merge mode can be an inter picture prediction submode where the motion vector is derived from one or more motion vector predictors without the benefit of a coded motion vector component outside the predictors. In certain other video coding technologies, a motion vector component applicable to the subject block may be present. In an example, the video encoder (603) includes other components, such as a mode decision module (not shown) to determine the mode of the processing blocks.

In the FIG. 6 example, the video encoder (603) includes the inter encoder (630), an intra encoder (622), a residue calculator (623), a switch (626), a residue encoder (624), a general controller (621), and an entropy encoder (625) coupled together as shown in FIG. 6.

The inter encoder (630) is configured to receive the samples of the current block (e.g., a processing block), compare the block to one or more reference blocks in reference pictures (e.g., blocks in previous pictures and later pictures), generate inter prediction information (e.g., description of redundant information according to inter encoding technique, motion vectors, merge mode information), and calculate inter prediction results (e.g., predicted block) based on the inter prediction information using any suitable technique. In some examples, the reference pictures are decoded reference pictures that are decoded based on the encoded video information.

The intra encoder (622) is configured to receive the samples of the current block (e.g., a processing block), in some cases compare the block to blocks already coded in the same picture, generate quantized coefficients after transform, and in some cases also intra prediction information (e.g., an intra prediction direction information according to one or more intra encoding techniques). In an example, the intra encoder (622) also calculates intra prediction results (e.g., predicted block) based on the intra prediction information and reference blocks in the same picture.

The general controller (621) is configured to determine general control data and control other components of the video encoder (603) based on the general control data. In an example, the general controller (621) determines the mode of the block, and provides a control signal to the switch (626) based on the mode. For example, when the mode is the intra mode, the general controller (621) controls the switch (626) to select the intra mode result for use by the residue calculator (623), and controls the entropy encoder (625) to select the intra prediction information and include the intra prediction information in the bitstream; and when the mode is the inter mode, the general controller (621) controls the switch (626) to select the inter prediction result for use by the residue calculator (623), and controls the entropy encoder (625) to select the inter prediction information and include the inter prediction information in the bitstream.

The residue calculator (623) is configured to calculate a difference (residue data) between the received block and prediction results selected from the intra encoder (622) or the inter encoder (630). The residue encoder (624) is configured to operate based on the residue data to encode the residue data to generate the transform coefficients. In an example, the residue encoder (624) is configured to convert the residue data from a spatial domain to a frequency domain, and generate the transform coefficients. The transform coefficients are then subject to quantization processing to obtain quantized transform coefficients. In various embodiments, the video encoder (603) also includes a residue decoder (628). The residue decoder (628) is configured to perform inverse-transform, and generate the decoded residue data. The decoded residue data can be suitably used by the intra encoder (622) and the inter encoder (630). For example, the inter encoder (630) can generate decoded blocks based on the decoded residue data and inter prediction information, and the intra encoder (622) can generate decoded blocks based on the decoded residue data and the intra prediction information. The decoded blocks are suitably processed to generate decoded pictures and the decoded pictures can be buffered in a memory circuit (not shown) and used as reference pictures in some examples.

The entropy encoder (625) is configured to format the bitstream to include the encoded block. The entropy encoder (625) is configured to include various information according to a suitable standard, such as the HEVC standard. In an example, the entropy encoder (625) is configured to include the general control data, the selected prediction information (e.g., intra prediction information or inter prediction information), the residue information, and other suitable information in the bitstream. Note that, according to the disclosed subject matter, when coding a block in the merge submode of either inter mode or bi-prediction mode, there is no residue information.

FIG. 7 shows a diagram of a video decoder (710) according to another embodiment of the disclosure. The video decoder (710) is configured to receive coded pictures that are part of a coded video sequence, and decode the coded pictures to generate reconstructed pictures. In an example, the video decoder (710) is used in the place of the video decoder (310) in the FIG. 3 example.

In the FIG. 7 example, the video decoder (710) includes an entropy decoder (771), an inter decoder (780), a residue decoder (773), a reconstruction module (774), and an intra decoder (772) coupled together as shown in FIG. 7.

The entropy decoder (771) can be configured to reconstruct, from the coded picture, certain symbols that represent the syntax elements of which the coded picture is made up. Such symbols can include, for example, the mode in which a block is coded (such as, for example, intra mode, inter mode, bi-predicted mode, the latter two in merge submode or another submode), prediction information (such as, for example, intra prediction information or inter prediction information) that can identify certain sample or metadata that is used for prediction by the intra decoder (772) or the inter decoder (780), respectively, residual information in the form of, for example, quantized transform coefficients, and the like. In an example, when the prediction mode is inter or bi-predicted mode, the inter prediction information is provided to the inter decoder (780); and when the prediction type is the intra prediction type, the intra prediction information is provided to the intra decoder (772). The residual information can be subject to inverse quantization and is provided to the residue decoder (773).

The inter decoder (780) is configured to receive the inter prediction information, and generate inter prediction results based on the inter prediction information.

The intra decoder (772) is configured to receive the intra prediction information, and generate prediction results based on the intra prediction information.

The residue decoder (773) is configured to perform inverse quantization to extract de-quantized transform coefficients, and process the de-quantized transform coefficients to convert the residual from the frequency domain to the spatial domain. The residue decoder (773) may also require certain control information (to include the Quantizer Parameter (QP)), and that information may be provided by the entropy decoder (771) (data path not depicted as this may be low volume control information only).

The reconstruction module (774) is configured to combine, in the spatial domain, the residual as output by the residue decoder (773) and the prediction results (as output by the inter or intra prediction modules as the case may be) to form a reconstructed block, that may be part of the reconstructed picture, which in turn may be part of the reconstructed video. It is noted that other suitable operations, such as a deblocking operation and the like, can be performed to improve the visual quality.

It is noted that the video encoders (303), (503), and (603), and the video decoders (310), (410), and (710) can be implemented using any suitable technique. In an embodiment, the video encoders (303), (503), and (603), and the video decoders (310), (410), and (710) can be implemented using one or more integrated circuits. In another embodiment, the video encoders (303), (503), and (503), and the video decoders (310), (410), and (710) can be implemented using one or more processors that execute software instructions.

II. Transform Processing Techniques 1. Quadtree Block Partitioning Structure

A block partitioning structure is referred to as a coding tree. In some embodiments, by using a quadtree structure, a coding tree unit (CTU) is split into coding units (CUs) to adapt to various local characteristics. A decision on whether to code a picture area using an inter-picture (temporal) or intra-picture (spatial) prediction is made at CU level. Each CU can be further split into one, two, or four prediction units (PUs) according to a PU splitting type. Inside one PU, a same prediction process is applied and relevant information is transmitted to a decoder on a PU basis.

After obtaining a residual block by applying a prediction process based on the PU splitting type, a CU can be partitioned into transform units (TUs) according to another quadtree structure. As can be seen, there are multiple partition conceptions including CU, PU, and TU. In some embodiments, a CU or a TU can only be square shape, while a PU may be square or rectangular shape. In some embodiments, one coding block may be further split into four square sub-blocks, and transform is performed on each sub-block, i.e., TU. Each TU can be further split recursively into smaller Tus using a quadtree structure which is called residual quadtree (RQT).

At a picture boundary, in some embodiments, implicit quadtree split can be employed so that a block will keep quad-tree splitting until the size fits the picture boundary.

2. Quadtree Plus Binary Tree (QTBT) Block Partitioning Structure

In some embodiments, a quadtree plus binary tree (QTBT) structure is employed. The QTBT structure removes the concepts of multiple partition types (the CU, PU and TU concepts), and supports more flexibility for CU partition shapes. In the QTBT block structure, a CU can have either a square or rectangular shape.

FIG. 8A shows a CTU (810) that is partitioned by using a QTBT structure (820) shown in FIG. 8B. The CTU (810) is first partitioned by a quadtree structure. The quadtree leaf nodes are further partitioned by a binary tree structure or a quadtree structure. There can be two splitting types, symmetric horizontal splitting and symmetric vertical splitting, in the binary tree splitting. The binary tree leaf nodes are called CUs that can be used for prediction and transform processing without any further partitioning. Accordingly, CU, PU and TU have the same block size in the QTBT coding block structure.

In some embodiments, a CU can include coding blocks (CBs) of different color components. For example, one CU contains one luma CB and two chroma CBs in the case of P and B slices of the 4:2:0 chroma format. A CU can include a CB of a single color component. For example, one CU contains only one luma CB or just two chroma CBs in the case of I slices.

The following parameters are defined for the QTBT partitioning scheme in some embodiments:

- CTU size: the root node size of a quadtree, e.g. the same concept as in HEVC.
- MinQTSize: the minimum allowed quadtree leaf node size.
- MaxBTSize: the maximum allowed binary tree root node size.
- MaxBTDepth: the maximum allowed binary tree depth.
- MinBTSize: the minimum allowed binary tree leaf node size.

In one example of the QTBT partitioning structure, the CTU size is set as 128×128 luma samples with two corresponding 64×64 blocks of chroma samples, the MinQTSize is set as 16×16, the MaxBTSize is set as 64×64, the MinBTSize (for both width and height) is set as 4×4, and the MaxBTDepth is set as 4. The quadtree partitioning is applied to the CTU first to generate quadtree leaf nodes. The quadtree leaf nodes may have a size from 16×16 (i.e., the MinQTSize) to 128×128 (i.e., the CTU size). If the leaf quadtree node is 128×128, it will not be further split by the binary tree since the size exceeds the MaxBTSize (i.e., 64×64). Otherwise, the leaf quadtree node could be further partitioned by the binary tree. Therefore, the quadtree leaf node is also the root node for the binary tree and it has the binary tree depth as 0.

When the binary tree depth reaches MaxBTDepth (i.e., 4), no further splitting is considered. When the binary tree node has width equal to MinBTSize (i.e., 4), no further horizontal splitting is considered. Similarly, when the binary tree node has height equal to MinBTSize, no further vertical splitting is considered. The leaf nodes of the binary tree are further processed by prediction and transform processing without any further partitioning. In an embodiment, a maximum CTU size is 256×256 luma samples.

In FIGS. 8A and 8B, the solid lines indicate quadtree splitting and dotted lines indicate binary tree splitting. In each splitting (i.e., non-leaf) node of the binary tree, one flag is signaled to indicate which splitting type (i.e., horizontal or vertical) is used. For example, 0 indicates a horizontal splitting and 1 indicates a vertical splitting. For the quadtree splitting, there is no need to indicate the splitting type since quadtree splitting always splits a block both horizontally and vertically to produce 4 sub-blocks with an equal size.

In some embodiments, the QTBT scheme supports the flexibility for the luma and chroma to have a separate QTBT structure. For example, for P and B slices, the luma and chroma blocks in one CTU share the same QTBT structure. However, for I slices, the luma CTB is partitioned into CUs by a QTBT structure, and the chroma blocks are partitioned into chroma CUs by another QTBT structure. Thus, a CU in an I slice consists of a coding block of the luma component or coding blocks of two chroma components, and a CU in a P or B slice consists of coding blocks of all three color components.

In some embodiments, inter prediction for small blocks is restricted to reduce memory access of motion compensation. For example, bi-prediction is not supported for 4×8 and 8×4 blocks, and inter prediction is not supported for 4×4 blocks.

3. Ternary Tree (TT) Block Partitioning Structure

In some embodiments, a multi-type-tree (MTT) structure is used for partitioning a picture. The MTT structure is a more flexible tree structure than the QTBT structure. In MTT, in addition to quad-tree and binary-tree, horizontal center-side triple-tree and vertical center-side triple-tree as shown in FIG. 9A and FIG. 9B, respectively, are employed. Triple tree partitioning can complement quad-tree and binary-tree partitioning. For example, triple-tree partitioning is able to capture objects which locate in a block center, while quad-tree and binary-tree splits crossing block centers. The width and height of partitions by triple trees are a power of 2 so that no additional transform partition is needed.

4. Primary Transform Examples

In some embodiments, 4-point, 8-point, 16-point and 32-point DCT-2 transforms are used as primary transforms. FIGS. 10A-10D show transform core matrices of 4-point, 8-point, 16-point, and 32-point DCT-2, respectively. Elements of those transform core matrices can be represented using 8-bit integers, and thus those transform core matrices are referred to as 8-bit transform cores. As shown, the transform core matrix of a smaller DCT-2 is a part of that of a larger DCT-2.

The DCT-2 core matrices show symmetry/anti-symmetry characteristics. Accordingly, a so-called “partial butterfly” implementation can be supported to reduce the number of operation counts (multiplications, adds/subs, shifts). Identical results of matrix multiplication can be obtained using the partial butterfly implementation.

5. Additional Primary Transform Examples

In some embodiments, in addition to 4-point, 8-point, 16-point and 32-point DCT-2 transforms described above, additional 2-point and 64-point DCT-2 are used. FIGS. 11A-11E shows a 64×64 transform core matrix of the 64-point DCT-2 transform.

In some embodiments, in addition to DCT-2 and 4×4 DST-7 transforms, an adaptive multiple transform (AMT) (also known as enhanced multiple transform (EMT), or multiple transform selection (MTS)) is used for residual coding of both inter and intra coded blocks. The AMT uses multiple selected transforms from discrete cosine transform (DCT)/discrete sine transform (DST) families in addition to DCT-2 transforms, such as transform core matrices of DST-7, or DCT-8 transform. FIG. 12 shows transform basis functions of the selected DST/DCT transforms.

In some embodiments, the DST/DCT transform core matrices used in AMT are represented with 8-bit representation. In some embodiments, AMT is applied to CUs with both width and height smaller than or equal to 32. Whether to apply AMT or not can be controlled by a flag denoted by mts_flag. For example, when the mts_flag is equal to 0, only DCT-2 is applied to coding a residue block. When the mts_flag is equal to 1, an index, denoted by mts_idx, can farther be signaled using 2 bins to specify a horizontal and vertical transforms to be used.

FIG. 13 shows a table (1300) illustrating a mapping relationship between an mts_idx value and respective horizontal or vertical transforms. The row (1301) with the mts_idx having a value of −1 corresponds to the scenario where the mts_flag is equal to 0, and DCT-2 transform is used. The rows (1302)-(1305) with the mts_idx having a value of 0, 1, 2, or 3 correspond to the scenario where the mts_flag is equal to 1. In the right two columns of the table (1300), 0 represents a transform type of DCT-2, 1 represents a transform type of DST-7, and 2 represents a transform type of DCT 8.

FIGS. 14A-14D show transform core matrices of DST-7 transform. FIGS. 15A-15D show transform core matrices of DCT-8 transform.

6. Intra Sub-Partition (ISP) Coding Mode

In some embodiments, an intra sub-partition (ISP) coding mode is employed. In ISP coding mode, a luma intra-predicted block can be partitioned vertically or horizontally into 2 or 4 sub-partitions. The number of sub-partitions can depend on a size of the block. FIG. 16 shows the number of sub-partitions depending on the block size. FIG. 17 shows the scenario where a block is partitioned into two sub-partitions. FIG. 18 shows the scenario where a block is partitioned into four sub-partitions. In an example, all sub-partitions fulfill a condition of having at least 16 samples. In an example, ISP is not applied to chroma components.

In an example, for each of sub-partitions partitioned from a coding block, a residual signal is generated by entropy decoding respective coefficients sent from an encoder and then inverse quantizing and inverse transforming them. Then, a first one of the sub-partitions is intra predicted to generate a prediction signal. The prediction signal is added to the respective residual signal of the first sub-partition to obtain corresponding reconstructed samples. Thereafter, the reconstructed sample values of the first sub-partition can be available to generate a prediction of a second one of the sub-partitions. This process can be repeated sub-partition by sub-partition, until all sub-partitions from the coding block are reconstructed. In an example, all the sub-partitions share a same intra mode.

In an embodiment, the ISP coding mode is only tested with intra modes that are part of a most probable mode (MPM) list. Accordingly, if a block uses ISP, then a MPM flag can be inferred to be one. In addition, when ISP is used for a certain block, then a respective MPM list will be modified to exclude DC mode and to prioritize horizontal intra modes for the ISP horizontal split and vertical intra modes for the vertical one.

In ISP coding mode, each sub-partition can be regarded as a sub-TU, since the transform and reconstruction is performed individually for each sub-partition.

FIGS. 19A-19B shows an example syntax table (1900) that includes related syntax elements signaled for an ISP coding mode. As shown in the frame (1910), a syntax element, intra_subpartitions_mode_flag, indicates whether ISP is used or not. A syntax element, intra_subpartitions_split_flag, indicates a partition direction (vertical or horizontal).

7. Sub-Block Transform (SBT)

In some embodiments, a sub-block transform (SBT), also referred to as spatially varying transform (SVT), is employed. The SBT can be applied to inter prediction residuals. For example, a coding block can be partitioned into sub-blocks, only part of the sub-blocks is treated at a residual block. Zero residual is assumed for the remaining part of the sub-blocks. Therefore, the residual block is smaller than the coding block, and a transform size in SBT is smaller than the coding block size. For the region which is not covered by the residual block, no transform processing is performed.

FIGS. 20A-20D shows sub-block types (SVT-H, SVT-V) (e.g., vertically or horizontally partitioned), sizes and positions (e.g., left half, left quarter, right half, right quarter, top half, top quarter, bottom half, bottom quarter) supported in SBT. The shaded regions labeled by letter “A” is residual blocks with transform, and the other regions is assumed to be zero residual without transform.

As an example, FIGS. 21A-21I show changes to a specification text of a video coding standard (e.g., VVC) being developed by the Joint Video Experts Team (JVET) when SBT is used. The added texts are shown in frames from (2101) to (2113). As shown, additional syntax elements, cu_sbt_flag, cu_sbt_quad_flag, cu_sbt_horizontal_flag, and cu_sbt_pos_flag, are signaled to indicate the sub-block type (horizontal or vertical), size (half or quarter) and position (left or right, top or bottom), respectively.

8. YUV Formats

FIG. 22 shows different YUV formats (e.g., 4:4:4, 4:2:2, 4:1:1, and 4:2:0) used in some embodiments. In an example, a cross component linear model intra prediction is used for the 4:2:0 format. A six-tap interpolation filter can be applied to obtain a down-sampled luma sample corresponding to a chroma sample as shown in FIG. 22. In a formula way, a down-sampled luma sample Rec′L[x, y] can be calculated from nearby reconstructed luma samples (represented by Rec_L[x, y]) in the following way:
Rec′_L [x,y]=(2×Rec_L[2x,2y]+2×Rec_L[2x,2y+1]+Rec_L[2x−1,2y]+Rec_L[2x+1,2y]+Rec_L[2x−1,2y+1]+Rec_L[2x+1,2y+1]+4)>>3

9. Virtual Pipeline Data Unit (VPDU)

Virtual pipeline data units (VPDUs) are defined as non-overlapping units in a picture. In hardware decoders, successive VPDUs are processed by multiple pipeline stages at the same time. A VPDU size is roughly proportional to a buffer size in most pipeline stages. It is desirable to keep the VPDU at a certain size (e.g., 64×64 or smaller). A maximum transform block (TB) size can be specified in a video coding standard to match the VPDU size required by some hardware decoders. However, in some examples, when ternary tree (TT) and binary tree (BT) partition are used without certain restrictions, resulting transform blocks may not be aligned with the intended maximum transform block size (e.g., 64×64), or VPDU size.

In order to keep the VPDU size as 64×64 luma samples, the following normative partition restrictions (with syntax signaling modification) are applied in some embodiments:

- TT split is not allowed for a CU with either width or height, or both width and height equal to 128,
- For a 128×N CU with N≤64 (i.e. width equal to 128 and height smaller than 128), horizontal BT is not allowed.
- For an N×128 CU with N≤64 (i.e. height equal to 128 and width smaller than 128), vertical BT is not allowed.

FIG. 23 shows examples of disallowed TT and BT partitioning.

III. Transform Block Partitioning and Processing Techniques

In some embodiments, a fixed maximum allowable transform unit (TU) size (e.g., 64×64 pixels or samples) is used. For example, by performing a tree-structure based partitioning, a picture or a slice can be partitioned into coding blocks for intra or inter prediction processing. For transform processing, when a coding block is larger than the maximum allowable TU size (e.g., a side length is larger than 64 samples, or both a width and height are larger than 64 samples), the coding block can be further partitioned into sub-blocks such that sizes of the resulting sub-blocks agree with the maximum allowable TU size.

The fixed maximum allowable TU size employed can be specified in a video coding standard, and accordingly can determine a size of a VPDU processed through a multi-stage pipeline at a hardware encoder or decoder. Transform block partitioning according to the maximum allowable TU size results in transform blocks having a size matching the VPDU size required by the pipelined encoder or decoder.

In contrast, in some embodiments, controllable or configurable maximum allowable TU sizes are employed. For example, in addition to the size of 64×64 samples, a maximum TU size can be of other sizes, such as 32×32 samples, 16×16 samples, or the like. A maximum TU size can be determined at an encoder side and signaled to a decoder side. Such flexibility of the maximum allowable TU size can have an impact on hardware complexity for encoder implementation (e.g., pipeline intermediate buffer size, number of multipliers, and the like), and potentially improve performance of a hardware encoder, and thus is desirable.

When controllable maximum allowable TU sizes are employed, it is possible that a maximum TU size (e.g., 16×16 samples) is smaller than a VPDU size (e.g., 64×64 samples). Under such a scenario, in some embodiments, specific transform block partitioning techniques are employed to partition a coding block into transform blocks. Those transform blocks have a maximum allowable TU size. At the same time, partitioning of those transform blocks is compatible with the VPDU size. Or, in other words, the resulting transform blocks are compatible with the requirement of the VPDU size based pipeline processing.

In addition, in some embodiments, those transform blocks are processed according to a certain order such that the processed blocks can be combined into VPDUs suitable for pipelined processing. For example, processing of those transform blocks at a decoder, for example, may include entropy decoding, inverse quantization, inverse transforming, or the like. The pipelined processing, for example, may include block reconstructing, deblocking, sample adaptive offset (SAO) processing, adaptive loop filter (ALF) processing, or the like.

1. Example A

In an example, a maximum allowable TU size is set to be M samples (e.g., a size of M×M samples). A VPDU size is set to be K samples (e.g., a size of K×K samples). A coding block (or CU) has a width of W samples and a height of H samples. The coding block can be partitioned in the following way based on the VPDU size K and the maximum allowable TU size M. First, the coding block with a size of W×H samples can be partitioned into multiple sub-blocks, referred to as sub processing units (SPUs), each having a size of Min(W, K)×Min(H, K) samples. Then, each SPU is further partitioned into transform blocks (or TUs) having a size of M×M samples. Those transform blocks can be referred to as sub-TUs.

In addition, in an example, the SPUs are each treated as a VPDU, and those VPDUs can be passed through a multi-stage pipeline. The SPUs can be processed according to a first order. Based on the first order for processing the SPU, an order of processing the sub-TUs can be determined. For example, a first and second SPUs are processed successively through the multi-stage pipeline. Accordingly, the sub-TUs in the first SPU are first processed (e.g., entropy decoding, inverse quantization, and inverse transforming), and input to the multi-stage pipeline. The sub-TUs in a second SPU are subsequently processed, and input to the multi-stage pipeline. By processing the sub-PUs in this order, the requirement of the VPDU based pipelined processing can be satisfied.

Further, within each SPU, the sub-TUs can be processed according to a second order.

In various embodiments, the first order for processing the SPUs and the second order for processing the sub-TUs within an SPU can be one of a raster scan order, a vertical scan order (e.g., scans SPUs or sub-TUs column-wise from left to right or vice versa), a zig-zag order, a diagonal scan order, or the like.

The first order and the second order can be the same or different in different embodiments. For example, the first order for processing the SPUs and the second order for processing the sub-TUs within an SPU are both the raster scan order in an embodiment.

2. Example B

FIG. 24 shows a coding block (or CU) (2410) having a size of W×H samples where W=128, and H=64. A maximum allowable TU size of M=32 samples is signaled from an encoder to a decoder. A VPDU size is specified as K=64 samples. To align transform blocks with VPDUs, the coding block (2410) is first split into a left 64×64 SPU (2420) and a right 64×64 SPU (2430). The left SPU (2420) and the right SPU (2430) can then be further partitioned into sub-TUs (labeled from 0 to 7) each having a size of 32×32 samples. The sub-TUs labeled by 0, 1, 2 and 3 are included in the first SPU (2420), and the sub-TUs labeled by 4, 5, 6 and 7 are included in the second SPU (2430).

According to a configured or default order, the left SPU (2420) can first be processed followed by the right SPU (2430). Within each SPU (2420) or (2430), a raster scan order can be specified (or a default) for processing the resulting sub-TUs (labeled from 0 to 7). Accordingly, the sub-TUs labeled from 0 to 7 are processed according to an order indicated by the arrows (2451).

3. Example C

FIG. 25 shows a coding block (2510) having a size of W×H samples where W=128, and 11=32. A maximum allowable TU size of M=16 samples is signaled from an encode to a decoder. A VPDU size is specified as K=64 samples. A lesser of W and K is 64, while a lesser of H and K is 32. Thus, to align transform blocks with VPDUs, a size of a SPU can be determined to be 64×32 samples. The coding block (2510) can be partitioned into a left SPU (2520) and a right SPU (2530) each having a size of 64×32 samples. The two SPUs (2520) and (2520) can be processed in an order from left to right.

Each of the two SPUs (2520) and (2520) can be further split into sub-TUs (labeled from 0 to 15) each having the maximum allowable TU size, 16×16 samples. As shown, the left SPU (2520) is partitioned into the sub-TUs labeled from 0 to 7, while the right SPU (2530) is partitioned into the sub-TUs labeled from 8 to 15. Within each SPU (2520) and (2530), the sub-TUs can be processed in a raster scan order. Accordingly, the sub-TUs labeled from 0 to 15 can be performed in an order indicated by the arrows (2551).

4. Example D

FIG. 26 shows a coding block (2610) having a size of W×H samples where W=128, and H=32. A maximum allowable TU size of M=16 samples is signaled from an encode to a decoder. A VPDU size is specified as K=64 samples. In a similar way as in the FIG. 25 example, the coding block (2610) can be partitioned into two SPUs (2620) and (2630) that can each be further partitioned into sub-TUs labeled from 0 to 15. The SPUs (2620) and (2630) can be processed from left to right in the same order as in FIG. 25. However, different from the FIG. 25 example, the sub-TUs within each SPU (2620) and (2630) are processed in a zig-zag scan order.

5. Example E

FIG. 27 shows a flow chart outlining a transform block partitioning and processing process (2700) according to an embodiment of the disclosure. The process (2700) can be used in the reconstruction of a block coded in intra mode or inter mode. In various embodiments, the process (2700) are executed by processing circuitry, such as the processing circuitry in the terminal devices (210), (220), (230) and (240), the processing circuitry that performs functions of the video decoder (310), the processing circuitry that performs functions of the video decoder (410), and the like. In some embodiments, the process (2700) is implemented in software instructions, thus when the processing circuitry executes the software instructions, the processing circuitry performs the process (2700). The process starts at (S2701) and proceeds to (S2710).

At (S2710), a syntax element indicating a maximum allowable TU size of M can be received from a bitstream. For example, controllable maximum allowable TU sizes are used. The maximum allowable TU size can be determined at an encoder and signaled to a decoder.

At S(2720), a coding block having a width of W pixels and a height of H pixels can be received at the decoder. For example, a syntax element indicating the coding block with the width and height can be received from a bitstream at the decoder.

At (S2730), the coding block is partitioned into SPUs. For example, a VPDU size of K×K samples (or pixels) can be preconfigured to the decoder. Based on the VPDU size and the size of the coding block, a size of the SPUs can be determined. For example, a width of the SPU can be a lesser of W or K pixels and a height of the SPU can be a lesser of H or K pixels. Accordingly, the coding block can be partitioned into SPUs each having the determined width and height.

At (S2740), each SPU is partitioned into sub-TUs with each sub-TU having the maximum allowable TU size of M.

At (S2750), the sub-TUs of the SPUs are processed according to an SPU processing order. For example, the SPU processing order can be predefined for processing the SPUs, for example, through a multi-stage pipeline. Within each SPU, the sub-TUs can be processed according to a predefined order. Alternatively, the orders for processing the SPUs or sub-TUs may be controllable, and signaled from a decoder.

For example, according to the SPU processing order and the sub-TU processing order within each SPU, residual signals of each sub-TU can be obtained by a sequence of decoding operations (e.g., entropy decoding of transform coefficients, inverse quantization, inverse transforming, and the like). In an example, the residual signals can be combined and input to the multi-stage pipeline in a SPU by SPU basis. The process can proceed to (S2799) and terminate at (S2799).

IV. Computer System

The techniques described above, can be implemented as computer software using computer-readable instructions and physically stored in one or more computer-readable media. For example, FIG. 28 shows a computer system (2800) suitable for implementing certain embodiments of the disclosed subject matter.

The computer software can be coded using any suitable machine code or computer language, that may be subject to assembly, compilation, linking, or like mechanisms to create code comprising instructions that can be executed directly, or through interpretation, micro-code execution, and the like, by one or more computer central processing units (CPUs), Graphics Processing Units (GPUs), and the like.

The instructions can be executed on various types of computers or components thereof, including, for example, personal computers, tablet computers, servers, smartphones, gaming devices, internet of things devices, and the like.

The components shown in FIG. 28 for computer system (2800) are exemplary in nature and are not intended to suggest any limitation as to the scope of use or functionality of the computer software implementing embodiments of the present disclosure. Neither should the configuration of components be interpreted as having any dependency or requirement relating to any one or combination of components illustrated in the exemplary embodiment of a computer system (2800).

Computer system (2800) may include certain human interface input devices. Such a human interface input device may be responsive to input by one or more human users through, for example, tactile input (such as: keystrokes, swipes, data glove movements), audio input (such as: voice, clapping), visual input (such as: gestures), olfactory input (not depicted). The human interface devices can also be used to capture certain media not necessarily directly related to conscious input by a human, such as audio (such as: speech, music, ambient sound), images (such as: scanned images, photographic images obtain from a still image camera), video (such as two-dimensional video, three-dimensional video including stereoscopic video).

Input human interface devices may include one or more of (only one of each depicted): keyboard (2801), mouse (2802), trackpad (2803), touch screen (2810), data-glove (not shown), joystick (2805), microphone (2806), scanner (2807), camera (2808).

Computer system (2800) may also include certain human interface output devices. Such human interface output devices may be stimulating the senses of one or more human users through, for example, tactile output, sound, light, and smell/taste. Such human interface output devices may include tactile output devices (for example tactile feedback by the touch-screen (2810), data-glove (not shown), or joystick (2805), but there can also be tactile feedback devices that do not serve as input devices), audio output devices (such as: speakers (2809), headphones (not depicted)), visual output devices (such as screens (2810) to include CRT screens, LCD screens, plasma screens, OLED screens, each with or without touch-screen input capability, each with or without tactile feedback capability—some of which may be capable to output two dimensional visual output or more than three dimensional output through means such as stereographic output; virtual-reality glasses (not depicted), holographic displays and smoke tanks (not depicted)), and printers (not depicted).

Computer system (2800) can also include human accessible storage devices and their associated media such as optical media including CD/DVD ROM/RW (2820) with CD/DVD or the like media (2821), thumb-drive (2822), removable hard drive or solid state drive (2823), legacy magnetic media such as tape and floppy disc (not depicted), specialized ROM/ASIC/PLD based devices such as security dongles (not depicted), and the like.

Those skilled in the art should also understand that term “computer readable media” as used in connection with the presently disclosed subject matter does not encompass transmission media, carrier waves, or other transitory signals.

Computer system (2800) can also include an interface to one or more communication networks. Networks can for example be wireless, wireline, optical. Networks can further be local, wide-area, metropolitan, vehicular and industrial, real-time, delay-tolerant, and so on. Examples of networks include local area networks such as Ethernet, wireless LANs, cellular networks to include GSM, 3G, 4G, 5G, LTE and the like, TV wireline or wireless wide area digital networks to include cable TV, satellite TV, and terrestrial broadcast TV, vehicular and industrial to include CANBus, and so forth. Certain networks commonly require external network interface adapters that attached to certain general purpose data ports or peripheral buses (2849) (such as, for example USB ports of the computer system (2800)); others are commonly integrated into the core of the computer system (2800) by attachment to a system bus as described below (for example Ethernet interface into a PC computer system or cellular network interface into a smartphone computer system). Using any of these networks, computer system (2800) can communicate with other entities. Such communication can be uni-directional, receive only (for example, broadcast TV), uni-directional send-only (for example CANbus to certain CANbus devices), or bi-directional, for example to other computer systems using local or wide area digital networks. Certain protocols and protocol stacks can be used on each of those networks and network interfaces as described above.

Aforementioned human interface devices, human-accessible storage devices, and network interfaces can be attached to a core (2840) of the computer system (2800).

The core (2840) can include one or more Central Processing Units (CPU) (2841), Graphics Processing Units (GPU) (2842), specialized programmable processing units in the form of Field Programmable Gate Areas (FPGA) (2843), hardware accelerators for certain tasks (2844), and so forth. These devices, along with Read-only memory (ROM) (2845), Random-access memory (2846), internal mass storage such as internal non-user accessible hard drives, SSDs, and the like (2847), may be connected through a system bus (2848). In some computer systems, the system bus (2848) can be accessible in the form of one or more physical plugs to enable extensions by additional CPUs, GPU, and the like. The peripheral devices can be attached either directly to the core's system bus (2848), or through a peripheral bus (2849). Architectures for a peripheral bus include PCI, USB, and the like.

CPUs (2841), GPUs (2842), FPGAs (2843), and accelerators (2844) can execute certain instructions that, in combination, can make up the aforementioned computer code. That computer code can be stored in ROM (2845) or RAM (2846). Transitional data can be also be stored in RAM (2846), whereas permanent data can be stored for example, in the internal mass storage (2847). Fast storage and retrieve to any of the memory devices can be enabled through the use of cache memory, that can be closely associated with one or more CPU (2841), GPU (2842), mass storage (2847), ROM (2845), RAM (2846), and the like.

The computer readable media can have computer code thereon for performing various computer-implemented operations. The media and computer code can be those specially designed and constructed for the purposes of the present disclosure, or they can be of the kind well known and available to those having skill in the computer software arts.

As an example and not by way of limitation, the computer system having architecture (2800), and specifically the core (2840) can provide functionality as a result of processor(s) (including CPUs, GPUs, FPGA, accelerators, and the like) executing software embodied in one or more tangible, computer-readable media. Such computer-readable media can be media associated with user-accessible mass storage as introduced above, as well as certain storage of the core (2840) that are of non-transitory nature, such as core-internal mass storage (2847) or ROM (2845). The software implementing various embodiments of the present disclosure can be stored in such devices and executed by core (2840). A computer-readable medium can include one or more memory devices or chips, according to particular needs. The software can cause the core (2840) and specifically the processors therein (including CPU, GPU, FPGA, and the like) to execute particular processes or particular parts of particular processes described herein, including defining data structures stored in RAM (2846) and modifying such data structures according to the processes defined by the software. In addition or as an alternative, the computer system can provide functionality as a result of logic hardwired or otherwise embodied in a circuit (for example: accelerator (2844)), which can operate in place of or together with software to execute particular processes or particular parts of particular processes described herein. Reference to software can encompass logic, and vice versa, where appropriate. Reference to a computer-readable media can encompass a circuit (such as an integrated circuit (IC)) storing software for execution, a circuit embodying logic for execution, or both, where appropriate. The present disclosure encompasses any suitable combination of hardware and software.

APPENDIX A: ACRONYMS

ASIC: Application-Specific Integrated Circuit
BMS: benchmark set
CANBus: Controller Area Network Bus
CBF: Coded Block Flag
CD: Compact Disc
CPUs: Central Processing Units
CRT: Cathode Ray Tube
CTBs: Coding Tree Blocks
CTUs: Coding Tree Units
CU: Coding Unit
DVD: Digital Video Disc
FPGA: Field Programmable Gate Areas
GOPs: Groups of Pictures
GPUs: Graphics Processing Units
GSM: Global System for Mobile communications
HEVC: High Efficiency Video Coding
HRD: Hypothetical Reference Decoder
ISP: Intra Sub-Partitions
IC: Integrated Circuit
JEM: joint exploration model
LAN: Local Area Network
LCD: Liquid-Crystal Display
LTE: Long-Term Evolution
MPM: Most Probable Mode
MV: Motion Vector
OLED: Organic Light-Emitting Diode
PBs: Prediction Blocks
PCI: Peripheral Component Interconnect
PLD: Programmable Logic Device
PUs: Prediction Units
RAM: Random Access Memory
ROM: Read-Only Memory
SBT: Sub-block Transform
SEI: Supplementary Enhancement Information
SNR: Signal Noise Ratio
SSD: solid-state drive
TUs: Transform Units,
USB: Universal Serial Bus
VPDU: Virtual Pipeline Data Unit
VUI: Video Usability Information
VVC: versatile video coding

While this disclosure has described several exemplary embodiments, there are alterations, permutations, and various substitute equivalents, which fall within the scope of the disclosure. It will thus be appreciated that those skilled in the art will be able to devise numerous systems and methods which, although not explicitly shown or described herein, embody the principles of the disclosure and are thus within the spirit and scope thereof.

Claims

What is claimed is:

1. A method of video decoding at a video decoder, comprising:

receiving a coding block having a width of W pixels and a height of H pixels;

partitioning the coding block into sub processing units (SPUs) each having a width of a lesser of W or K pixels and a height of a lesser of H or K pixels, where K is a dimension of a virtual pipeline data unit (VPDU) having an area of K×K pixels; and

partitioning each SPU into transform units, with each transform unit having a maximum allowable transform unit size of M pixels.

2. The method of claim 1, further comprising:

receiving a syntax element in a bitstream indicating the maximum allowable transform unit size of M pixels.

3. The method of claim 1, further comprising:

processing the transform units of the SPUs according to an SPU processing order.

4. The method of claim 3, wherein the SPU processing order for processing the SPUs is one of a raster scan order, a vertical scan order, a zig-zag order, or a diagonal scan order.

5. The method of claim 3, wherein an order for processing the transform units within each SPU is one of a raster scan order, a vertical scan order, a zig-zag order, or a diagonal scan order.

6. The method of claim 3, wherein the SPU processing order and an order for processing the transform units within each SPU are both a raster scan order.

7. The method of claim 1, wherein K is 64 and M is 32.

8. An apparatus of video decoding, comprising circuitry configured to:

receive a coding block having a width of W pixels and a height of H pixels;

partition the coding block into sub processing units (SPUs) each having a width of a lesser of W or K pixels and a height of a lesser of H or K pixels, where K is a dimension of a virtual pipeline data unit (VPDU) having an area of K×K pixels; and

partition each SPU into transform units, with each transform unit having a maximum allowable transform unit size of M pixels.

9. The apparatus of claim 8, wherein the circuitry is further configured to:

receive a syntax element in a bitstream indicating the maximum allowable transform unit size of M pixels.

10. The apparatus of claim 8, wherein the circuitry is further configured to:

process the transform units of the SPUs according to an SPU processing order.

11. The apparatus of claim 10, wherein the SPU processing order for processing the SPUs is one of a raster scan order, a vertical scan order, a zig-zag order, or a diagonal scan order.

12. The apparatus of claim 10, wherein an order for processing the transform units within each SPU is one of a raster scan order, a vertical scan order, a zig-zag order, or a diagonal scan order.

13. The apparatus of claim 10, wherein the SPU processing order and an order for processing the transform units within each SPU are both a raster scan order.

14. The apparatus of claim 8, wherein K is 64 and M is 32.

15. A non-transitory computer-readable medium storing instructions that, when executed by a computer for video decoding, cause the computer to perform a method of video decoding, the method comprising:

receiving a coding block having a width of W pixels and a height of H pixels;

16. The non-transitory computer-readable medium of claim 15, wherein the method further comprising:

17. The non-transitory computer-readable medium of claim 15, wherein the method further comprising:

18. The non-transitory computer-readable medium of claim 17, wherein the SPU processing order for processing the SPUs is one of a raster scan order, a vertical scan order, a zig-zag order, or a diagonal scan order.

19. The non-transitory computer-readable medium of claim 17, wherein an order for processing the transform units within each SPU is one of a raster scan order, a vertical scan order, a zig-zag order, or a diagonal scan order.

20. The non-transitory computer-readable medium of claim 17, wherein the SPU processing order and an order for processing the transform units within each SPU are both a raster scan order.