US10964525B2 - Removing a sacrificial material via sublimation in forming a semiconductor - Google Patents
Removing a sacrificial material via sublimation in forming a semiconductor Download PDFInfo
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- US10964525B2 US10964525B2 US15/847,601 US201715847601A US10964525B2 US 10964525 B2 US10964525 B2 US 10964525B2 US 201715847601 A US201715847601 A US 201715847601A US 10964525 B2 US10964525 B2 US 10964525B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00841—Cleaning during or after manufacture
- B81C1/00849—Cleaning during or after manufacture during manufacture
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B08—CLEANING
- B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
- B08B3/00—Cleaning by methods involving the use or presence of liquid or steam
- B08B3/04—Cleaning involving contact with liquid
- B08B3/08—Cleaning involving contact with liquid the liquid having chemical or dissolving effect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
- H01L21/67034—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for drying
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- H10P70/20—
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- H10P72/0408—
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B08—CLEANING
- B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
- B08B1/00—Cleaning by methods involving the use of tools
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0102—Surface micromachining
- B81C2201/0105—Sacrificial layer
- B81C2201/0109—Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
Definitions
- the present disclosure relates generally to semiconductor processing, and, more particularly, to using sublimation in forming a semiconductor.
- Semiconductor processing e.g., fabrication
- semiconductor devices such as integrated circuits, memory devices, microelectromechanical devices (MEMS), etc.
- MEMS microelectromechanical devices
- Examples of memory devices that can be formed by semiconductor processing include, but are not limited to, volatile memory (e.g., that can require power to maintain its data), such as random-access memory (RAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), among others, and non-volatile memory (e.g., that can provide persistent data by retaining stored data when not powered), such as NAND flash memory, NOR flash memory, read only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM, among others.
- volatile memory e.g., that can require power to maintain its data
- RAM random-access memory
- DRAM dynamic random access memory
- SDRAM synchronous dynamic random access memory
- non-volatile memory e.g., that can provide persistent data by retaining stored data when not powered
- NAND flash memory NOR flash memory
- ROM read only memory
- EEPROM electrically erasable programmable ROM
- EPROM erasable
- Semiconductor processing can involve forming features (e.g., patterns) on and/or in a semiconductor (e.g., of silicon) that may be referred to as a wafer or substrate.
- a semiconductor e.g., of silicon
- one or more materials such as silicon-based materials (e.g., silicon oxide (SiO), silicon nitride (SiN), tetraethyl orthosilicate (TEOS), and/or polysilicon) may be formed on the semiconductor.
- a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electrochemical deposition and/or molecular beam epitaxy, among others may be used to form one or more materials on the semiconductor.
- PVD physical vapor deposition
- CVD chemical vapor deposition
- ALD atomic layer deposition
- electrochemical deposition and/or molecular beam epitaxy among others may be used to form one or more materials on the semiconductor.
- portions of the one or more materials, and in some instances, portions of the semiconductor may be removed, such as by wet and/or dry etching, to form the features.
- the features may have high aspect ratios (e.g., ratio of height to width or diameter) and may be referred to as high-aspect-ratio (HAR) features.
- HAR high-aspect-ratio
- the features might be separated from each other by HAR openings.
- the semiconductor and the features may be subjected to wet processing, such as wet cleaning, and subsequent drying.
- wet cleaning can be helpful to remove residue left behind, such as by the removal process or other processing.
- FIG. 1 presents various examples of feature toppling.
- FIGS. 2A-2D illustrate cross-sectional views of processing steps associated with forming a semiconductor device, in accordance with a number of embodiments of the present disclosure.
- FIG. 3 an example of a processing step associated with forming a semiconductor device, in accordance with a number of embodiments of the present disclosure.
- FIG. 4 is a block diagram illustration of a processing apparatus used in conjunction with the processing steps associated with forming a semiconductor device, in accordance with a number of embodiments of the present disclosure.
- FIG. 5 is a block diagram illustration of an apparatus formed, at least in part, in accordance with a number of embodiments of the present disclosure.
- the present disclosure includes processing methods associated with forming semiconductor devices, such as integrated circuits, memory devices MEMS, among others.
- An example of forming semiconductor devices can include forming a sacrificial material in an opening of a structure, wherein the sacrificial material displaces a solvent used in a wet clean operation and removing the sacrificial material via sublimation by exposing the sacrificial material to sub-atmospheric pressure.
- Embodiments of the present disclosure provide technical advantages, such as reducing the likelihood of feature collapse (e.g. toppling) during processing compared to previous approaches.
- a number of embodiments form a sacrificial material in openings between features in a structure, such as a structure to be used in a semiconductor device (e.g., a memory device), that acts to prevent feature collapse (e.g., sometimes referred to as pattern collapse) while the structure is drying at the end of a wet clean process or while the structure is being moved from one processing tool to another processing tool during processing (e.g., formation of the semiconductor device).
- a sacrificial material in openings between features in a structure, such as a structure to be used in a semiconductor device (e.g., a memory device), that acts to prevent feature collapse (e.g., sometimes referred to as pattern collapse) while the structure is drying at the end of a wet clean process or while the structure is being moved from one processing tool to another processing tool during processing (e.g.
- Some prior approaches can include forming features in a structure at a dry etch tool, such as by dry etching, and moving the structure to a wet cleaning tool (e.g., to clean residue from the dry etch from the structure). After cleaning, solvent from the wet cleaning tool may remain on the structure.
- liquid solvent can remain on surfaces of a structure after a wet clean operation.
- Remaining liquid solvent can be a problem for structures having high aspect ratio structures, such as shallow trench isolation (STI) structures.
- the liquid solvent may form in the openings between the features.
- High surface tension forces may result from the liquid in the openings that can cause the features to topple (e.g., collapse) toward each other, bringing adjacent features into contact with each other.
- FIG. 1 illustrates a feature 101 toppling (e.g., collapsing) into an adjacent feature and a pair of adjacent features 102 toppling into each other (e.g. in what is sometimes referred to as bridging). This can lead to defects in the semiconductor device structure, and can even render the semiconductor device inoperable.
- the sacrificial materials of the embodiments described herein obstruct the openings to prevent liquid solvent from remaining on the high aspect ratio structures and in the openings after a wet clean operation, and thus can reduce the likelihood of (e.g., eliminate) high aspect ratio features collapsing due to capillary forces created by the liquid solvent.
- the sacrificial material can completely or partially fill the openings to prevent liquid solvent from remaining in the openings after a wet clean operation.
- semiconductor can refer to, for example, a bulk material, a semiconductive wafer, or a substrate, and includes any base semiconductor structure.
- semiconductor or “Semiconductive” is to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film-transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures.
- SOS silicon-on-sapphire
- SOI silicon-on-insulator
- TFT thin-film-transistor
- doped and undoped semiconductors epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures.
- semiconductor can include the underlying layers containing such regions/junctions.
- the apparatus can be formed by semiconductor processing, but are not limited to semiconductor or semiconductive structures.
- the apparatus can be formed using quartz substrate and/or other materials.
- FIGS. 2A-2D illustrate cross-sectional views of processing steps associated with forming a semiconductor device, such as a portion of an integrated circuit, a memory device, a MEMS, among others, in accordance with a number of embodiments of the present disclosure.
- the processing steps may be associated with forming (e.g., a memory array of) a DRAM memory device, a NAND flash memory device, a NOR flash memory device, among others.
- FIG. 2A depicts a structure (e.g., to be used in a semiconductor device) after several processing steps have occurred.
- the structure may include a base structure, such as a substrate 206 (e.g., a semiconductor).
- a substrate 206 e.g., a semiconductor
- one or more materials 210 such as silicon-based or non-silicon based materials, may be formed on (e.g., over) a surface 208 , such as an upper surface, of semiconductor 206 , using, for example, a deposition process, such as PVD, CVD, ALD, electrochemical deposition and/or molecular beam epitaxy, among others.
- a deposition process such as PVD, CVD, ALD, electrochemical deposition and/or molecular beam epitaxy, among others.
- Features 211 such as microfeatures (e.g., having a width or diameter of about 0.1 micrometer to about 100 micrometer) and/or nanofeatures (e.g., having a width or diameter of about 0.1 nanometer to about 100 nanometer) are formed by removing portions of the structure, such as portions of the one or more materials 210 and portions of semiconductor 206 .
- the removal process forms openings 212 , such as spaces (e.g., trenches), through the one or more materials 210 , stopping on or in (e.g., as shown in FIG. 2A ) semiconductor 206 .
- an opening 212 may be between adjacent features 211 .
- each of the respective features 211 includes the one or more materials 210 and a portion of semiconductor 206 .
- the removal process can stop above or on the surface of substrate 206 .
- portions of the openings 212 in semiconductor 206 may correspond to isolation regions, such as shallow trench isolation (STI) regions and/or high aspect ratio features such as those used while forming capacitors, transistors, and other electrical components.
- a feature 211 may be entirely of semiconductor 206 , and openings 212 may correspond to STI regions.
- Features 211 may be HAR features, and openings 212 may be HAR openings.
- an HAR may have a height to width or diameter ratio of 10 to 1.25 to 1, or greater.
- openings 212 may be formed using a dry processing tool (not shown), such as the dry removal tool (e.g., dry etch tool), using a dry removal process, such as a dry etch.
- a mask such as imaging resist (e.g., photo-resist), may be formed over the one or more materials 210 and patterned to expose regions of the one or more materials 210 . The exposed regions may be subsequently removed, such as by the dry etch process, to form openings 212 that may terminate on or in semiconductor 206 .
- material such as a dielectric material (e.g., silicon oxide, silicon nitride, etc.), an organic compound (e.g., an organic polymer), an ionic compound (e.g., an ammonium salt or a halide salt), a soluble material (e.g., soluble in a solvent, such as water, hydrofluoric acid (HF), etc.), among others, can be formed on the structure of FIG. 2A to obstruct openings 212 .
- a dielectric material e.g., silicon oxide, silicon nitride, etc.
- an organic compound e.g., an organic polymer
- an ionic compound e.g., an ammonium salt or a halide salt
- a soluble material e.g., soluble in a solvent, such as water, hydrofluoric acid (HF), etc.
- the material may be formed on the structure of FIG. 2A at a dry removal tool before the structure is exposed to a moisture-containing atmosphere, such as air, for example.
- a wet cleaning tool may be dedicated to the removal of the particles and/or residues that may form as a result of the dry etch and/or to remove other material deposited (e.g., sacrificial material and/or mask material) on the wafer.
- the composition of the material used to fill openings may be selected so it can be removed by the wet clean chemistry to be used for wet cleaning.
- Material from the dry-etch process can be removed from the structure via the wet cleaning tool (e.g., as part of the wet cleaning process) to re-expose (e.g., reopen) the openings 212 between features 211 .
- the wet cleaning process may be performed in an inert atmosphere so that the structure of FIG. 2A is not exposed to a reactive gas (e.g., O 2 ).
- the wet cleaning may include an aqueous wet clean that may include hydrofluoric acid (HF).
- an aqueous wet clean may include a standard clean-1 (SC-1) (e.g. for removing organics, particles, and films) that may include deionized (DI) water, aqueous ammonium hydroxide, and aqueous hydrogen peroxide.
- SC-1 standard clean-1
- SC-2 e.g., for removing metal ions
- SC-2 e.g., for removing metal ions
- the wet-cleaning process may further include the aqueous wet clean with a DI water rinse, followed by a solvent (e.g., isopropyl alcohol (IPA)) rinse, followed by drying, such as spin drying.
- IPA isopropyl alcohol
- wet cleaning process and the removal of material may be integrated, and the wet cleaning process may remove residue from the dry etch.
- a sacrificial material 220 such as a volatile solid material, is formed on (e.g., is used to coat) the structure of FIG. 2A at the wet cleaning tool, to obstruct openings 212 (e.g., without exposing the structure to a gas).
- sacrificial material 220 may be spin coated onto the structure of FIG. 2A .
- sacrificial material 220 obstructs openings 212 by completely filling openings 212 .
- sacrificial material 220 can completely fill openings 212 such that an upper surface of sacrificial material 220 may be coplanar (e.g., flush) with the upper surfaces 216 of features 211 . Additionally, as shown in FIG. 2B , sacrificial material 220 can overfill openings 212 and extend over (e.g., cover) upper surfaces 216 of features 211 . In some examples, sacrificial material 220 may partially fill openings 212 such that the upper surface of sacrificial material 220 may be below the level of upper surface 216 . In some examples, sacrificial material 220 may completely displace any liquid from the wet cleaning process.
- Non-limiting examples of suitable volatile solid materials include camphor, ammonium acetate, ammonium formate, ammonium carbamate, ammonium carbonate, ammonium bicarbonate, ammonium fluoride, ammonium biflouride, ammonium chloride, metaldehyde, hexamethylenetetramine, cyanuric acid, benzotriazole, p-benzoquinone, camphene, naphthalene, phenol, oxalic acid, succinonitrile, trioxane, and/or acetamide, among others.
- the volatile material may be formed in the openings 212 in FIG. 2A in-situ through the use of a reactive gas and a solution.
- the gas can be carbon dioxide (CO 2 ) and the solution can be ammonia (NH 3 ) that can react to form solid ammonium carbamate.
- the gas can be ammonia (NH 3 ) and the solution can be carbon dioxide (CO 2 ).
- the gas can be ammonia and the solution can be formic acid to form ammonium formate as the sacrificial material.
- the sacrificial material can be ammonium acetate formed using acetic acid as the solution and ammonia as the reactive gas.
- Liquid formic and/or acetic acids on their own and/or with a solvent could also be used to form ammonium salts with ammonia vapor to be used as the sacrificial material, for example.
- the sacrificial material may displace any liquid from the wet cleaning operation.
- the structure of FIG. 2B can be moved from the wet cleaning tool to a different processing tool, such as the deposition tool.
- the structure of FIG. 2B may be exposed to a moisture-containing atmosphere as it is moved from the wet cleaning tool to the deposition tool.
- sacrificial material 220 prevents condensation on the features 211 and in openings 212 , and thus the toppling of features 211 resulting from the condensation and/or physical forces. Sacrificial material 220 may also protect features 211 from oxidation that can occur as the structure is being moved through an oxygen containing atmosphere.
- sacrificial material 220 may be removed at the wet cleaning tool and/or deposition tool to re-expose openings 212 between features 211 .
- sacrificial material 220 may be removed by sublimation.
- the pressure, temperature, and/or gas in a chamber, such as chamber 440 as shown in FIG. 4 may be set such that sacrificial material 220 sublimates.
- the pressure may be controlled by a pump 444 as shown in FIG. 4
- temperature may be controlled by a temperature control 443
- gas inside chamber may be controlled by a gas purge 446 as shown in FIG. 4 .
- the volatile sacrificial material 220 may be removed by removing the structure from the chamber.
- openings 212 in the structure of FIG. 2A may be obstructed without completely filling openings 212 with a sacrificial material, such as sacrificial material 220 in FIG. 2B .
- a sacrificial material 330 may be formed on a structure, such as the structure of FIG. 2A , to form the structure in FIG. 3 .
- Sacrificial material 330 is formed in openings 312 and between features 311 so that sacrificial material 330 obstructs the openings 312 adjacent to a top of the openings 312 without completely filling the openings 312 .
- Sacrificial material 330 pinches off adjacent to the top of the openings before the openings are completely filled, leaving voids 332 between features 311 .
- sacrificial material 330 lines openings 312 and obstructs openings 312 adjacent to the tops of openings 312 to create voids 332 .
- the sacrificial material 330 is coupled between adjacent features 311 by spanning upper portions of the openings between the adjacent features 311 .
- sacrificial material 330 may be sacrificial material 220 .
- the structure of FIG. 3 may be formed at the wet cleaning tool, which can include chamber 440 of FIG. 4 .
- the structure of FIG. 3 may be formed in-situ by combining a reactive gas and a solution.
- a solution for example, liquid formic acid or acetic acid can react with an ammonia vapor to form solid ammonium salt that can be removed via sublimation.
- sacrificial material 330 may be deposited to partially fill openings 312 such that sacrificial material 330 is formed on features 311 within openings 312 , as shown in FIG. 3 , thus lining openings 312 , but without pinching off.
- FIG. 4 is a block diagram illustration of a processing apparatus used in conjunction with the processing steps associated with forming a semiconductor device, in accordance with a number of embodiments of the present disclosure.
- the processing apparatus can include a chamber 440 to form sacrificial material in a solid state in openings of structures, a carrier 442 can hold a batch of semiconductor wafers 443 , and tools, for example a pump 444 , a gas purge 446 , and a temperature control 448 , can remove sacrificial material via sublimation.
- a sacrificial material can be formed in an opening of a structure in the chamber 440 .
- the sacrificial material in a solid state can obstruct the opening 212 in FIG. 2A , in the structure.
- the structure can be included on one of the semiconductor wafers 443 .
- the sacrificial material in a solid state can prevent pattern collapse caused by capillary forces after wet clean operations.
- the sacrificial material can be formed in the opening of the structure in response to performing a wet clean operation.
- the wet clean operation can be performed in chamber 440 and/or the same tool as the chamber 440 is in.
- the wet clean operation can include using a solvent to wet clean the structure prior to forming the sacrificial material.
- the solvent can evaporate prior to removing the sacrificial material.
- the solvent can evaporate in a carbon dioxide (CO 2 ) atmosphere, for example.
- the sacrificial material can displace a solvent of the wet clean operation.
- the sacrificial material can be spin coated into the opening 212 in FIG. 2A or 2C , in the structure.
- the sacrificial material can be formed in the opening of the structure using a reactive gas and a solution.
- the reactive gas can be carbon dioxide (CO 2 ) and the solution can be ammonia (NH 3 ), for example.
- the carbon dioxide and the ammonia can react to form solid ammonium carbamate.
- the solid ammonium carbamate can be the sacrificial material that can be formed in the opening of the structure to prevent pattern collapse after a wet clean process and/or while the structure is drying.
- the sacrificial material can be formed without the need to cool the wafer in order to freeze the sacrificial material.
- the sacrificial material can be removed in the chamber 440 .
- the sacrificial material can be removed via sublimation by exposing the sacrificial material to sub-atmospheric pressure.
- the sacrificial material can be exposed to sub-atmospheric pressure via a pump 444 pressurizing the chamber 440 .
- the pump 444 can be a vacuum connected or separate from the chamber 440 , for example.
- sublimation can be accelerated by heating the structure.
- the structure can be heated by a temperature control mechanism 448 , for example.
- the sacrificial material can be removed via sublimation by heating the structure. Heating the structure can cause the sacrificial material in a solid state to thermally decompose into a gaseous product without melting.
- the structure can be heated using a temperature control 448 , for example a hot plate.
- the chamber 440 and/or temperature control 448 can include a gas purge 446 or a pump 444 , for example a vacuum, to remove the gaseous byproducts.
- the gas purge 446 and pump 444 can be provided to protect the structure from oxidation by removing the gaseous byproducts.
- the sacrificial material can be removed via sublimation by removing a reactive gas from the structure.
- the sacrificial material can decompose into a gas mixture in response to removing the reactive gas from the structure.
- the reactive gas can be removed via the gas purge 446 , for example.
- FIG. 5 is a block diagram of an apparatus, such as a memory device 550 .
- memory device 550 may be a volatile memory device, such as a DRAM, a non-volatile memory device, such as NAND flash or NOR flash, among others.
- memory device 550 may be formed, at least in part, using the processing previously described, such as in conjunction with FIGS. 2A-2D and FIG. 3 .
- Memory device 550 includes a controller 552 , such as an application specific integrated circuit (ASIC), coupled to a memory array 554 , such as a DRAM array, a NAND array, a NOR array, among others.
- ASIC application specific integrated circuit
- memory array 554 might be formed, at least in part, according to the processing described previously.
- the controller 552 can control the operations on the memory device 550 , and of the memory array 554 , including data sensing (e.g., reading) and data programming (e.g., writing), for example.
- Memory device 550 may be coupled to a host device (not shown in FIG. 5 ).
- Embodiments of the disclosure use sacrificial materials to obstruct openings in structures (e.g., to be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, and the like), such as between features in the structures.
- the sacrificial materials prevent condensate from forming in the openings as the structures are moved through a moist atmosphere between tools, thereby preventing the features from collapsing.
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Abstract
Description
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Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/847,601 US10964525B2 (en) | 2017-12-19 | 2017-12-19 | Removing a sacrificial material via sublimation in forming a semiconductor |
| CN201880081263.6A CN111492461A (en) | 2017-12-19 | 2018-12-03 | Sublimation when forming semiconductors |
| PCT/US2018/063555 WO2019125744A1 (en) | 2017-12-19 | 2018-12-03 | Sublimation in forming a semiconductor |
| TW107145863A TWI750433B (en) | 2017-12-19 | 2018-12-19 | Method for forming a semiconductor device and semiconductor processing system |
| TW110144407A TWI771235B (en) | 2017-12-19 | 2018-12-19 | Method for forming a semiconductor device and semiconductor processing system |
| US17/212,004 US12322585B2 (en) | 2017-12-19 | 2021-03-25 | Sublimation in forming a semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| US15/847,601 US10964525B2 (en) | 2017-12-19 | 2017-12-19 | Removing a sacrificial material via sublimation in forming a semiconductor |
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| US20190189426A1 US20190189426A1 (en) | 2019-06-20 |
| US10964525B2 true US10964525B2 (en) | 2021-03-30 |
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| US17/212,004 Active 2038-08-29 US12322585B2 (en) | 2017-12-19 | 2021-03-25 | Sublimation in forming a semiconductor |
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| JP2020178062A (en) * | 2019-04-19 | 2020-10-29 | メルク、パテント、ゲゼルシャフト、ミット、ベシュレンクテル、ハフツングMerck Patent GmbH | Substrate pattern filling composition and its use |
| US11859153B2 (en) | 2021-11-08 | 2024-01-02 | Changxin Memory Technologies, Inc. | Method for cleaning substrate and system for cleaning substrate |
Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008010638A (en) | 2006-06-29 | 2008-01-17 | Ulvac Seimaku Kk | Manufacturing method of semiconductor device |
| US7749909B2 (en) | 2008-06-16 | 2010-07-06 | Kabushiki Kaisha Toshiba | Method of treating a semiconductor substrate |
| US20110189858A1 (en) | 2010-02-01 | 2011-08-04 | Lam Research Corporation | Method for reducing pattern collapse in high aspect ratio nanostructures |
| US20130055584A1 (en) * | 2011-09-05 | 2013-03-07 | Yohei Sato | SUPERCRlTICAL DRYING METHOD FOR SEMICONDUCTOR SUBSTRATE |
| US20130081301A1 (en) | 2011-09-30 | 2013-04-04 | Applied Materials, Inc. | Stiction-free drying of high aspect ratio devices |
| US20150118821A1 (en) | 2013-10-29 | 2015-04-30 | Micron Technology, Inc. | Methods of forming semiconductor device structures, and methods of forming capacitor structures |
| US20150128991A1 (en) | 2013-11-11 | 2015-05-14 | Tokyo Electron Limited | Method and Hardware for Enhanced Removal of Post Etch Polymer and Hardmask Removal |
| US20150221500A1 (en) | 2014-02-06 | 2015-08-06 | Shin-Etsu Chemical Co., Ltd. | Method for cleaning and drying semiconductor substrate |
| US20150273535A1 (en) * | 2014-03-25 | 2015-10-01 | Kabushiki Kaisha Toshiba | Substrate processing apparatus and substrate processing method |
| US20160042945A1 (en) | 2014-08-11 | 2016-02-11 | Lam Research Corporation | Coverage of high aspect ratio features using spin-on dielectric through a wetted surface without a prior drying step |
| US20160097590A1 (en) | 2014-10-06 | 2016-04-07 | Lam Research Corporation | Systems and methods for drying high aspect ratio structures without collapse using sacrificial bracing material that is removed using hydrogen-rich plasma |
| US20170062244A1 (en) * | 2015-08-26 | 2017-03-02 | Kabushiki Kaisha Toshiba | Substrate processing method and substrate processing apparatus |
| JP2017050576A (en) | 2016-12-15 | 2017-03-09 | 東京エレクトロン株式会社 | Substrate drying method and substrate processing apparatus |
| US9653307B1 (en) | 2016-07-14 | 2017-05-16 | Micron Technology, Inc. | Surface modification compositions, methods of modifying silicon-based materials, and methods of forming high aspect ratio structures |
| TW201725280A (en) | 2016-01-15 | 2017-07-16 | 台灣積體電路製造股份有限公司 | Atomic layer deposition equipment and semiconductor processes |
| US20170250094A1 (en) | 2012-11-26 | 2017-08-31 | Applied Materials, Inc. | Stiction-free drying process with contaminant removal for high-aspect ratio semiconductor device str |
| KR20170132676A (en) | 2016-05-24 | 2017-12-04 | 가부시키가이샤 스크린 홀딩스 | Substrate processing apparatus and substrate processing method |
| US20190189427A1 (en) * | 2017-12-19 | 2019-06-20 | Micron Technology, Inc. | Freezing a sacrificial material in forming a semiconductor |
| US20190189424A1 (en) * | 2017-12-19 | 2019-06-20 | Micron Technology, Inc. | Using sacrificial solids in semiconductor processing |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102009058278B3 (en) | 2009-12-13 | 2011-05-19 | Stiftung Alfred-Wegener-Institut Für Polar- Und Meeresforschung | Device for locating and harvesting marine hard-bottomed animals |
-
2017
- 2017-12-19 US US15/847,601 patent/US10964525B2/en active Active
-
2018
- 2018-12-03 CN CN201880081263.6A patent/CN111492461A/en not_active Withdrawn
- 2018-12-03 WO PCT/US2018/063555 patent/WO2019125744A1/en not_active Ceased
- 2018-12-19 TW TW110144407A patent/TWI771235B/en active
- 2018-12-19 TW TW107145863A patent/TWI750433B/en active
-
2021
- 2021-03-25 US US17/212,004 patent/US12322585B2/en active Active
Patent Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008010638A (en) | 2006-06-29 | 2008-01-17 | Ulvac Seimaku Kk | Manufacturing method of semiconductor device |
| US7749909B2 (en) | 2008-06-16 | 2010-07-06 | Kabushiki Kaisha Toshiba | Method of treating a semiconductor substrate |
| US20110189858A1 (en) | 2010-02-01 | 2011-08-04 | Lam Research Corporation | Method for reducing pattern collapse in high aspect ratio nanostructures |
| US8617993B2 (en) | 2010-02-01 | 2013-12-31 | Lam Research Corporation | Method of reducing pattern collapse in high aspect ratio nanostructures |
| US20130055584A1 (en) * | 2011-09-05 | 2013-03-07 | Yohei Sato | SUPERCRlTICAL DRYING METHOD FOR SEMICONDUCTOR SUBSTRATE |
| US20130081301A1 (en) | 2011-09-30 | 2013-04-04 | Applied Materials, Inc. | Stiction-free drying of high aspect ratio devices |
| US20170250094A1 (en) | 2012-11-26 | 2017-08-31 | Applied Materials, Inc. | Stiction-free drying process with contaminant removal for high-aspect ratio semiconductor device str |
| US20150118821A1 (en) | 2013-10-29 | 2015-04-30 | Micron Technology, Inc. | Methods of forming semiconductor device structures, and methods of forming capacitor structures |
| US20150128991A1 (en) | 2013-11-11 | 2015-05-14 | Tokyo Electron Limited | Method and Hardware for Enhanced Removal of Post Etch Polymer and Hardmask Removal |
| US20150221500A1 (en) | 2014-02-06 | 2015-08-06 | Shin-Etsu Chemical Co., Ltd. | Method for cleaning and drying semiconductor substrate |
| US20150273535A1 (en) * | 2014-03-25 | 2015-10-01 | Kabushiki Kaisha Toshiba | Substrate processing apparatus and substrate processing method |
| US20160042945A1 (en) | 2014-08-11 | 2016-02-11 | Lam Research Corporation | Coverage of high aspect ratio features using spin-on dielectric through a wetted surface without a prior drying step |
| US20160097590A1 (en) | 2014-10-06 | 2016-04-07 | Lam Research Corporation | Systems and methods for drying high aspect ratio structures without collapse using sacrificial bracing material that is removed using hydrogen-rich plasma |
| US20170062244A1 (en) * | 2015-08-26 | 2017-03-02 | Kabushiki Kaisha Toshiba | Substrate processing method and substrate processing apparatus |
| TW201725280A (en) | 2016-01-15 | 2017-07-16 | 台灣積體電路製造股份有限公司 | Atomic layer deposition equipment and semiconductor processes |
| KR20170132676A (en) | 2016-05-24 | 2017-12-04 | 가부시키가이샤 스크린 홀딩스 | Substrate processing apparatus and substrate processing method |
| US10153181B2 (en) | 2016-05-24 | 2018-12-11 | SCREEN Holdings Co., Ltd. | Substrate treating apparatus and substrate treating method |
| US9653307B1 (en) | 2016-07-14 | 2017-05-16 | Micron Technology, Inc. | Surface modification compositions, methods of modifying silicon-based materials, and methods of forming high aspect ratio structures |
| JP2017050576A (en) | 2016-12-15 | 2017-03-09 | 東京エレクトロン株式会社 | Substrate drying method and substrate processing apparatus |
| US20190189427A1 (en) * | 2017-12-19 | 2019-06-20 | Micron Technology, Inc. | Freezing a sacrificial material in forming a semiconductor |
| US20190189424A1 (en) * | 2017-12-19 | 2019-06-20 | Micron Technology, Inc. | Using sacrificial solids in semiconductor processing |
Non-Patent Citations (5)
| Title |
|---|
| Buriak "Organometallic Chemistry on Silicon and Germanium Surfaces", Chemical Reviews, vol. 102, No. 5, Mar. 8, 2002, pp. 1271-1308. |
| Chen, et al. "Non-Stiction Performance of Various Post Wet-Clean Drying Schemes on High-Aspect-Ratio Device Structures", The Electrochemical Society, vol. 58, Issue 6, 2013, 1 pp. |
| International Search Report and Written Opinion from related international application No. PCT/US2018/063555, dated Mar. 25, 2019, 12 pages. |
| Office Action from related Taiwan patent application No. 107145863, dated Sep. 23, 2019, 12 pages. |
| Rejection Decision from related Taiwan patent application No. 107145863, dated Jan. 21, 2020, 7 pages. |
Also Published As
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|---|---|
| TWI750433B (en) | 2021-12-21 |
| US12322585B2 (en) | 2025-06-03 |
| WO2019125744A1 (en) | 2019-06-27 |
| CN111492461A (en) | 2020-08-04 |
| US20190189426A1 (en) | 2019-06-20 |
| TWI771235B (en) | 2022-07-11 |
| TW202210183A (en) | 2022-03-16 |
| TW201936276A (en) | 2019-09-16 |
| US20210210341A1 (en) | 2021-07-08 |
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