US10541203B2 - Nickel-silicon fuse for FinFET structures - Google Patents
Nickel-silicon fuse for FinFET structures Download PDFInfo
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- US10541203B2 US10541203B2 US16/003,820 US201816003820A US10541203B2 US 10541203 B2 US10541203 B2 US 10541203B2 US 201816003820 A US201816003820 A US 201816003820A US 10541203 B2 US10541203 B2 US 10541203B2
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- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 title description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 62
- 239000002019 doping agent Substances 0.000 claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 description 32
- 239000010410 layer Substances 0.000 description 27
- 238000000034 method Methods 0.000 description 25
- 230000015572 biosynthetic process Effects 0.000 description 22
- 230000008569 process Effects 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 238000000151 deposition Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 8
- 238000013461 design Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- -1 i.e. Substances 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 239000012265 solid product Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- PFNQVRZLDWYSCW-UHFFFAOYSA-N (fluoren-9-ylideneamino) n-naphthalen-1-ylcarbamate Chemical compound C12=CC=CC=C2C2=CC=CC=C2C1=NOC(=O)NC1=CC=CC2=CC=CC=C12 PFNQVRZLDWYSCW-UHFFFAOYSA-N 0.000 description 1
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910020751 SixGe1-x Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000012707 chemical precursor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H05K999/99—
Definitions
- the present invention generally relates to semiconductor devices and, more particularly, to nickel-silicon fuses formed with fin field effect transistor (FinFET) processes.
- FinFET fin field effect transistor
- Fin field effect transistor (FinFET) devices are prevalent in modern circuit designs. Their advantageous electronic characteristics and small layout area make them suitable for many different applications. However, full circuit designs often make use of other structures, such as capacitors and fuses, to perform certain functions.
- a fuse includes a semiconductor fin having a metallized region between two non-metallized regions. Conductive layers are formed on the semiconductor fin above the two non-metallized regions. A dielectric layer is formed over the metallized region, between the conductive layers.
- FIG. 1 is a cross-sectional view of a step in the formation of a semiconductor fuse in accordance with the present embodiments
- FIG. 2 is a cross-sectional view of a step in the formation of a semiconductor fuse in accordance with the present embodiments
- FIG. 3 is a cross-sectional view of a step in the formation of a semiconductor fuse in accordance with the present embodiments
- FIG. 4 is a cross-sectional view of a step in the formation of a semiconductor fuse in accordance with the present embodiments
- FIG. 5 is a cross-sectional view of a step in the formation of a semiconductor fuse in accordance with the present embodiments
- FIG. 6 is a cross-sectional view of a step in the formation of a semiconductor fuse in accordance with the present embodiments
- FIG. 7 is a cross-sectional view of a step in the formation of a semiconductor fuse in accordance with the present embodiments.
- FIG. 8 is a cross-sectional view of a step in the formation of a semiconductor fuse in accordance with the present embodiments.
- FIG. 9 is a cross-sectional view of a step in the formation of a semiconductor fuse in accordance with the present embodiments.
- FIG. 10 is a block/flow diagram of a method of forming a semiconductor fuse in accordance with the present embodiments.
- Embodiments of the present invention provide electronically programmable fuses based on a fin field effect transistor (FinFET) fabrication process.
- FinFET fin field effect transistor
- the integration of fuse fabrication with standard FinFET processes makes it easier to implement these devices on the same chip as FinFETs, reducing the number of steps needed to fabricate the entire chip and thereby reducing the cost to make the finished product.
- the present embodiments form a semiconductor fin, form a source and drain outside of a dummy gate, remove the dummy gate, and silicide the portion of the fin that would represent the channel in a conventional FinFET.
- Such silicide fins form the programmable fuse.
- the electromigration effect is used to cause the conductive silicide material to move and separate. Under a sufficiently high current density, the material of the silicide fin will partially or fully break, thereby significantly changing the resistance of the device.
- the logical state of the fuse i.e., whether the fuse is whole or tripped
- electromigration is described by the mean time to failure, which can be characterized as:
- MTTF A J n ⁇ e E a kT
- A is the cross sectional area of the fin
- J is the current density
- E a is the activation energy
- k is Boltzmann's constant
- T is the temperature in Kelvin
- n is a scaling factor.
- a semiconductor fin 102 is provided and is shown in lengthwise in this figure.
- the semiconductor fin 102 may formed from a bulk-semiconductor substrate.
- the bulk-semiconductor substrate may be a silicon-containing material.
- silicon-containing materials suitable for the bulk-semiconductor substrate include, but are not limited to, silicon, silicon germanium, silicon carbide, polysilicon, epitaxial silicon, amorphous silicon, and multi-layers thereof.
- silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed, such as, but not limited to, germanium, gallium arsenide, gallium nitride, cadmium telluride, and zinc selenide.
- the semiconductor fin 102 may be formed from a semiconductor-on-insulator substrate with a buried insulator layer 104 underneath a semiconductor layer. It is specifically contemplated that the buried insulator layer 104 may be, e.g., a silicon dioxide layer, but it should be understood that any appropriate insulating or dielectric material may be used instead. In other embodiments, the insulator layer 104 may be formed on a lower bulk semiconductor substrate.
- the semiconductor fin 102 may itself be formed by any appropriate lithographic process including, e.g., a photolithographic mask and etch.
- a layer of semiconductor material is deposited on the buried insulator layer 104 .
- a pattern is produced by applying a photoresist to the surface of the deposited semiconductor material. The photoresist is exposed to a pattern of radiation that causes a chemical reaction within the photoresist. The pattern is then developed into the photoresist utilizing a resist developer. Once the patterning of the photoresist is completed, the sections covered by the photoresist are protected while the exposed regions are removed using a selective etching process that removes the unprotected regions. The photoresist may also be removed after patterning is complete.
- a hardmask may be used to form the semiconductor fin 102 .
- the mask may be formed by first depositing a dielectric hardmask material, like silicon nitride or silicon dioxide atop a layer of semiconductor layer and then applying a photoresist pattern to the hardmask material using a lithography process. The photoresist pattern is then transferred into the hardmask material using a dry etch process. Next the photoresist pattern is removed and the pattern is transferred into the semiconductor material during a selective etching process, such as reactive ion etching (RIE). The remaining mask material may be removed by a wet or dry etch.
- RIE reactive ion etching
- RIE is a form of plasma etching in which during etching the surface to be etched is placed on a radio-frequency powered electrode. Moreover, during RIE the surface to be etched takes on a potential that accelerates the etching species extracted from plasma toward the surface, in which the chemical etching reaction is taking place in the direction normal to the surface.
- anisotropic etching that can be used at this point of the present invention include ion beam etching, plasma etching or laser ablation.
- the semiconductor fin 102 can be formed by other patterning techniques such as spacer image transfer.
- a dummy gate 202 is formed on and around the semiconductor fin 102 .
- the semiconductor fin 102 has a thin oxide layer around it to separate it from the dummy gate 202 and to enable later removal.
- the dummy gate 202 may be formed from a semiconductor material such as polysilicon, but any appropriate, patternable material may be used instead.
- a layer of dummy gate material is deposited on the semiconductor fin 102 and subsequently patterned with, e.g., photolithographic processes to create the dummy gate structure.
- the hardmask used to pattern the dummy gate 202 may be left intact after patterning.
- a spacer 204 is formed conformally on the dummy gate 202 . It is specifically contemplated that the spacer 204 may be formed from silicon nitride, but it should be understood that any appropriate insulating, dielectric, or hardmask material may be used instead.
- the spacer 204 may be formed in some embodiments by conformally depositing spacer material on the semiconductor fin 102 and then anisotropically etching the material to remove the deposited dielectric from horizontal surfaces. The remaining vertical dielectric material and the remaining hardmask from dummy gate formation form the spacer 204 .
- Conductive regions 302 are formed on the semiconductor fin 102 .
- the conductive regions 302 may be formed from a doped semiconductor.
- the conductive regions 302 match the source and drain regions of conventional FinFETs and may be formed by the same processes.
- the conductive regions 302 may be epitaxially grown from the portions of the semiconductor fin 102 that are not covered by the dummy gate 202 .
- the conductive regions 302 may be in situ doped during epitaxial growth or, alternatively, may be doped by implantation or any other appropriate process for adding dopant to the material.
- the dopant may be either a p-type dopant or an n-type dopant.
- p-type refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons.
- examples of p-type dopants, i.e., impurities include but are not limited to: boron, aluminum, gallium and indium.
- n-type refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor in a silicon containing substrate
- impurities include but are not limited to antimony, arsenic and phosphorous.
- conductive regions 302 that are formed from silicon with a phosphorous dopant or silicon germanium (with a germanium content of between about 20% and about 60%) with a boron dopant, but it should be understood that any appropriate combination of semiconductor material and dopant may be used instead.
- a dopant concentration range of about 4 ⁇ 10 10 /cm 3 to about 2 ⁇ 10 21 /cm 3 may be used.
- FIG. 4 a cross-sectional view of a step in the formation of a FinFET-based fuse is shown.
- An inter-layer dielectric 402 is deposited over and around the gate 202 , conductive regions 302 , and semiconductor fins 102 and polished down to the level of the gate 202 . It is specifically contemplated that the inter-layer dielectric 402 may be formed from silicon dioxide, but it should be understood that any appropriate dielectric or insulating material may be used instead.
- the inter-layer dielectric 402 may be formed by any appropriate process including, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition.
- CVD is a deposition process in which a deposited species is formed as a result of chemical reaction between gaseous reactants at greater than room temperature (e.g., from about 25° C. about 900° C.).
- the solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed.
- CVD processes include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), Plasma Enhanced CVD (PECVD), and Metal-Organic CVD (MOCVD) and combinations thereof may also be employed.
- APCVD Atmospheric Pressure CVD
- LPCVD Low Pressure CVD
- PECVD Plasma Enhanced CVD
- MOCVD Metal-Organic CVD
- a sputtering apparatus may include direct-current diode systems, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering.
- chemical precursors react with the surface of a material one at a time to deposit a thin film on the surface.
- a high-pressure gas is allowed to expand in a vacuum, subsequently condensing into clusters.
- the clusters can be ionized and directed onto a surface, providing a highly anisotropic deposition.
- the inter-layer dielectric 402 is polished down using, e.g., chemical mechanical planarization (CMP).
- CMP is performed using, e.g., a chemical or granular slurry and mechanical force to gradually remove upper layers of the device.
- the slurry may be formulated to be unable to dissolve, for example, the dummy gate material, resulting in the CMP process's inability to proceed any farther than that layer.
- FIG. 5 a cross-sectional view of a step in the formation of a FinFET-based fuse is shown.
- the dummy gate 202 is removed, exposing the underlying region 502 of the semiconductor fin 102 .
- the vertical portion of the spacer 204 remains as sidewalls 504 , defining the edges of the exposed region 502 .
- the dummy gate 202 may be removed by any appropriate wet or dry etch that selectively removes the dummy gate material while leaving the vertical sidewalls 504 , the inter-layer dielectric 402 , and the semiconductor fin 102 unharmed.
- the height of the exposed portion of the semiconductor fin 102 may be trimmed using any appropriate etch such as, e.g., a wet oxide etch, a thermal oxide etch, or a hydrochloric acid etch.
- the trimmed region 602 has a smaller cross sectional area than the untrimmed fin, such that the amount of current needed to break the fuse will be smaller.
- the fuse can be precisely fabricated with desired fuse properties, in particular by providing a cross-sectional area that would be difficult or impossible to create with lithographic processes alone or with fin heights that are substantially different than those used for other fin-based devices on the same chip.
- the final fuse may have a width of about 16 nm. Trimming the silicon fins to values below 8 nm will proportionally decrease the final fuse size.
- a metallized region 702 is formed on the exposed portion 502 of the semiconductor fin 102 . It is specifically contemplated that the metallized region 702 may be formed as a silicide—an alloy of metal and silicon—but it should be understood that the metallized region may alternatively be formed using any appropriate semiconductor material such as, e.g., germanium (germanicide) or silicon germanium. In one specific embodiment, the metallized region 702 may be formed as an alloy of nickel and silicon, though other metals, such as titanium or platinum, are contemplated as well.
- Silicide formation typically involves the deposition of a refractory metal such as nickel or titanium by any appropriate deposition process onto the surface of a semiconductor material. Following deposition, the structure is then subjected to an annealing step using conventional processes such as, but not limited to, rapid thermal annealing. In one specific embodiment, the silicidation anneal may be performed at about 420° C. for about 5 minutes, with a temperature range between about 400° C. and about 450° C. for a time period of about 5 minute to about 10 minutes also being contemplated. During thermal annealing, the deposited metal reacts with the semiconductor, forming a metal silicide.
- a refractory metal such as nickel or titanium
- the metallized region 702 will have a fully silicide cross section, such that every part of the cross section is conductive and undergoes electromigration.
- a passivating insulator or dielectric 802 is deposited over the metallized region 702 .
- the passivating layer 802 may be formed from, e.g., silicon dioxide or any other appropriate material using, for example, CVD, ALD, PVD, or any other suitable deposition process.
- the passivating material may then be polished down to the level of the vertical sidewalls 502 using, e.g., CMP.
- Conductive contacts 902 are formed by forming holes in the inter-layer dielectric 402 using an anisotropic etch, such as RIE, and depositing a suitable conductive material therein. It is specifically contemplated that the conductive contacts 902 may be formed from a metal such as, e.g., copper, nickel, titanium, gold, silver, aluminum, platinum, or alloys thereof. A CMP process removes any excess conductive material. This completes the fuse structure. It is specifically contemplated that each fuse will have a single respective fin, to decrease the likelihood of ambiguous or incomplete fuse breakage, but it should be understood that multiple fins may be used in a single fuse with merged contacts.
- anisotropic etch such as RIE
- the present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly.
- the stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer.
- the photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes Si x Ge 1-x where x is less than or equal to 1, etc.
- SiGe includes Si x Ge 1-x where x is less than or equal to 1, etc.
- other elements can be included in the compound and still function in accordance with the present principles.
- the compounds with additional elements will be referred to herein as alloys.
- such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C).
- This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
- spatially relative terms such as “beneath.” “below.” “lower,” “above.” “upper.” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below.
- the device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.
- a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.
- Block 1002 forms a fin 102 from, e.g., a semiconductor substrate using any appropriate fabrication technique, such as photolithography and sidewall image transfer.
- Block 1004 forms a dummy gate 202 over the semiconductor fin 102 with an accompanying spacer 204 .
- Block 1006 grows the conductive regions 302 epitaxially on the fins 102 .
- the conductive regions 302 may be formed from a doped semiconductor material such as, e.g., phosphorous-doped silicon or boron-doped silicon germanium.
- Block 1008 forms an inter-layer dielectric 402 over the conductive regions 302 that may be formed from any appropriate dielectric material such as, e.g., silicon dioxide. Block 1008 deposits the dielectric material and then polishes the layer down to the level of the dummy gate 202 .
- Block 1010 removes the dummy gate 202 using any appropriate etch to expose the underlying region 502 of the semiconductor fin 102 .
- Block 1012 optionally trims the height of the semiconductor fin 102 to adjust the properties of the fuse.
- Block 1014 then metallizes the exposed fin region 502 by, e.g., depositing a metal such as nickel and annealing the exposed fin region 502 to form metallized region 702 .
- Block 1016 forms a passivating dielectric over the metallized region 702 from, e.g., silicon dioxide.
- Block 1018 forms holes within the inter-layer dielectric 402 that reach down to the conductive regions 302 and then forms conductive contacts 902 in the holes to complete the fuse.
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Abstract
Description
where A is the cross sectional area of the fin, J is the current density, Ea is the activation energy, k is Boltzmann's constant, T is the temperature in Kelvin, and n is a scaling factor. Thus, the amount of time for the device to fail (i.e., for the fuse to be programmed by causing a break in the conductive material of the silicide fin) decreases as the current density increases and as the cross-sectional area decreases. As a result, a lower cross-sectional area means that a correspondingly lower current density is needed, making FinFET fuses particularly useful in situations where a fuse needs to be programmed quickly or with little energy expenditure.
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US15/271,698 US9799600B1 (en) | 2016-09-21 | 2016-09-21 | Nickel-silicon fuse for FinFET structures |
US15/471,479 US10062643B2 (en) | 2016-09-21 | 2017-03-28 | Nickel-silicon fuse for FinFET structures |
US16/003,820 US10541203B2 (en) | 2016-09-21 | 2018-06-08 | Nickel-silicon fuse for FinFET structures |
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US15/471,479 Active 2036-09-26 US10062643B2 (en) | 2016-09-21 | 2017-03-28 | Nickel-silicon fuse for FinFET structures |
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US20180082948A1 (en) | 2018-03-22 |
US9799600B1 (en) | 2017-10-24 |
US20180294223A1 (en) | 2018-10-11 |
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