US10458842B2 - Low flux and low noise detection circuit - Google Patents
Low flux and low noise detection circuit Download PDFInfo
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- US10458842B2 US10458842B2 US15/818,220 US201715818220A US10458842B2 US 10458842 B2 US10458842 B2 US 10458842B2 US 201715818220 A US201715818220 A US 201715818220A US 10458842 B2 US10458842 B2 US 10458842B2
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/44—Electric circuits
- G01J1/46—Electric circuits using a capacitor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
- G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
- G01J5/20—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
- G01J5/22—Electrical features thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/30—Transforming light or analogous information into electric information
- H04N5/33—Transforming infrared radiation
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- H04N5/361—
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- H04N5/363—
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- H04N5/3745—
Definitions
- the invention relates to a detection circuit.
- Optic detection circuits generally comprise a photodetector connected to a readout circuit.
- the function of the readout circuit is to convert and if necessary to amplify the signal coming from the photodetector so that it can be processed.
- FIG. 1 represents an example of a detection circuit commonly used with photodetectors.
- the circuit comprises a photodetector 1 and a readout circuit 2 .
- One terminal of the photodetector 1 is connected to the readout circuit 2 .
- the other terminal of the photodetector 1 is connected to the potential of the photodetector substrate V SUB .
- the readout circuit 2 can be of integrator type. It performs two functions—firstly it integrates the current I 1 of the photodetector 1 and thus converts the current into a usable voltage V S , and secondly it performs biasing of the photodetector 1 .
- the readout circuit 2 can be formed by a capacitive transimpedance amplifier (CTIA) represented in FIG. 1 .
- CTIA capacitive transimpedance amplifier
- Such an integrator comprises an operational amplifier 3 .
- the first input of the amplifier 3 the negative input, forms the input of the readout circuit 2
- the output of the amplifier 3 forms the output of the readout circuit 2 .
- the second input of the amplifier receives a reference potential V REF .
- the readout circuit 2 also comprises an integration capacitor C 1 and a reset switch S 1 connected in parallel between the first input of the amplifier and the output of the amplifier.
- the output of the readout circuit 2 delivers the voltage V S representative of the received signal.
- This embodiment is particularly efficient for detection and management of medium or weak optic signals, but this efficiency is obtained to the detriment of size and consumption. Furthermore, when the photodetector receives a light flux of very low intensity, the signal-to-noise ratio is in fact impaired by the emission of stray photons emitted by the amplifier implanted in the pixel and it is very difficult to obtain attractive performances.
- the detection circuit is engineered in particular manner by means of an SFD (Source follower per Detector) architecture illustrated in FIG. 2 .
- SFD Source follower per Detector
- This type of sensor operates with weak radiation conditions, i.e. with a low incident flux.
- the incident radiation is converted into a quantity of electrons which is representative of the observed scene.
- the electronic noise generated by the detection circuit i.e. the quantity of electrons not linked to the observed scene.
- the first means for reducing the quantity of stray electrons is to limit the electric consumption of the circuit which incites the detection circuit to be simplified. Integration of the charges emitted by the photodetector is then performed by the internal capacitor of the photodetector.
- the detection circuit comprises a photodiode 1 with so its internal capacitor C PD .
- the circuit also comprises a reset transistor T 1 which performs the connection between the photodetector 1 and a bias voltage Vreset. Switching of the reset transistor T 1 between a saturated On state and an Off state makes the photodiode 1 switch between a reverse bias and a floating state.
- the photodiode 1 When the photodiode 1 is in a floating state, the electric charges generated are stored in the stray capacitor C PD . As the electric charges are progressively stored in the capacitor C PD , the voltage at the terminals of the photodiode 1 changes. This change of bias conditions generally results in an impairment of the integrity of the signal, for example with a modification of the conversion rate of the electromagnetic radiation received into a quantity of electrons, by the variation of the capacitance value of capacitor C PD or by the increase of the stray leakage current in the detector.
- the photodiode 1 is also connected to a processing circuit 4 which processes the signal emitted by the photodiode 1 .
- the charges generated by the photodiode 1 are partly stored by the internal capacitor C PD of the photodiode 1 which results in a modification of the potential of the integration node N connected to the processing circuit 4 .
- the electric capacitance of the integration node N results partially from the electric capacitance of the photodiode 1 and partially from the stray capacitances of the other components connected to the integration node N.
- the circuit is remarkable in that it comprises:
- FIG. 1 represents a detection circuit of capacitive transimpedance amplifier type, in schematic manner
- FIG. 2 represents a detection circuit of SFD type, in schematic manner
- FIG. 3 represents a particular embodiment of a detection circuit according to the invention, in schematic manner
- FIG. 4 represents, in schematic manner, several detection circuits according to the invention in relation with a detection matrix.
- the detection circuit partially presents an assembly of SFD (Source follower per Detector) type.
- the detection circuit comprises a photodetector 1 which is preferentially a photodiode.
- Photodetector 1 is associated with a bias circuit 5 .
- Bias circuit 5 biases photodetector 1 between first and second different states corresponding to first and second periods.
- photodetector 1 is in the first state, photodetector 1 advantageously being reverse biased.
- the photodetector is in the second state, photodetector 1 being left in a floating state where the initial bias, for example reverse bias, changes according to the accumulation of received charges, in this case the change takes place to forward bias.
- Acquisition of the electromagnetic signal is performed when photodetector 1 is in the second state, i.e. during the second period. Setting to floating state is achieved by leaving the electrode initially connected to bias circuit 5 at a floating potential.
- photodetector 1 is represented schematically as a current source as it delivers electric charges according to the electromagnetic radiation received.
- Photodetector 1 can be a photodiode, a quantum well or multi-quantum well device, or any other detector that is configured to transform incident electromagnetic radiation into electric charges.
- bias circuit 5 is formed in compact manner by means of a switch T 1 which connects a bias voltage Vreset source to a first electrode of photodetector 1 .
- switch T 1 is formed by a transistor and advantageously by a field effect 16 transistor.
- the control electrode of switch T 1 is connected to a control circuit A, for example a signal generator which emits the signal RSEL Rn .
- switch T 1 switches between on and off state and photodetector 1 switches between a reverse bias and a floating state.
- the second electrode of photodetector 1 is connected to a voltage source which delivers the voltage Vdet.
- the signal RSEL Rn enables the first and second periods to be defined.
- the detection circuit comprises an integration node N formed by the connection between the first electrode of photodetector 1 and the first electrode of a first capacitor also called integration capacitor C INT .
- integration node N is formed by stray capacitor C PD and integration capacitor C INT .
- Integration node N is also connected to bias circuit 5 .
- photodetector 1 During the acquisition period, i.e. the second period, photodetector 1 is in its floating state, i.e. it is connected to the capacitive integration node N which conserves the electric charges generated by the photodetector. Photodetector 1 transforms light radiation into electric charges which are stored in stray capacitor C PD and also in integration capacitor C INT . Accumulation of the electric charges in these two capacitors will result in a modification of the potential of capacitive integration node N. When bias 6 circuit 5 sets photodetector 1 to a floating potential, integration node N sees its potential change as the electric charges are progressively generated and stored in capacitors C PD and C INT .
- photodetector 1 may generate different quantities of electric charges depending on its bias state.
- the device comprises a modulation circuit of the power supply conditions of photodetector 1 whereas the latter is at a floating potential, i.e. during the second period.
- the modulation circuit is configured to set photodetector 1 back to its initial bias state without eliminating the generated electric charges or at least to set the photodetector to a state that is close to its initial state defined during the first period.
- the bias conditions at the terminals of the photodetector being more stable in time, it is then easier to compare two electric signals to compare two optic signals in quantitative manner.
- modification of the bias at the terminals of so photodetector 1 is performed by transfer of at least a part of the electric charges stored in capacitor C PD to integration capacitor C INT .
- the electric charges are eliminated to revert to the initial bias state, in this embodiment the electric charges are transferred to prevent the introduction of stray electric charges. Transfer of the charges takes place during the acquisition period.
- the detection circuit advantageously comprises a transfer circuit 6 configured to transfer electric charges from capacitor C PD to integration capacitor C INT . Transfer of the charges enables at least a part of the charges accumulated in stray capacitor C PD to be removed and to be transferred to integration capacitor C INT . Transfer of the charges generated and stored in capacitor C PD enables the fluctuations in the bias conditions of photodetector 1 to be limited. In this way, for the same optic signal, photodetector 1 generates substantially the same quantity of electric charges over a longer time period and it is therefore easier to quantitatively compare the received signals.
- Transfer circuit 6 is advantageously configured to disable transfer of the electric charges when the potential of the integration node reaches a predefined value.
- This predefined value is advantageously equal or close to the target value defined during the first period.
- Transfer of the electric charges from capacitor C PD to capacitor C INT is performed by injecting electric charges into the second electrode of capacitor C INT .
- transfer of the electric charges is performed by modifying the bias of the second electrode of capacitor C INT , for example by applying a voltage on the second electrode.
- This particular architecture enables the potential value of integration node N to be measured. It is then possible to initiate and/or terminate transfer of the electric charges from capacitor C PD to integration capacitor C INT according to the potential value of integration node N.
- Transfer may be conditioned on the potential of integration node N reaching a threshold value measured by measurement circuit 7 .
- photodetector 1 By resetting integration node N to a target value which is close to the conditions defined in the first period, photodetector 1 will also be reset to bias conditions close to those defined by the first period. If several transfers are performed during the second period, using a constant or substantially constant target value enables the repeatability of the measurements to be enhanced.
- measurement circuit 7 of the potential value of integration node N can be activated before electric charge transfer circuit 6 . In this way, measurement circuit 7 will measure the value of the potential at integration node N and, if the latter reaches the threshold value, this triggers transfer of electric charges from capacitor C PD to capacitor C INT . When transfer of the charges takes place, measurement circuit 7 can be active and measures the potential of integration node N. Measurement circuit 7 stops transfer of the electric charges when the potential of integration node N reaches the target value.
- measurement circuit 7 of the potential value of integration node N and electric charge transfer circuit 6 are activated simultaneously so that transfer of the charges takes place until the potential of integration node N reaches the target value.
- Transistor T 2 is advantageously a field effect transistor so that integration node N is completely insulated electrically from the other components of the circuit. This electric insulation prevents electric charges from being lost from the node N or injected into the node N thereby avoiding introducing a deviation from what has been actually detected by the photodetector.
- the generated signal is no longer distorted and a better correlation between the optic signal received and the electric signal can be obtained. In other words, the signal is less impaired than in circuits of the prior art.
- the electric charges generated by photodetector 1 cannot be lost as integration node N is completely insulated from the other components of the circuit, i.e. by the insulating layer forming integration capacitor C INT , by the gate insulator of transistor T 2 and by the insulators of the capacitors.
- Integration node N is connected to measurement circuit 7 so that the latter delivers data representative of the potential at the node N.
- circuit 7 can be configured to deliver digital data or analog data.
- This data is delivered to transfer circuit 6 to initiate and/or disable transfer of the electric charges.
- the voltage delivered by transistor T 2 changes in analog manner with the potential value of integration node N. If a voltage represented in digital form is required, it is possible to connect an analog-to-digital converter on output of transistor T 2 , which converter will deliver digital data representative of the measured value.
- Transfer circuit 6 can be achieved in different manners.
- activation and disabling of the transfer circuit are linked to emission of signals by measurement circuit 7 which emits signals of ON/OFF type.
- Measurement circuit 7 can emit an activation signal of transfer circuit 6 so long as the potential of node N does not reach the target value.
- the signals emitted by measurement circuit 7 are representative of the potential of node N which enables transfer circuit 6 to make node N converge more easily on the target value.
- the signal emitted by measurement circuit 7 is analysed in real time in order to apply a voltage on the second electrode of capacitor C INT and to make node N converge to the target value.
- the signals emitted by measurement circuit 7 are analysed and analysis of these signals enables a charge or a current sent to the second electrode of capacitor C INT to be modulated.
- transfer circuit 6 comprises an amplifier 8 and the voltage delivered by transistor T 2 is applied to the input of amplifier 8 .
- the other input of amplifier 8 is connected to a voltage source which delivers a voltage Vamp, here voltage Vamp is advantageously offset from voltage Vreset by a value equal to the threshold voltage of transistor T 2 .
- Transfer circuit 6 is also configured to deliver the voltage value which enables the charges to be transferred from detector 1 and from its stray capacitor C PD to integration capacitor C INT .
- transfer circuit 6 when transfer circuit 6 receives data indicating that node N has strayed from its target value, amplifier 8 delivers the signal to be applied to transfer the charges from capacitor C PD to capacitor C INT and transfer circuit 6 applies this signal to capacitor C INT .
- the second electrode of capacitor C INT charges until the electric charges stored in capacitor C PD have been transferred to capacitor C INT and the potential of node N has reverted to the initial potential.
- the measurement circuit delivers data, for example a voltage, indicating that node N is at the target value and the output of transfer circuit 6 stabllises at the value representative of the received signal and stops charging capacitor C INT .
- the value representative of the received signal is available on the output OUT of transfer circuit 6 .
- Transfer circuit 6 can be shut down and the electric charges accumulated in the second electrode of capacitor C INT are kept, and integration node N can be charged again with new electric charges generated by photodetector 1 .
- amplifier 8 is formed by an operational amplifier.
- the output of amplifier 8 is feedback connected in integrator mode and delivers on output a suitable voltage to make the voltage delivered by transistor T 2 converge to voltage Vamp, i.e. to make node N converge to its initial value.
- This embodiment is particularly advantageous as it enables the output of comparator 8 to be connected directly on the second electrode of capacitor C INT and at the same time enables a signal representative of the optic signal to obtained on output of the same amplifier.
- amplifier 8 is formed by an operational amplifier, it is advantageous to perform reset of the second electrode of capacitor C INT by short-circuiting the output terminal of amplifier 8 with its input terminal connected to measurement circuit 7 .
- Short-circuiting can be performed by means of a switch which receives signal S reset from a signal generator on its control electrode.
- the measurement circuit or the transfer circuit can be configured to deliver data representative of the difference between the voltage value measured on integration node N and the target value or a value representative of the target value.
- This data representative of the difference is used to define the voltage variation to be applied on the second terminal of capacitor C INT or of the quantity of electric charges to be applied on the second electrode of capacitor C INT .
- transfer circuit 6 is illustrated in a configuration with an amplifier which is particularly advantageous to facilitate conversion to the target value, it is also possible to use a comparator to charge capacitor C INT .
- measurement circuit 7 is configured to deliver a voltage representative of the charges received by detector 1 and stored on node N.
- node N is in fact at its initial value which is known, and the charges of the detectors are all transferred to capacitor C INT r, the second electrode of capacitor C INT is then at a potential representative of the charges coming from the detector, and this potential is identical to that of output OUT.
- the second so electrode of capacitor C INT is connected to an additional capacitor also called memory capacitor C M .
- the second electrode of capacitor C INT is connected to the first electrode of a memory capacitor C M .
- the second electrode of memory capacitor C M is connected to a second reference voltage source, here voltage V REF .
- the second reference voltage source delivers a fixed potential.
- memory capacitor C M so as to store the voltage applied by circuit 6 when the latter charges capacitor C INT and to keep this voltage on the second electrode of capacitor C INT .
- preservation of this data can be achieved by placing switch T 4 in the open state and for example by shutting circuit 6 down.
- the voltage present on the second electrode of capacitor C INT can be maintained for a longer time and in more precise manner thus enabling the potential of node N to be stabilised thereby reducing the potential change during the 16 acquisition period.
- the charges stored on capacitor C M are not necessarily representative of the electric charges generated by the photodetector.
- Charging of the second electrode of capacitor C INT means that the first electrode of capacitor C M is also charged. In this way, the voltage present on the second electrode of capacitor C INT can be maintained for a longer time.
- circuit 6 When circuit 6 has transferred the electric charges to capacitor C INT , the so second terminal of capacitor C INT is connected to the output of the detection circuit so as to deliver a signal representative of the optic signal received.
- the output of the detection circuit can be connected to an analysis circuit (not shown).
- the target value for node N corresponds to the value of the potential of node N when photodetector 1 is in the first state.
- voltage Vamp applied on the positive input of operational amplifier 8 is equal to voltage Vreset shifted by the value of the threshold voltage of transistor T 2 when this transistor is in follower mode.
- circuit 6 is configured so that the voltage applied on the second electrode of capacitor C INT resets integration node N to voltage Vreset as bias circuit 5 would do on initialisation of photodetector 1 .
- the detection circuit can perform continuous transfer of the charges generated by photodetector 1 , it is particularly advantageous to perform transfer of the electric charges in periodic manner, i.e. with alternations of transfer phases and accumulation phases.
- the circuit advantageously comprises a switch T 3 , advantageously a switch T 3 which is connected between the output of measurement circuit 7 of the potential of integration node N, formed here by transistor T 2 , and the input of transfer circuit 6 .
- switch T 3 more particularly connects the output of transistor T 2 to the first input of amplifier 8 .
- the acquisition period can be broken down into at least two distinct phases.
- a first phase also called integration phase
- the optic signal received by the photodetector generates electric charges which are stored in capacitor C PD and in capacitor C INT .
- switches T 3 and T 4 are in off state, i.e. open.
- the potential of integration node N changes progressively as the electric charges are stored.
- switches T 3 and T 4 are in on state, i.e. closed.
- the potential of integration node N is measured and a voltage is applied on the second electrode of capacitor C INT so that the potential of integration node N is for example equal to the target value.
- photodetector 1 is in a so floating state and generates electric charges according to the optic signal received.
- switches T 3 and T 4 can be switched simultaneously by receiving the same signal on their control electrode. This exemplary case is illustrated in FIG. 3 where switches T 3 and T 4 receive the same signal SEL Rn . It is also possible to provide for switches T 3 and T 4 to receive different signals, the independent and appropriate commands of T 3 and T 4 for example reducing the disturbances on integration node N when switching takes place. Transistor T 4 can be actuated in logic manner between the on and off states. However, it is particularly advantageous to define at least two on states, one of which limits the quantity of current able to flow through the transistor. This precaution prevents the occurrence of too abrupt transitions of electric charges which have the effect of impairing the integrity of the signal.
- Shifting of the charges enables integration node N to be reset to an identical or substantially identical bias level to that of the beginning of the acquisition period, which enables the photodetector to be reset to an identical or almost identical bias state to that of the beginning of the acquisition period.
- capacitor C INT As the transfer cycles are performed, the number of electric charges stored in capacitor C INT progressively increases.
- the voltage present on the second electrode of capacitor C INT at the end of the second period is representative of the total number of electric charges generated by the photodetector during the acquisition period.
- FIG. 3 illustrates a detection circuit with a single photodetector 1 .
- the detection matrix comprises a plurality of detection circuits as presented in the foregoing.
- the detection circuits are organised in rows and columns.
- bias circuits 5 of the detection circuits it is particularly advantageous to provide for bias circuits 5 of the detection circuits to receive the same first synchronisation signal (RSEL RN ). In this way, the first periods and the second periods are synchronised for the detection matrix.
- Bias circuits 5 of a line or column of detection circuits are connected to a control circuit A configured to perform simultaneous switching between the first period and the second period.
- the detection matrix is formed by a plurality of detection circuits which are organised with one or more repetition pitches in one or two organisation directions, for example those of the columns and rows.
- the detection matrix is divided into pixels formed by the detectors associated with bias circuit 5 , integration capacitor C INT and measurement circuit 7 .
- the pixels are organised with one or more repetition pitches in one or two organisatlon directions, for example those of the columns and rows.
- the detection matrix is surrounded by an area devoid of detectors.
- This area devoid of detectors presents a width at least equal to the width of a pixel, preferably a width at least equal to two pixels.
- the area devoid of detectors is in the form of a ring having a width at least equal to a repetition pitch, preferably at least equal to two repetition pitches.
- circuit 6 is removed to a location outside the photodetector matrix, which releases the volume occupied by this function on the area that is most sensitive in terms of available surface, thereby enabling the compactness of the photodetector matrix to be increased. Furthermore, this enables the major source of stray photon emission to be moved away from the photodetector matrix thereby improving the integrity of the optic signal received.
- the photodetector matrix is not provided with a transfer circuit 6 . Transfer circuit 6 or at least the amplifier 8 of transfer circuit 6 is separated from the nearest photodetector by a distance at least equal to a repetition pitch and preferably to at least two repetition pitches.
- Transfer circuit 6 is removed to a location outside the detection matrix so as to reduce or even eliminate the disturbances linked to the operation of transfer circuit 6 and more particularly to the operation of amplifier 8 . This shifting of the transfer circuit enables the noise level in the detection circuit to be reduced.
- circuit 6 is shared between Np photodetectors, which enables the space occupied by this function in the detection matrix to be divided by Np thereby increasing the compactness.
- electric charge transfer circuit 6 can be common to several detection circuits of a row or of a column.
- FIG. 4 illustrates sharing for a column.
- the circuit advantageously comprises a switch T 4 which is connected between the second electrode of integration capacitor C INT and transfer circuit 6 .
- the control circuit and transfer circuit 6 are configured to sequentially perform transfer of the charges from integration nodes N of said detection circuits during the second period. In this way, the electric charges present in the integration nodes are transferred in sequential manner during the second period.
- each detection device comprises a transistor T 3 and a transistor T 4 which are turned on or off depending on whether the detection device is in the transfer phase or in the integration phase of the acquisition period, i.e. the second period.
- the column is formed by n detection devices representative of n rows of the matrix.
- switches T 3 and T 4 of a first detection device When switches T 3 and T 4 of a first detection device are in on state, the other switches T 3 and T 4 are in off state. In this way, each of the integration nodes N of the column can be analysed on its own without any risk of disturbance of the other integration nodes of the column.
- Signal SELRn can therefore be an activation signal of switches T 3 and T 4 of the device of rank n of the column or more generally of all the switches T 3 and T 4 of rank n of the detection matrix.
- a single connection is used to connect the so output of amplifier 8 with all the switches T 4 of one and the same column. Activating the different switches T 4 sequentially makes it possible to vary the potential of one node N at a time.
- This detection device architecture is particularly advantageous in the field of low flux signal detection and more particularly in the field of astronomy where the collected signals are very weak.
- the detection device enables better results to be obtained than the two detection architectures known from the prior art, SFD and CTIA.
- the photodetector can be a photodetector configured to detect a visible or infrared radiation. In the infrared range, the photodetector can be configured to detect at least one spectral band from the VLWIR, LWIR, MWIR and SWIR bands.
- the detection device In the infrared range and more particularly in the LWIR band, the detection device enables the integrity of the signal to be kept over a larger operating range in comparison with architectures of the prior art.
- the detection circuit is presented in conjunction with a photodetector, it is also of great interest for all detectors which deliver an electric signal as a function of an external stimulus, for example a pressure sensor.
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Abstract
Description
-
- a detector provided with a stray capacitor and configured to deliver electric charges according to an observed phenomenon,
- a bias circuit configured to bias the detector during a first period and to leave a first terminal of the detector at a floating potential during a second period.
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- a first capacitor having a first terminal connected to the first terminal of the detector to form an integration node with the stray capacitor, the integration node being at a target value during the first period and changing during the second period,
- a transfer circuit of the electric charges from the stray capacitor to the first capacitor, the electric charge transfer circuit being configured to bias a second electrode of the first capacitor so as to shift the potential of the retention node to the target value,
- an output terminal delivering a voltage representative of the potential present on the second terminal of the first capacitor.
Claims (18)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1661322A FR3059189B1 (en) | 2016-11-21 | 2016-11-21 | DETECTION CIRCUIT WITH LOW FLOW AND LOW NOISE. |
FR1661322 | 2016-11-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20180143072A1 US20180143072A1 (en) | 2018-05-24 |
US10458842B2 true US10458842B2 (en) | 2019-10-29 |
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EP (1) | EP3324610B1 (en) |
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DE102018130006A1 (en) * | 2018-11-27 | 2020-05-28 | Instrument Systems Optische Messtechnik Gmbh | Device and method for measuring semiconductor-based light sources |
CN111337905B (en) * | 2020-03-20 | 2021-12-28 | 东南大学 | Dual-mode focal plane pixel-level circuit based on CTIA and implementation method |
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EP2600125A1 (en) | 2011-11-29 | 2013-06-05 | Société Française de Détecteurs Infrarouges - SOFRADIR | Radiation-detection device with improved illumination range |
WO2013083889A1 (en) | 2011-12-08 | 2013-06-13 | Societe Francaise De Detecteurs Infrarouges - Sofradir | Device for detecting pulsed electromagnetic radiation |
US8803064B2 (en) * | 2009-02-03 | 2014-08-12 | Hamamatsu Photonics K.K. | Signal processing device, including charge injection circuit, and photodetection device |
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US8803064B2 (en) * | 2009-02-03 | 2014-08-12 | Hamamatsu Photonics K.K. | Signal processing device, including charge injection circuit, and photodetection device |
EP2600125A1 (en) | 2011-11-29 | 2013-06-05 | Société Française de Détecteurs Infrarouges - SOFRADIR | Radiation-detection device with improved illumination range |
WO2013083889A1 (en) | 2011-12-08 | 2013-06-13 | Societe Francaise De Detecteurs Infrarouges - Sofradir | Device for detecting pulsed electromagnetic radiation |
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FR3059189B1 (en) | 2018-12-07 |
EP3324610B1 (en) | 2019-09-11 |
US20180143072A1 (en) | 2018-05-24 |
IL255798A0 (en) | 2017-12-31 |
IL255798B (en) | 2021-01-31 |
FR3059189A1 (en) | 2018-05-25 |
EP3324610A1 (en) | 2018-05-23 |
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