US10339238B2 - Method and apparatus for performing register retiming in the presence of timing analysis exceptions - Google Patents
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Abstract
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.
Description
This application is a continuation of and claims priority and benefit to U.S. Pat. No. 9,710,591 filed on Feb. 20, 2015, entitled, “Method and Apparatus for Performing Register Retiming in the Presence of Timing Analysis Exceptions”.
Embodiments of the present invention relate to tools for designing systems on target devices. More specifically, embodiments of the present invention relate to a method and apparatus for performing register retiming in the presence of false path timing analysis exceptions.
Target devices such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and structured ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are design generation and integration, synthesis, placement, and routing of the system on the target device.
When addressing conventional timing closure, designers focus on the critical paths in a design. A critical path is a path from a register to another register, through combinational or routing elements, which fails or is close to failing a timing requirement. In an effort to close timing, a designer may examine the critical path and attempt to improve it by reducing an amount of combinational or routing delay along the path.
EDA tools may utilize register retiming algorithms in order to close timing. Register retiming is a synchronous circuit transformation that is used to improve the speed-performance of a synchronous circuit. Register retiming involves moving register across combinational or routing circuit elements in order to reduce the length of timing-critical paths. Register retiming may also involve inserting pipelined registers along timing-critical paths in order to split combinational logic into multiple cycles which leads to an increase of slack in timing-critical paths. This allows for an increase in clock rate, and/or an increase in throughput. The combinational structure remains unchanged and the observable behavior of the circuit is identical to the original circuit.
Designers may use timing analysis exceptions such as false paths, multicycle, and minimum and maximum delay constraints for portions of a signal path. These timing analysis exceptions, however, can limit optimizations associated with register retiming. Traditional register retiming techniques cannot move registers across a timing analysis exception. As a result, the timing analysis exception may limit the performance of the system. In addition, traditional register retiming techniques fail to utilize the arbitrary delay between two registers when a false path timing analysis exception is present.
Embodiments of the present invention enable a system designer unit to move registers across a timing analysis exception to improve circuit performance. From the specification of the timing analysis exception, components (nodes) affected by the timing analysis exceptions are represented as constraints. The constraints are enforced to preserve the legality of the timing analysis exceptions in the presence of register retiming. This allows register retiming to be performed in the presence of timing analysis exceptions, while still preserving the exception. In addition, other embodiments of the present invention may utilize the properties of false paths and add pipeline registers at the boundaries of a false path timing analysis exception to improve circuit performance.
According to an embodiment of the present invention, a method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components impacted by the timing exception is identified. Register retiming is performed where a register is moved from a first position on the signal path on one side of the area to a second position on the signal path on another side of the area. According to an aspect of the present invention, the timing exception for the portion of the signal path includes a timing condition permitted that is different from a default timing constraint applied to other portions of the signal paths or to other signal paths. According to another aspect of the present invention, the timing exception may be a multicycle that identifies how a default timing constraint may be applied differently to the portion of the signal path, a false path that excludes a default timing constraint from being applied to the portion of the signal path, or a minimum delay and maximum delay for a signal on the portion of the signal path. The timing exception may be provided by a user after timing analysis is performed on the system or provided during design entry prior to synthesis, placement, and routing of the system.
According to an embodiment of the present invention, a method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components impacted by the timing exception is identified. The timing exception may be, for example, a false path. Register retiming is performed where pipeline registers are added at boundaries of the area. The boundaries of the area may be the location of the source and destination keepers of a false path. According to an aspect of the present invention, the pipeline registers are added in response to an assignment set by a user. The assignment set by the user may specify which signal paths affected by a false path should have pipeline registers added. According to another aspect of the present invention, a report is generated to a user that identifies a number and location of the pipeline registers added.
The features and advantages of embodiments of the present invention are illustrated by way of example and are not intended to limit the scope of the embodiments of the present invention to the particular embodiments shown.
In the following description, for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that specific details in the description may not be required to practice the embodiments of the present invention. In other instances, well-known circuits, devices, procedures, and programs are shown in block diagram form to avoid obscuring embodiments of the present invention unnecessarily.
At 101, a design for a system is entered. The specification for the system may be provided though a design entry tool. The specification may describe components and interconnections in the system. According to an embodiment of the present invention, timing exceptions are included with the specification for the system. The timing exceptions may be applied to a portion of a signal path where the timing exception for the portion of the signal path is different from a default timing constraint applied to other portions of the signal path.
At 102, the system is synthesized. Synthesis includes generating a logic design of the system to be implemented by the target device. According to an embodiment of the present invention, synthesis generates an optimized logical representation of the system from an HDL design definition. The optimized logical representation of the system may include a representation that has a minimized number of functional blocks such as logic gates, logic elements, and registers required for the system. Synthesis also includes mapping the optimized logical representation. Mapping includes determining how to implement logic gates and logic elements in the optimized logic representation with the types or categories of resources available on the target device. The resources available on the target device may be referred to as “cells” or “components” and may include logic-array blocks, registers, memories, digital signal processing blocks, input/output elements, and other components. According to an embodiment of the present invention, a netlist is generated from mapping. This netlist may be an optimized technology-mapped netlist generated from the HDL.
At 103, the system is placed. According to an embodiment of the present invention, placement involves placing the technology-mapped logical system design on the target device. Placement includes fitting the system on the target device by determining which specific resources on the target device are to be assigned to and implemented by the technology-mapped netlist determined during synthesis. Placement may include clustering which involves grouping logic elements together to form the logic clusters present on the target device.
At 104, the placed design is routed. During routing, routing resources on the target device are allocated to provide interconnections between logic gates, logic elements, and other components on the target device. Routability optimization may also be performed on the placed logic design. According to an embodiment of the present invention, the goal of routability optimization is to reduce the amount of wiring used to connect components in the placed logic design. Routability optimization may include performing fanout splitting, logic duplication, logical rewiring, or other procedures. It should be appreciated that one or more of the procedures may be performed on the placed logic design.
At 105, timing analysis is performed on the design of the system generated. According to an embodiment of the present invention, the timing analysis determines whether timing constraints of the system are satisfied. The timing analysis may utilize approximations depending on when it is performed. According to an embodiment of the present invention, timing analysis establishes a delay for each path in the system as well as the slack for each path in the system. Slack may be defined to be the amount of delay that can be added to a path before it becomes critical or required time for signal arrival minus actual time of signal arrival.
At 106, if it is determined that the design for the system meets timing constraints, control proceeds to 107. If it is determined that the design for the system does not meet timing constraints, control proceeds to 108.
At 107, control terminates the procedure.
At 108 timing exceptions are analyzed and processed. According to an embodiment of the present invention, areas on the target device that include components affected by timing exceptions for portions of signal paths are identified. The areas may also be referred to as “clouds”. Unallocated registers on the target device residing in the clouds are identified as registers that may not be utilized for register retiming. Constraints may be utilized to prevent register retiming from utilizing the registers in the clouds.
At 109, register retiming is performed on the system. According to an embodiment of the present invention, register retiming may involve moving registers across combinational or routing circuit elements to reduce the length of timing-critical or near critical paths as determined by the timing analysis procedure 106. In addition, register retiming may also involve adding pipelined registers on a path affected by a false path timing exception at the boundaries of the area(s) identified at 108. Register retiming is performed respecting the constraints established at 108. It should be appreciated that register retiming may also be performed respecting other computed constraints. Register retiming may operate in response to settings set by the user which specify when to move registers, which registers to move, and when and where to add pipelined registers.
At 110, a report is generated that identifies the results of register retiming to a user. According to an embodiment of the present invention, the report may identify registers that have moved over an exception and a critical chain that has been retimed. The report may also identify a number and location of the pipeline registers added. Information from the report may be used by the user to modify settings for register retiming during a next iteration.
Control returns to timing analysis at 105 to determine whether timing is satisfied. Register retiming may be further performed if timing is not satisfied by repeating procedures 108-110. After a predetermined number of iterations, control may proceed to 107. It should be appreciated that in addition to entering timing exceptions during design entry 101 that timing exceptions may also be entered after timing analysis 105.
At 202, areas on the target device affected by the timing exceptions are identified. According to an embodiment of the present invention, a first component at a beginning of a timing exception is identified. A second component at an end of the timing exception is identified. An area affected by a timing exception may be defined to include the first component, the second component, and all components along a portion of a path between the first and second components.
At 203, constraints are applied to both allocated and unallocated registers in the area for the purpose of register retiming a signal along the path. The constraints enforce the preservation and legality of the exception when register retiming is performed. When register retiming is attempted for a particular signal path, the unallocated registers in the identified area would be made unavailable. This results in a selection of unallocated registers outside the identified area for register retiming. This has the effect of moving a register across the area during register retiming.
Together, registers 311-313, combinational logic 320, and registers 331-332, define an area or cloud 340 on the target device where register retiming may not be performed. This prevents registers 311-313 and 331-332 from being retimed and effectually moved outside the area. It should be appreciated that the target device may include one or more unused or unallocated registers (not shown) in area 340. Any unused or unallocated registers within the area 340 on the target device may not be used for register retiming. Allowing registers in area 340 that have different timing requirements to move may lead a register retiming procedure to converge on a lower maximum frequency requirement for the system.
Referring to FIG. 3B , registers 301-303 are allowed to be retimed by moving the registers 301-303 forward over the area 340 to unallocated registers 351-352. This allows the area 340 with components affected by the timing exception and timing constraints between registers 311-313 and 331-332 to be preserved.
Referring to FIG. 4B , registers 451-452 are allowed to be retimed by moving the registers 451-452 backwards over the area 440 to unallocated registers 401-402. This allows the area 440 with components affected by the timing exception and timing constraints between registers 411-413 and 431-432 to be preserved.
At 602, from the superset of source components, one or more areas that include components affected by the timing exception are identified.
At 603, it is determined whether additional exceptions exist. If an additional exception which has yet to be analyzed exists, control returns to 601 and performs the procedure with the new exception. If an additional exception which has yet to be analyzed does not exist, control proceeds to 604.
At 604, all the areas identified at 602 for all exceptions are merged. According to an embodiment of the present invention, merging involves combining two areas when the areas share a common component.
At 702, the superset of source components is designated to be set S, and is initialized to be an empty set. The index j is initialized to be zero.
At 703, control determines whether index j is less than the number of visited components from 701. If index j is not less than the number of visited components, control terminates the method at 704. If index j is less than the number of visited components, control proceeds to 705.
At 705, the predecessors of the jth component visited from the depth first search is added to a set of predecessors, P. The index k is set to zero.
At 706, it is determined whether the index k is less than the size of P. If the index k is not less than the size of the set of predecessors, P, control proceeds to 710. If the index k is less than the size of the set of predecessors, P, control proceeds to 707.
At 707, it is determined whether Pk is a member of any member of S. If Pk is a member of any member of S, control proceeds to 708. If Pk is not a member of any member of S, control proceeds to 709.
At 708, the index k is incremented by one. Control returns to 706.
At 709, the superset of source components, S, is updated by taking the union of S with Pk. Control returns to 708.
At 710, a set Q is created which takes a union of elements in subsets in set S which have an element in set P. The set S is then updated by removing any subset which includes a member of set P. The set S is then further updated by taking the union of S with the set Q.
At 711, the index j is incremented by one. Control returns to 703.
At 802, a depth first search (DFS) in a forward direction starting from each component identified at procedure 801 is performed. The DFS is stopped on any path when a keeper is encountered. The set of reached keepers may be designated as D′.
At 803, the set of reached keepers, D′, is updated by including only components common with exception destination keepers.
At 804, all components reachable in a backward direction from the updated set of reached keepers, D′, and in a forward direction from the common set of elements, S′, are identified as being in a set of components affected by the timing exception.
At 805 the set of components identified at 804 are added to any previous set of components identified.
At 806, it is determined whether another set of superset of source components exists. If it is determined that another set of superset of source components exists, control returns to 801 and performs the procedure on the new set from the superset of source components. If it is determined that another set from the superset of source components do not exist, control terminates the procedure at 807.
According to an embodiment of the present invention, the procedures illustrated in FIGS. 6-8 may be implemented using the pseudo code listed below.
For exception specification i
-
- In the netlist, perform depth first search back from the set of destination keepers stopping on each search path when a keeper is encountered. While searching, for each visited node v do:
- i. P={set of predecessors of v}
- ii. For each p in P
- If p is not a member of any member in S
- S=S∪{{p}}
- iii. Q=∪ of all members of S that contain any member of P
- iv. Remove from S any member that contains any member of P
- v. S=S∪{Q}
For each s in S
-
- vi. S′=∩ of S and source keepers of exception specification
- vii. In the netlist, perform depth first search forward from S′ stopping on each search path when a keeper is encountered. Call D′ the set of reached keepers.
- viii. D′=D′∩ with destination keepers of exception specification
- ix. Cloud=set of all nodes reachable backwards from D′ and forward from S′
- x. Add cloud to C_i
Merge clouds in all C_is
Referring back to FIG. 7 , a superset of source components that represent source keepers of potential clouds is identified. For the first exception, at 701, a depth first search is performed in a backward direction starting from each of the exception destination keepers {f, c, y}. For DFS1=f, the depth first search visits and stops at the component a.
At 705, the first component visited from the depth first search is added to a set of predecessors, P. P={a}.
At 709, the superset of source components, S, is updated by taking the union of S with Pk. S={{a}}.
At 710, a set Q is created which takes a union of elements in subsets in set S which have an element in set P. The set S is then updated by removing any subset which includes a member of set P. The set S is then further updated by taking the union of S with the set Q. S={{a}}.
At 711, j is incremented by one and returns to 703.
At 705, the second component visited from the depth first search is added to a set of predecessors, P. P={b}.
At 709, the superset of source components, S, is updated by taking the union of S with Pk. S={{a}, {b}}.
At 710, a set Q is created which takes a union of elements in subsets in set S which have an element in set P. The set S is then updated by removing any subset which includes a member of set P. The set S is then further updated by taking the union of S with the set Q. S={{a}, {b}}.
At 711, j is incremented by one and returns to 703.
At 705, the third component visited from the depth first search is added to a set of predecessors, P. P={x}.
At 709, the superset of source components, S, is updated by taking the union of S with Pk. S={{a}, {b}, {x}}.
At 710, a set Q is created which takes a union of elements in subsets in set S which have an element in set P. The set S is then updated by removing any subset which includes a member of set P. The set S is then further updated by taking the union of S with the set Q. S={{a}, {b}, {x}}.
At 711, j is incremented by one and returns to 703.
At 703, since j is not less than the number of visited components, control terminates the method at 704.
Referring back to FIG. 8 , a set of components affected by the first timing exception is identified. At 801, components common to a first set from the superset of source components, S, and exception source keepers are identified. The first set from the superset of source components is {a}. The exception source keepers are {c, b, x}. The common set of elements designated S′ is an empty set.
At 802, a depth first search in a forward direction starting from each component identified at procedure 801 is performed. The DFS is stopped on any path when a keeper is encountered. The set of reached keepers designated as D′ is an empty set.
At 803, the set of reached keepers, D′, is updated by including only components common with exception destination keepers. The updated set is an empty set.
At 804, all components reachable in a backward direction from the updated set of reached keepers, D′, and in a forward direction from the common set of elements, S′, are identified as being in a set of components affected by the timing exception. For this iteration, the set is an empty set.
At 806, control determines a second set from the superset of source components exists. Control returns to 801.
At 801, components common to the second set from the superset of source components and exception source keepers are identified. The second set from the superset of source components is {b}. The exception source keepers are {e, b, x}. The common set of elements designated S′ is {b}.
At 802, a depth first search in a forward direction starting from each component identified at procedure 801 is performed. The DFS is stopped on any path when a keeper is encountered. The set of reached keepers designated as D′ is {c}.
At 803, the set of reached keepers, D′, is updated by including only components common with exception destination keepers. The updated set is {c}.
At 804, all components reachable in a backward direction from the updated set of reached keepers, D′, and in a forward direction from the common set of elements, S′, are identified as being in a set of components affected by the timing exception. For this iteration, the set is {b, c}.
At 805, the set of components identified at 804 is the first non-empty set of components identified and is added to sets of components identified.
At 806, control determines a third set from the superset of source components exists. Control returns to 801.
At 801, components common to the third set from the superset of source components and exception source keepers are identified. The third set from the superset of source components is {x}. The exception source keepers are {e, b, x}. The common set of elements designated S′ is {x}.
At 802, a depth first search in a forward direction starting from each component identified at procedure 801 is performed. The DFS is stopped on any path when a keeper is encountered. The set of reached keepers designated as D′ is {y}.
At 803, the set of reached keepers, D′, is updated by including only components common with exception destination keepers. The updated set is {y}.
At 804, all components reachable in a backward direction from the updated set of reached keepers, D′, and in a forward direction from the common set of elements, S′, are identified as being in a set of components affected by the timing exception. For this iteration, the set is {x, y}.
At 805, the set of components identified at 804 is added to set {b, c} identified in the second iteration.
At 806, control determines that no additional set from the superset of source components exist and terminates the procedure at 807.
Referring back to FIG. 7 , a superset of source components that represent source keepers of potential clouds is identified. For the second exception, at 701, a depth first search is performed in a backward direction starting from each of the exception destination keepers {d}. For DFS1=d, the depth first search visits and stops at the component a.
At 705, the first component visited from the depth first search is added to a set of predecessors, P. P={c}.
At 709, the superset of source components, S, is updated by taking the union of S with Pk. S={{c}}.
At 710, a set Q is created which takes a union of elements in subsets in set S which have an element in set P. The set S is then updated by removing any subset which includes a member of set P. The set S is then further updated by taking the union of S with the set Q. S={{c}}.
At 711, j is incremented by one and returns to 703.
At 703, since j is not less than the number of visited components, control terminates the method at 704.
Referring back to FIG. 8 , a set of components affected by the second timing exception is identified. At 801, components common to a set from the superset of source components, S, and exception source keepers is identified. The set from the superset of source components is {c}. The exception source keepers is {c}. The common set of elements designated S′ is {c}.
At 802, a depth first search in a forward direction starting from each component identified at procedure 801 is performed. The DFS is stopped on any path when a keeper is encountered. The set of reached keepers designated as D′ is {d}.
At 803, the set of reached keepers, D′, is updated by including only components common with exception destination keepers. The updated set is {d}.
At 804, all components reachable in a backward direction from the updated set of reached keepers, D′, and in a forward direction from the common set of elements, S′, are identified as being in a set of components affected by the timing exception. For this iteration, the set is {c, d}.
At 806, control determines that no additional set from the superset of source components exist and terminates the procedure at 807.
According to an embodiment of the present invention, the sets of affected components from the first exception {b, c} and {x, y} may be merged with the set of affected components from the second exception {c, d}. This results in sets {b, c, d} and {x, y}.
At 1002, the identified registers at 1002 are pushed backwards. According to an embodiment of the present invention, a push backward involves moving the register backwards on the near-critical path to an input of a component. For the backward push to occur, a register needs to be present on each fanout of the component.
At 1003, it is determined whether pushing any of the registers backwards at 1002 causes a violation of a constraint. According to an embodiment of the present invention, constraints may include user-defined timing constraints. Constraints may include area constraints for the system such as global constraints on the maximum area increase allowed and constraints that ensure that registers are created evenly across the system. Constraints may include architectural constraints that define rules for handling carry chains and various restrictions on secondary signals such as control signals. Constraints may include implicit legality constraints, such as constraints for moving registers feeding asynchronous lines, to ensure that the system functions correctly after retiming is performed. Constraints may include prohibitions to cross time boundaries. Constraints may include user defined constraints such as constraints that prohibit the placement of components on designated sections of the target device. Constraints may also include the constraints identified at procedure 108 in FIG. 1 that prevent register retiming from utilizing the registers in identified areas affected by a timing exception. It should be appreciated that other types of constraints may also be defined and included for the purpose of determination of violation at 1003. If it is determined that pushing any of the registers backwards causes a violation of a constraint, control proceeds to 1004. If it is determined that pushing any of the registers backwards does not cause a violation of a constraint, control proceeds to 1005.
At 1004, backward pushes that result in violations are undone. Control proceeds to 1005.
At 1005, timing analysis is performed. Timing analysis establishes the length for each path in the system as well as the slack for each path in the system.
At 1006, it is determined whether the timing of the system has improved. Determining whether timing of the system has improved may be achieved by comparing the slack values of near-critical paths in the recently retimed system design with a previous system design. If the timing of the system has improved, control proceeds to 1007. If the timing of the system has not improved, control proceeds to 1008.
At 1007, the current changes to the system are saved. The current changes to the system include the changes made at 1002.
At 1008, it is determined whether a threshold number of iterations of 1001-1007 has been performed. If a threshold number of iterations of 1001-1007 has not been performed, control returns to 1001. If a threshold number of iterations of 1001-1007 has been performed, control proceeds to 1009.
At 1009, the current changes saved at 1007 are designated as the current design for the system.
At 1010, registers with outputs coupled to near-critical paths are identified. According to an embodiment of the present invention, a near-critical path is a path in the system with a slack value below a threshold value.
At 1011, the identified registers at 1010 are pushed forward. According to an embodiment of the present invention, a push forward involves moving the register forward on the near-critical path to an output of a component. For the forward push to occur, a register needs to be present on each input of the component.
At 1012 it is determined whether pushing any of the registers forwards at 1011 causes a violation of a constraint. The constraints described with reference to 1003 may be used at 1012. If it is determined that pushing any of the registers forward causes a violation of a constraint, control proceeds to 1013. If it is determined that pushing any of the registers forward does not cause a violation of a constraint, control proceeds to 1014.
At 1013, forward pushes that result in violations are undone. Control proceeds to 1014.
At 1014, timing analysis is performed. Timing analysis establishes the length for each path in the system as well as the slack for each path in the system.
At 1015, it is determined whether the timing of the system has improved. Determining whether timing of the system has improved may be achieved by comparing the slack values of near-critical paths in the recently retimed system design with a previous system design. If the timing of the system has improved, control proceeds to 1016. If the timing of the system has not improved, control proceeds to 1017.
At 1016, the current changes to the system are saved. The current changes to the system include the changes made at 1011.
At 1017, it is determined whether a threshold number of iterations of 1010-1016 has been performed. If a threshold number of iterations of 1010-1016 has not been performed, control returns to 1010. If a threshold number of iterations of 1010-1016 has been performed, control proceeds to 1018.
At 1018, the current changes saved at 1016 are designated as the current design for the system.
At 1202, areas on the target device affected by the timing exceptions are identified. According to an embodiment of the present invention, a first component at a beginning of a timing exception is identified. A second component at an end of the timing exception is identified. An area affected by a timing exception may be defined to include the first component, the second component, and all components along a portion of a path between the first and second components.
At 1203, signal paths which to add pipelined registers are identified. According to an embodiment of the present invention, the identification may be achieved by presenting a user with the identity of signal paths subject to false path exceptions and prompting the user to select signal paths which to add pipelined registers. According to an embodiment of the present invention, a user may specify that all or none of the signal paths impacted by a false path exception should have pipelined registers inserted. The user may also identify specific signal paths impacted by false path exceptions which should have pipelined registers inserted.
At 1204, constraints are applied to both allocated and unallocated registers in the area for the purpose of register retiming a signal along the path. The constraints enforce the preservation and legality of the exception when register retiming is performed. When register retiming is attempted for a particular signal path, the unallocated registers in the identified area would be made unavailable. This results in a selection of unallocated registers outside the identified area for register retiming. As a result, registers at the boundaries of the area will be selected as pipelined registers to be added to the signal path.
According to an embodiment of the present invention, the procedures illustrated in FIGS. 1-2, 6-8, 10, and 12 may be performed by an EDA tool executed on a first computer system. A data file may be generated and transmitted to a second computer system to allow the design of the system to be further processed. Alternatively, the data file may be transmitted to a second computer system which may be used to program the target device according to the system design. It should be appreciated that the design of the system may also be output in other forms such as on a display device or other medium. By programming the target with the data file, components on the target device are physically transformed to implement the system.
When the timing exception that impacts the portion of the signal is a false path timing exception, pipelined registers may be added to the signal path without adversely impacting timing on the signal path. As such, by adding the pipelined registers on the signal path, combinational logic may be split into multiple cycles which leads to an increase of slack in timing-critical paths. This allows for an increase in clock rates, and/or an increase in throughput.
Together, registers 1311-1313, combinational logic 1320, and registers 1331-1332, define an area or cloud 1340 on the target device where register retiming may not be performed. This prevents registers 1311-1313 and 1331-1332 from being retimed and effectually moved outside the area. It should be appreciated that the target device may include one or more unused or unallocated registers (not shown) in area 1340. Any unused or unallocated registers within the area 1340 on the target device may not be used for register retiming by being added to the signal paths traversing the area 1340. Allowing registers in area 1340 that have different timing requirements to move or by adding registers to signal paths traversing area 1340 may lead a register retiming procedure to converge on a lower maximum frequency requirement for the system.
Referring to FIG. 13B , registers 1361-1363 are inserted along the signal paths at the boundaries of the area 1340 defined by registers 1311-1313 (exception source keepers). Registers 1371-1372 are inserted along the signal paths at the boundaries of the area 1340 defined by registers 1331-1332 (exception destination keepers). The registers 1361-1363 and 1371-1372 generate pipeline stages at the false path timing exception boundaries. This allows the area 1340 with components affected by the false path timing exception between registers 1311-1313 and 1331-1332 to be preserved.
Referring to FIG. 14B , registers 1481-1483 are inserted along the signal paths at the boundaries of the area 1450 defined by registers 1401-1403 (exception source keepers). Registers 1491-1493 are inserted along the signal paths at the boundaries of the area 1450 defined by registers 1441-1442 (exception destination keepers). The registers 1481-1483 and 1491-1493 generate pipeline stages at the false path timing exception boundaries. This allows the area 1450 with components affected by the false path timing exception between registers 1401-1403 and 1441-1443 to be preserved.
According to an embodiment of the present invention, the properties of false paths timing exceptions are utilized during register retiming. Pipelined registers are added at source and/or destination keepers of a false path to improve circuit performance. Nodes in the circuit impacted by the false path are represented with constraints which enforce the preservation and legality of the false path in the presence of added pipeline registers. This allows for any number of pipeline registers to be added in order to achieve a desired solution while preserving the false path timing exception.
Source and destination keepers may be identified from false path timing exception specification. A netlist traversal may be performed to identify false path clouds which include a set of nodes in the netlist affected by each false path. False path timing exception clouds that share nodes may be merged to generate a set of non-overlapping exception clouds. For each false path timing exception, constraints are added to preserve timing between source and destination keepers.
A network controller 1540 is coupled to the bus 1501. The network controller 1540 may link the computer system 1500 to a network of computers (not shown) and supports communication among the machines. A display device controller 1550 is coupled to the bus 1501. The display device controller 1550 allows coupling of a display device (not shown) to the computer system 1500 and acts as an interface between the display device and the computer system 1500. An input interface 1560 is coupled to the bus 1501. The input interface 1560 allows coupling of an input device (not shown) to the computer system 1500 and transmits data signals from the input device to the computer system 1500.
A system designer 1521 may reside in the memory 1520 and be executed by the processor 1510. According to an embodiment of the present invention, the system designer 1121 analyzes and processes timing exceptions. According to an embodiment of the present invention, areas on a target device that include components affected by timing exceptions for portions of signal paths are identified. The areas may also be referred to as “clouds”. Unallocated registers on the target device residing in the identified areas are identified as registers that may not be utilized for register retiming. Constraints may be utilized to prevent register retiming from utilizing the registers in the identified areas. The system designer 1521 may also perform register retiming by moving identified registers across combinational or routing circuit elements to reduce the length of timing-critical or near critical paths as determined by timing analysis. According to another embodiment of the present invention, the system designer 1521 may also perform register retiming by adding pipeline registers at boundaries of the area. Register retiming is performed respecting the constraints established.
The system designer 1600 includes a designer manager 1610. The system designer manager 1610 is connected to and transmits data between the other components of the system designer 1600. The system designer manager 1610 provides an interface that allows a user to input data into the system designer 1600 and that allows the system designer 1100 to output data to the user. According to an embodiment of the present invention, a design for the system along with timing exceptions may be input using the system designer manager 1610. The timing exceptions may be applied to a portion of a signal path where the timing exception for the portion of the signal path is different from a default timing constraint applied to other portions of the signal path. According to an embodiment of the present invention, the system designer manager 1610 may present one or more signal paths subject to a timing exception, such as a false path, to a user and receive one or more assignments from the user that indicates which of the signal paths to insert pipeline registers.
The system designer 1600 includes a synthesis unit 1615. The synthesis unit 1615 generates a logic design of the system to be implemented by the target device. According to an embodiment of the present invention, the synthesis unit 1615 generates an optimized logical representation of the system from the HDL design definition and maps the optimized logic design. According to an embodiment of the present invention, a netlist is generated from mapping. This netlist may be an optimized technology-mapped netlist generated from the HDL.
The system designer 1100 includes a placement unit 1620. According to an embodiment of the present invention, the placement unit 1620 places the mapped logical system design on the target device. Placement works on the technology-mapped netlist to produce a placement for each of the functional blocks. According to an embodiment of the present invention, placement unit 1620 fits the system on the target device by determining which resources on the logic design are to be used for specific logic elements, and other function blocks determined to implement the system as determined during synthesis. Placement may include clustering which involves grouping logic elements together to form the logic clusters present on the target device.
The system designer 1600 includes a routing unit 1625 which routes the placed design on the target device. The routing unit 1625 allocates routing resources on the target device to provide interconnections between logic gates, logic elements, and other components on the target device. The routing unit 1625 may also perform routability optimization on the placed logic design.
The system designer 1600 includes a timing analysis unit 1630 which performs timing analysis on the design of the system generated. According to an embodiment of the present invention, the timing analysis determines whether timing constraints of the system are satisfied. The timing analysis may utilize approximations depending on when it is performed.
The system designer 1630 includes a timing exception unit 1635. According to an embodiment of the present invention, the timing exception unit 1635 includes a timing exception identification unit 1636. The timing exception identification unit 1636 identifies timing exceptions for portions of signal paths in the system. The timing exception identified may include false path, multi-cycle, minimum/maximum delay and other exceptions. The timing exception unit 1635 includes an area identification unit 1637. The area identification unit 1637 identifies areas (clouds) on the target device that include components affected by timing exceptions for portions of signal paths. According to an embodiment of the present invention, the area identification unit 1637 may perform the procedures described with reference to FIGS. 6-8 . The timing exception unit 1635 includes a pipeline register unit 1638. The pipeline register unit 1638 identifies signal paths affected by a false path timing exception to insert pipeline registers. According to an embodiment of the present invention, the pipeline register unit 1638 identifies signal paths to insert pipeline registers in response to information received from the system designer manager 1610 obtained from the user. The timing exception unit 1635 includes a constraints unit 1639. The constraints unit 1639 applies constraints to unallocated registers in the areas identified to prevent the unallocated registers from being used for register retiming.
The system designer 1600 includes a register retiming unit 1640. According to an embodiment of the present invention, the register retiming unit 1640 moves identified registers across combinational circuit elements to reduce the length of timing-critical or near critical paths as determined by the timing analysis unit 1630. The register retiming unit 1640 may perform the procedures illustrated in FIG. 10 while honoring the constraints applied by the constraints unit 1639. According to another embodiment of the present invention, the register retiming unit 1640 may also insert registers at or outside of boundaries of areas affected by a false path timing exception.
The system designer 1600 includes a report generation unit 1650. The report generation unit 1650 generates a report that identifies the results of register retiming to a user. According to an embodiment of the present invention, the report may identify registers that have moved over an exception and a critical chain that has been retimed. The report may also identify a number and location of the pipeline registers added. Information from the report may be used by the user to modify settings for register retiming for a future iteration of register retiming.
It should be appreciated that embodiments of the present invention may be provided as a computer program product, or software, that may include a computer-readable or machine-readable medium having instructions. The instructions on the computer-readable or machine-readable medium may be used to program a computer system or other electronic device. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, and magneto-optical disks or other type of media/machine-readable medium suitable for storing electronic instructions. The techniques described herein are not limited to any particular software configuration. They may find applicability in any computing or processing environment. The terms “computer-readable medium” or “machine-readable medium” used herein shall include any medium that is capable of storing or encoding a sequence of instructions for execution by the computer and that cause the computer to perform any one of the methods described herein. Furthermore, it is common in the art to speak of software, in one form or another (e.g., program, procedure, process, application, module, unit, logic, and so on) as taking an action or causing a result. Such expressions are merely a shorthand way of stating that the execution of the software by a processing system causes the processor to perform an action to produce a result.
The device 1700 includes memory blocks. The memory blocks may be, for example, dual port random access memory (RAM) blocks that provide dedicated true dual-port, simple dual-port, or single port memory up to various bits wide at up to various frequencies. The memory blocks may be grouped into columns across the device in between selected LABs or located individually or in pairs within the device 1700. Columns of memory blocks are shown as 1721-1724.
The device 1700 includes digital signal processing (DSP) blocks. The DSP blocks may be used to implement multipliers of various configurations with add or subtract features. The DSP blocks include shift registers, multipliers, adders, and accumulators. The DSP blocks may be grouped into columns across the device 1700 and are shown as 1731.
The device 1700 includes a plurality of input/output elements (IOEs) 1740. Each IOE feeds an IO pin (not shown) on the device 1700. The IOEs 1740 are located at the end of LAB rows and columns around the periphery of the device 1700. Each IOE may include a bidirectional IO buffer and a plurality of registers for registering input, output, and output-enable signals.
The device 1700 may include routing resources such as LAB local interconnect lines, row interconnect lines (“H-type wires”), and column interconnect lines (“V-type wires”) (not shown) to route signals between components on the target device.
In the foregoing specification, embodiments of the invention have been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.
Claims (24)
1. A method for designing a system on a target device, comprising:
identifying an area on the target device that includes components affected by a timing exception for a portion of a signal path; and
performing register retiming where a register is moved from a first position on the signal path on one side of the area to a second position on the signal path on another side of the area.
2. The method of claim 1 , wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other portions of the signal path.
3. The method of claim 1 , wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other signal paths.
4. The method of claim 1 , wherein the timing exception comprises a multicycle that identifies how a default timing constraint may be applied differently to the portion of the signal path.
5. The method of claim 1 , wherein the timing exception comprises a false path that excuses a default timing constraint from being applied to the portion of the signal path.
6. The method of claim 1 , wherein the timing exception comprises a minimum delay and maximum delay for a signal on the portion of the signal path.
7. The method of claim 1 , wherein identifying the area that includes components affected by the timing exception comprises:
identifying a first component at a beginning of the timing exception;
identifying a second component at an end of the timing exception; and
defining the area to include the first component, the second component, and all components along the portion of the path between the first and second components.
8. The method of claim 1 further comprising:
identifying a second timing exception for a second portion of the signal path;
identifying a second area on the target device that includes components affected by the second timing exception, wherein the first position on the signal path is on one side of the second area and the second position on the signal path is on another side of the second area.
9. The method of claim 1 , wherein the register retiming reallocates delay along the signal path to allow a signal to satisfy timing requirements along the signal path.
10. The method of claim 1 , wherein the timing exception is provided by a user after timing analysis is performed on the system.
11. The method of claim 1 , wherein the timing exception is provided during design entry prior to synthesis, placement, and routing of the system.
12. The method of claim 1 , wherein register retiming is performed after synthesis, placement, and routing is performed on the system.
13. The method of claim 1 further comprising generating constraints that prevent registers residing in the area from being used for register retiming, wherein at least one of the identifying and generating is performed by a processor.
14. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method for designing a system on a target device, comprising:
identifying an area on the target device that includes components affected by a timing exception for a portion of a signal path; and
generating constraints that prevent registers residing in the area from being used for register retiming.
15. The non-transitory computer readable medium of claim 14 further comprising performing register retiming where a register is moved from a first position on the signal path on one side of the area to a second position on the signal path on another side of the area.
16. The non-transitory computer readable medium of claim 14 , wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other portions of the signal path.
17. The non-transitory computer readable medium of claim 14 , wherein the timing exception comprises a multicycle that identifies how a default timing constraint may be applied differently to the portion of the signal path.
18. The non-transitory computer readable medium of claim 14 , wherein the timing exception comprises a false path that excuses a default timing constraint from being applied to the portion of the signal path.
19. The non-transitory computer readable medium of claim 14 , wherein the timing exception comprises a minimum delay and maximum delay for a signal on the portion of the signal path.
20. The non-transitory computer readable medium of claim 15 further comprising generating a report that identifies the register and the timing exception to a user.
21. A system designer, comprising:
an area identification unit that identifies an area in a system that includes a first component at a beginning of a timing exception for a portion of a signal path, a second component at an end of the timing exception, and all components along the signal path between the first and the second components; and
a register retiming unit that performs register retiming where a register is moved from a first position on the signal path on one side of the area to a second position on the signal path on another side of the area.
22. The system designer of claim 21 further comprising a constraints unit that applies constraints to unallocated registers in the area to prevent the unallocated registers to be used in register retiming.
23. The system designer of claim 21 , wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other portions of the signal path.
24. The method of claim 21 , wherein the register retiming is performed after synthesis, placement, and routing is performed on the system.
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US20180232475A1 (en) * | 2015-02-20 | 2018-08-16 | Altera Corporation | Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions |
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US11544435B1 (en) * | 2020-06-22 | 2023-01-03 | Synopsys, Inc. | On-the-fly computation of analog mixed-signal (AMS) measurements |
Citations (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5448497A (en) | 1992-09-08 | 1995-09-05 | Nec Research Institute, Inc. | Exploiting multi-cycle false paths in the performance optimization of sequential circuits |
US5553000A (en) | 1992-11-05 | 1996-09-03 | Nec Usa, Inc. | Eliminating retiming bottlenecks to improve performance of synchronous sequential VLSI circuits |
US6026219A (en) | 1995-05-12 | 2000-02-15 | Synopsys, Inc. | Behavioral synthesis links to logic synthesis |
US6053949A (en) | 1996-09-20 | 2000-04-25 | Matsushita Electric Industrial Co., Ltd. | Simulator of logic circuit and simulation method |
US6075936A (en) | 1997-07-11 | 2000-06-13 | Mitsubishi Denki Kabushiki Kaisha | Logic circuit simulation apparatus having cycle-based simulator for simulating circuits including multi-cycle paths |
US6336205B1 (en) | 1998-11-12 | 2002-01-01 | Matsushita Electric Industrial Co., Ltd. | Method for designing semiconductor integrated circuit |
US20020199161A1 (en) * | 2001-06-20 | 2002-12-26 | Mitsubishi Denki Kabushiki Kaisha | Method of designing logic circuit, and computer product |
US6622290B1 (en) * | 2000-10-03 | 2003-09-16 | Cadence Design Systems, Inc. | Timing verification method employing dynamic abstraction in core/shell partitioning |
US20040225970A1 (en) | 2003-05-09 | 2004-11-11 | Levent Oktem | Method and apparatus for circuit design and retiming |
US6874135B2 (en) | 1999-09-24 | 2005-03-29 | Nec Corporation | Method for design validation using retiming |
US6941541B2 (en) | 2002-07-19 | 2005-09-06 | Hewlett-Packard Development Company, L.P. | Efficient pipelining of synthesized synchronous circuits |
US6952816B2 (en) | 2002-10-07 | 2005-10-04 | Hewlett-Packard Development Company, L.P. | Methods and apparatus for digital circuit design generation |
US6952817B1 (en) * | 2002-12-04 | 2005-10-04 | Xilinx, Inc. | Generating hardware interfaces for designs specified in a high level language |
US20050225365A1 (en) * | 2002-02-15 | 2005-10-13 | John Wood | Electronic circuits |
US7007254B1 (en) * | 2003-01-17 | 2006-02-28 | Synplicity, Inc. | Method and apparatus for the design and analysis of digital circuits with time division multiplexing |
US7058914B2 (en) | 2003-07-08 | 2006-06-06 | International Business Machines Corporation | Automatic latch compression/reduction |
US7120883B1 (en) * | 2003-05-27 | 2006-10-10 | Altera Corporation | Register retiming technique |
US7203919B2 (en) * | 2003-03-19 | 2007-04-10 | Peter Suaris | Retiming circuits using a cut-based approach |
US7289946B1 (en) * | 2003-08-22 | 2007-10-30 | Neo Magic Corp. | Methodology for verifying multi-cycle and clock-domain-crossing logic using random flip-flop delays |
US7318213B2 (en) * | 2005-06-17 | 2008-01-08 | Kabushiki Kaisha Toshiba | Apparatus, method and program for behavioral synthesis including loop processing |
US7350169B2 (en) | 2005-06-02 | 2008-03-25 | International Business Machines Corporation | Method and system for enhanced verification through structural target decomposition |
US7360190B1 (en) | 2003-07-11 | 2008-04-15 | Altera Corporation | Method and apparatus for performing retiming on field programmable gate arrays |
US7467361B2 (en) * | 2006-03-31 | 2008-12-16 | Kabushiki Kaisha Toshiba | Pipeline high-level synthesis system and method |
US7490307B2 (en) | 2006-06-29 | 2009-02-10 | Lsi Corporation | Automatic generating of timing constraints for the validation/signoff of test structures |
US7500205B2 (en) | 2001-12-06 | 2009-03-03 | Synopsys, Inc. | Skew reduction for generated clocks |
US7571303B2 (en) * | 2002-10-16 | 2009-08-04 | Akya (Holdings) Limited | Reconfigurable integrated circuit |
US7584449B2 (en) * | 2004-11-22 | 2009-09-01 | Fulcrum Microsystems, Inc. | Logic synthesis of multi-level domino asynchronous pipelines |
US7584441B2 (en) * | 2003-09-19 | 2009-09-01 | Cadence Design Systems, Inc. | Method for generating optimized constraint systems for retimable digital designs |
US7676768B1 (en) * | 2006-05-19 | 2010-03-09 | Altera Corporation | Automatic asynchronous signal pipelining |
US7774729B1 (en) * | 2006-06-02 | 2010-08-10 | Altera Corporation | Method and apparatus for reducing dynamic power in a system |
US7853912B2 (en) | 2007-11-05 | 2010-12-14 | International Business Machines Corporation | Arrangements for developing integrated circuit designs |
US7945880B1 (en) | 2007-05-30 | 2011-05-17 | Cadence Design Systems, Inc. | Constraint based retiming of synchronous circuits |
US8136063B2 (en) * | 2008-11-14 | 2012-03-13 | Synopsys, Inc. | Unfolding algorithm in multirate system folding |
US8346529B2 (en) | 2009-12-29 | 2013-01-01 | Mentor Graphics Corporation | Delta retiming in logic simulation |
US8381142B1 (en) | 2007-10-09 | 2013-02-19 | Altera Corporation | Using a timing exception to postpone retiming |
US8423939B1 (en) | 2010-04-06 | 2013-04-16 | Cadence Design Systems, Inc. | Boundary buffers to model register incompatibility during pre-retiming optimization |
US20130174113A1 (en) * | 2011-12-30 | 2013-07-04 | Arteris SAS | Floorplan estimation |
US8504970B1 (en) | 2011-07-05 | 2013-08-06 | Altera Corporation | Method and apparatus for performing automated timing closure analysis for systems implemented on target devices |
US20130297278A1 (en) | 2012-05-07 | 2013-11-07 | Synopsys, Inc. | Retiming a design for efficient parallel simulation |
US8751986B2 (en) * | 2010-08-06 | 2014-06-10 | Synopsys, Inc. | Method and apparatus for automatic relative placement rule generation |
US8863059B1 (en) * | 2013-06-28 | 2014-10-14 | Altera Corporation | Integrated circuit device configuration methods adapted to account for retiming |
US20140310696A1 (en) * | 2011-06-08 | 2014-10-16 | Hyperion Core Inc. | Tool-level and hardware-level code optimization and respective hardware modification |
US8893071B1 (en) * | 2013-07-12 | 2014-11-18 | Xilinx, Inc. | Methods of pipelining a data path in an integrated circuit |
US8918748B1 (en) * | 2012-08-24 | 2014-12-23 | Altera Corporation | M/A for performing automatic latency optimization on system designs for implementation on programmable hardware |
US8990739B2 (en) * | 2012-12-04 | 2015-03-24 | The Mathworks, Inc. | Model-based retiming with functional equivalence constraints |
US9098661B1 (en) * | 2008-12-10 | 2015-08-04 | The Mathworks, Inc. | Extensible platform for back-annotation of target-specific characterization onto a model of a hardware system |
US9251300B2 (en) * | 2013-10-25 | 2016-02-02 | Altera Corporation | Methods and tools for designing integrated circuits with auto-pipelining capabilities |
US9275184B1 (en) | 2014-01-21 | 2016-03-01 | Altera Corporation | Method and apparatus for performing timing closure analysis when performing register retiming |
US9292638B1 (en) * | 2014-01-21 | 2016-03-22 | Altera Corporation | Method and apparatus for performing timing closure analysis when performing register retiming |
US9384311B1 (en) | 2014-07-25 | 2016-07-05 | Altera Corporation | Programmable device configuration methods incorporating retiming |
US20160371403A1 (en) * | 2015-06-22 | 2016-12-22 | Altera Corporation | Method and Apparatus for Utilizing Estimations for Register Retiming in a Design Compilation Flow |
US9710591B1 (en) * | 2015-02-20 | 2017-07-18 | Altera Corporation | Method and apparatus for performing register retiming in the presence of timing analysis exceptions |
US9971858B1 (en) * | 2015-02-20 | 2018-05-15 | Altera Corporation | Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions |
-
2015
- 2015-02-20 US US14/627,191 patent/US9710591B1/en active Active
-
2017
- 2017-06-17 US US15/626,089 patent/US10339238B2/en active Active
Patent Citations (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5448497A (en) | 1992-09-08 | 1995-09-05 | Nec Research Institute, Inc. | Exploiting multi-cycle false paths in the performance optimization of sequential circuits |
US5553000A (en) | 1992-11-05 | 1996-09-03 | Nec Usa, Inc. | Eliminating retiming bottlenecks to improve performance of synchronous sequential VLSI circuits |
US6026219A (en) | 1995-05-12 | 2000-02-15 | Synopsys, Inc. | Behavioral synthesis links to logic synthesis |
US6053949A (en) | 1996-09-20 | 2000-04-25 | Matsushita Electric Industrial Co., Ltd. | Simulator of logic circuit and simulation method |
US6075936A (en) | 1997-07-11 | 2000-06-13 | Mitsubishi Denki Kabushiki Kaisha | Logic circuit simulation apparatus having cycle-based simulator for simulating circuits including multi-cycle paths |
US6336205B1 (en) | 1998-11-12 | 2002-01-01 | Matsushita Electric Industrial Co., Ltd. | Method for designing semiconductor integrated circuit |
US6874135B2 (en) | 1999-09-24 | 2005-03-29 | Nec Corporation | Method for design validation using retiming |
US6622290B1 (en) * | 2000-10-03 | 2003-09-16 | Cadence Design Systems, Inc. | Timing verification method employing dynamic abstraction in core/shell partitioning |
US20020199161A1 (en) * | 2001-06-20 | 2002-12-26 | Mitsubishi Denki Kabushiki Kaisha | Method of designing logic circuit, and computer product |
US7500205B2 (en) | 2001-12-06 | 2009-03-03 | Synopsys, Inc. | Skew reduction for generated clocks |
US20050225365A1 (en) * | 2002-02-15 | 2005-10-13 | John Wood | Electronic circuits |
US6941541B2 (en) | 2002-07-19 | 2005-09-06 | Hewlett-Packard Development Company, L.P. | Efficient pipelining of synthesized synchronous circuits |
US6952816B2 (en) | 2002-10-07 | 2005-10-04 | Hewlett-Packard Development Company, L.P. | Methods and apparatus for digital circuit design generation |
US7571303B2 (en) * | 2002-10-16 | 2009-08-04 | Akya (Holdings) Limited | Reconfigurable integrated circuit |
US7895416B2 (en) | 2002-10-16 | 2011-02-22 | Akya (Holdings) Limited | Reconfigurable integrated circuit |
US6952817B1 (en) * | 2002-12-04 | 2005-10-04 | Xilinx, Inc. | Generating hardware interfaces for designs specified in a high level language |
US7007254B1 (en) * | 2003-01-17 | 2006-02-28 | Synplicity, Inc. | Method and apparatus for the design and analysis of digital circuits with time division multiplexing |
US7203919B2 (en) * | 2003-03-19 | 2007-04-10 | Peter Suaris | Retiming circuits using a cut-based approach |
US20040225970A1 (en) | 2003-05-09 | 2004-11-11 | Levent Oktem | Method and apparatus for circuit design and retiming |
US7120883B1 (en) * | 2003-05-27 | 2006-10-10 | Altera Corporation | Register retiming technique |
US8108812B1 (en) * | 2003-05-27 | 2012-01-31 | Altera Corporation | Register retiming technique |
US7058914B2 (en) | 2003-07-08 | 2006-06-06 | International Business Machines Corporation | Automatic latch compression/reduction |
US7360190B1 (en) | 2003-07-11 | 2008-04-15 | Altera Corporation | Method and apparatus for performing retiming on field programmable gate arrays |
US7289946B1 (en) * | 2003-08-22 | 2007-10-30 | Neo Magic Corp. | Methodology for verifying multi-cycle and clock-domain-crossing logic using random flip-flop delays |
US7584441B2 (en) * | 2003-09-19 | 2009-09-01 | Cadence Design Systems, Inc. | Method for generating optimized constraint systems for retimable digital designs |
US7584449B2 (en) * | 2004-11-22 | 2009-09-01 | Fulcrum Microsystems, Inc. | Logic synthesis of multi-level domino asynchronous pipelines |
US7350169B2 (en) | 2005-06-02 | 2008-03-25 | International Business Machines Corporation | Method and system for enhanced verification through structural target decomposition |
US7318213B2 (en) * | 2005-06-17 | 2008-01-08 | Kabushiki Kaisha Toshiba | Apparatus, method and program for behavioral synthesis including loop processing |
US7467361B2 (en) * | 2006-03-31 | 2008-12-16 | Kabushiki Kaisha Toshiba | Pipeline high-level synthesis system and method |
US7676768B1 (en) * | 2006-05-19 | 2010-03-09 | Altera Corporation | Automatic asynchronous signal pipelining |
US7774729B1 (en) * | 2006-06-02 | 2010-08-10 | Altera Corporation | Method and apparatus for reducing dynamic power in a system |
US7490307B2 (en) | 2006-06-29 | 2009-02-10 | Lsi Corporation | Automatic generating of timing constraints for the validation/signoff of test structures |
US7945880B1 (en) | 2007-05-30 | 2011-05-17 | Cadence Design Systems, Inc. | Constraint based retiming of synchronous circuits |
US8381142B1 (en) | 2007-10-09 | 2013-02-19 | Altera Corporation | Using a timing exception to postpone retiming |
US7853912B2 (en) | 2007-11-05 | 2010-12-14 | International Business Machines Corporation | Arrangements for developing integrated circuit designs |
US8136063B2 (en) * | 2008-11-14 | 2012-03-13 | Synopsys, Inc. | Unfolding algorithm in multirate system folding |
US9098661B1 (en) * | 2008-12-10 | 2015-08-04 | The Mathworks, Inc. | Extensible platform for back-annotation of target-specific characterization onto a model of a hardware system |
US8346529B2 (en) | 2009-12-29 | 2013-01-01 | Mentor Graphics Corporation | Delta retiming in logic simulation |
US8423939B1 (en) | 2010-04-06 | 2013-04-16 | Cadence Design Systems, Inc. | Boundary buffers to model register incompatibility during pre-retiming optimization |
US8751986B2 (en) * | 2010-08-06 | 2014-06-10 | Synopsys, Inc. | Method and apparatus for automatic relative placement rule generation |
US20140310696A1 (en) * | 2011-06-08 | 2014-10-16 | Hyperion Core Inc. | Tool-level and hardware-level code optimization and respective hardware modification |
US8504970B1 (en) | 2011-07-05 | 2013-08-06 | Altera Corporation | Method and apparatus for performing automated timing closure analysis for systems implemented on target devices |
US20130174113A1 (en) * | 2011-12-30 | 2013-07-04 | Arteris SAS | Floorplan estimation |
US20130297278A1 (en) | 2012-05-07 | 2013-11-07 | Synopsys, Inc. | Retiming a design for efficient parallel simulation |
US8918748B1 (en) * | 2012-08-24 | 2014-12-23 | Altera Corporation | M/A for performing automatic latency optimization on system designs for implementation on programmable hardware |
US8990739B2 (en) * | 2012-12-04 | 2015-03-24 | The Mathworks, Inc. | Model-based retiming with functional equivalence constraints |
US8863059B1 (en) * | 2013-06-28 | 2014-10-14 | Altera Corporation | Integrated circuit device configuration methods adapted to account for retiming |
US8893071B1 (en) * | 2013-07-12 | 2014-11-18 | Xilinx, Inc. | Methods of pipelining a data path in an integrated circuit |
US9251300B2 (en) * | 2013-10-25 | 2016-02-02 | Altera Corporation | Methods and tools for designing integrated circuits with auto-pipelining capabilities |
US9275184B1 (en) | 2014-01-21 | 2016-03-01 | Altera Corporation | Method and apparatus for performing timing closure analysis when performing register retiming |
US9292638B1 (en) * | 2014-01-21 | 2016-03-22 | Altera Corporation | Method and apparatus for performing timing closure analysis when performing register retiming |
US9384311B1 (en) | 2014-07-25 | 2016-07-05 | Altera Corporation | Programmable device configuration methods incorporating retiming |
US9710591B1 (en) * | 2015-02-20 | 2017-07-18 | Altera Corporation | Method and apparatus for performing register retiming in the presence of timing analysis exceptions |
US9971858B1 (en) * | 2015-02-20 | 2018-05-15 | Altera Corporation | Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions |
US20160371403A1 (en) * | 2015-06-22 | 2016-12-22 | Altera Corporation | Method and Apparatus for Utilizing Estimations for Register Retiming in a Design Compilation Flow |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180232475A1 (en) * | 2015-02-20 | 2018-08-16 | Altera Corporation | Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions |
US10671781B2 (en) * | 2015-02-20 | 2020-06-02 | Altera Corporation | Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions |
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