US10269657B2 - Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor - Google Patents
Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor Download PDFInfo
- Publication number
- US10269657B2 US10269657B2 US15/730,085 US201715730085A US10269657B2 US 10269657 B2 US10269657 B2 US 10269657B2 US 201715730085 A US201715730085 A US 201715730085A US 10269657 B2 US10269657 B2 US 10269657B2
- Authority
- US
- United States
- Prior art keywords
- region
- substrate
- gate
- dielectric
- gate dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 132
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 7
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 7
- 230000005669 field effect Effects 0.000 title abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 87
- 125000006850 spacer group Chemical group 0.000 claims description 41
- 238000000034 method Methods 0.000 description 67
- 108091006146 Channels Proteins 0.000 description 29
- 239000002019 doping agent Substances 0.000 description 24
- 238000000151 deposition Methods 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 21
- 230000008021 deposition Effects 0.000 description 19
- 238000005229 chemical vapour deposition Methods 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 238000001020 plasma etching Methods 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 238000005530 etching Methods 0.000 description 14
- 239000004020 conductor Substances 0.000 description 13
- 150000004767 nitrides Chemical class 0.000 description 13
- 238000000231 atomic layer deposition Methods 0.000 description 10
- 238000002955 isolation Methods 0.000 description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005137 deposition process Methods 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 8
- -1 for example Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- YWWDBCBWQNCYNR-UHFFFAOYSA-N trimethylphosphine Chemical compound CP(C)C YWWDBCBWQNCYNR-UHFFFAOYSA-N 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910002244 LaAlO3 Inorganic materials 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910003828 SiH3 Inorganic materials 0.000 description 2
- 229910002370 SrTiO3 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- YOTZYFSGUCFUKA-UHFFFAOYSA-N dimethylphosphine Chemical compound CPC YOTZYFSGUCFUKA-UHFFFAOYSA-N 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- NEXSMEBSBIABKL-UHFFFAOYSA-N hexamethyldisilane Chemical compound C[Si](C)(C)[Si](C)(C)C NEXSMEBSBIABKL-UHFFFAOYSA-N 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 2
- OLRJXMHANKMLTD-UHFFFAOYSA-N silyl Chemical compound [SiH3] OLRJXMHANKMLTD-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 2
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000807 Ga alloy Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 229910007258 Si2H4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 125000000484 butyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000224 chemical solution deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- OXTURSYJKMYFLT-UHFFFAOYSA-N dichlorogermane Chemical compound Cl[GeH2]Cl OXTURSYJKMYFLT-UHFFFAOYSA-N 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- VZZJVOCVAZHETD-UHFFFAOYSA-N diethylphosphane Chemical compound CCPCC VZZJVOCVAZHETD-UHFFFAOYSA-N 0.000 description 1
- VXGHASBVNMHGDI-UHFFFAOYSA-N digermane Chemical compound [Ge][Ge] VXGHASBVNMHGDI-UHFFFAOYSA-N 0.000 description 1
- UCMVNBCLTOOHMN-UHFFFAOYSA-N dimethyl(silyl)silane Chemical compound C[SiH](C)[SiH3] UCMVNBCLTOOHMN-UHFFFAOYSA-N 0.000 description 1
- UBHZUDXTHNMNLD-UHFFFAOYSA-N dimethylsilane Chemical compound C[SiH2]C UBHZUDXTHNMNLD-UHFFFAOYSA-N 0.000 description 1
- JZZIHCLFHIXETF-UHFFFAOYSA-N dimethylsilicon Chemical compound C[Si]C JZZIHCLFHIXETF-UHFFFAOYSA-N 0.000 description 1
- 125000000047 disilanyl group Chemical group [H][Si]([*])([H])[Si]([H])([H])[H] 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- KCWYOFZQRFCIIE-UHFFFAOYSA-N ethylsilane Chemical compound CC[SiH3] KCWYOFZQRFCIIE-UHFFFAOYSA-N 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- IQCYANORSDPPDT-UHFFFAOYSA-N methyl(silyl)silane Chemical compound C[SiH2][SiH3] IQCYANORSDPPDT-UHFFFAOYSA-N 0.000 description 1
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 125000001436 propyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])[H] 0.000 description 1
- 229910002059 quaternary alloy Inorganic materials 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
- IEXRMSFAVATTJX-UHFFFAOYSA-N tetrachlorogermane Chemical compound Cl[Ge](Cl)(Cl)Cl IEXRMSFAVATTJX-UHFFFAOYSA-N 0.000 description 1
- MUDDKLJPADVVKF-UHFFFAOYSA-N trichlorogermane Chemical compound Cl[GeH](Cl)Cl MUDDKLJPADVVKF-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- RXJKFRMDXUJTEX-UHFFFAOYSA-N triethylphosphine Chemical compound CCP(CC)CC RXJKFRMDXUJTEX-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Definitions
- the present disclosure relates to methods of forming semiconductor devices and the electronic device structures produced thereby, and more particularly to a method of epitaxially forming the drain, channel, and source of a vertical finFET.
- a Field Effect Transistor typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the channel.
- FETs semiconductor field effect transistors
- Planar FET devices typically have a conducting gate electrode positioned above a semiconducting channel, and electrically isolated from the channel by a thin layer of gate oxide. Current through the channel is controlled by applying voltage to the conducting gate.
- the present disclosure provides an electrical device that includes a substrate including a lateral device region and a vertical device region.
- a second semiconductor device is present in the vertical device region, wherein a vertical channel has a length that is perpendicular to said upper surface of the substrate, the second semiconductor device including a gate structure that is positioned around the vertical channel.
- the electrical device includes a substrate including a lateral device region and a vertical device region.
- a lateral diffusion metal oxide semiconductor (LDMOS) device is present in the lateral device region, wherein a diffusion region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed.
- a vertical field effect transistor (VFET) device is present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.
- LDMOS lateral diffusion metal oxide semiconductor
- VFET vertical field effect transistor
- a method of forming an electrical device includes forming at least one first fin structure in a lateral device region of a substrate and forming at least one second fin structure in a vertical device region of the substrate.
- a drift region is formed in the lateral device region and a dopant region is formed in the vertical device region of the substrate for the first of a source region and drain region.
- a dielectric layer is formed in the lateral device region of the substrate and the vertical device region of the substrate.
- a first portion of the dielectric layer provides a gate dielectric for a LDMOS device being formed in the lateral device region.
- a second portion of the dielectric spacer provides a spacer for the VFET.
- a gate structure is formed for the LDMOS devices and the VFET devices.
- An epitaxial semiconductor material is formed on the at least one first fin structure in the lateral device region of the substrate and the at least one second fin structure in the vertical device region of the substrate.
- the epitaxial semiconductor material in the lateral device region may provide dopant region for one of source region or drain region for the LDMOS device.
- the epitaxial semiconductor material in the vertical device region provides a doped region for a second of the source region and drain region.
- FIG. 1 is a side cross-sectional view of a substrate that has been etched to provide at least one first fin structure in a lateral device region and at least one second fin structure in a vertical device region, in accordance with one embodiment of the present disclosure.
- FIG. 2 is a side cross-sectional view of forming at least one conformal dielectric layer on the fin structures, and forming isolation regions separating the lateral device region from the vertical device region, in accordance with one embodiment of the present disclosure.
- FIG. 3 is a side cross-sectional view depicting one embodiment of forming a drift region in the lateral device region of the substrate, in accordance with the present disclosure.
- FIG. 4 is a side cross-sectional view depicting one embodiment of forming a first of a source region and a drain region in the vertical device region of the substrate, in accordance with one embodiment of the present disclosure.
- FIG. 5 is a side cross-sectional view depicting one embodiment of forming a dielectric layer in the lateral device region of the substrate and the vertical device region of the substrate, wherein a first portion of the dielectric layer provides a drift region gate dielectric for a LDMOS device being formed in the lateral device region, and a second portion of the dielectric spacer provides a spacer for the VFET being formed in the vertical device region.
- FIG. 6 is a side cross-sectional view of forming a thickened portion of the dielectric layer in the lateral device region, in accordance with one embodiment of the present disclosure.
- FIG. 7 is a side cross-sectional view depicting one embodiment of forming a gate dielectric on the fin structures, in accordance with the present disclosure.
- FIG. 8 is a side cross-sectional view depicting forming the material layers for the gate structures for the LDMOS devices and the VFET devices, in accordance with one embodiment of the present disclosure.
- FIG. 9 is a side cross-sectional view depicting patterning the material layer for the gate structures for the LDMOS devices and the VFET devices, in accordance with one embodiment of the present disclosure.
- FIG. 10 is a side cross-sectional view depicting forming an epitaxial semiconductor material on the at least one first fin structure in the lateral device region of the substrate and the at least one second fin structure in the vertical device region of the substrate, in accordance with the present disclosure.
- FIG. 11A is a top down view of an LDMOS semiconductor device in accordance with one embodiment of the present disclosure.
- FIG. 11B is a side cross-sectional view of one embodiment of an LDMOS semiconductor device, as depicted in FIG. 11A , in which the drift oxide has a single thickness.
- FIG. 11C is a side cross-sectional view of another embodiment of an LDMOS semiconductor device, as depicted in FIG. 11A , in which the drift oxide has two drift oxide thicknesses.
- FIG. 12A is a top down view of an LDMOS semiconductor device having a rectangular contact to the gate region, in accordance with one embodiment of the present disclosure.
- FIG. 12B is a side cross-sectional view of the LDMOS semiconductor device depicted in FIG. 12A .
- FIG. 13A is a top down view of a split gate LDMOS semiconductor device.
- FIG. 13B is a side cross-sectional view of the LDMOS semiconductor device depicted in FIG. 13A .
- FIG. 14A is a top down view of a symmetrical LDMOS semiconductor device, in accordance with some embodiments of the present disclosure.
- FIG. 14B is a side cross-sectional view of the structure depicted in FIG. 14A , in which the LDMOS device includes two source contacts.
- FIG. 14C is a side cross-sectional view of the structure depicted in FIG. 14A , in which the LDMOS device includes a single source contact.
- FIG. 15A is a top down view of a LDMOS semiconductor device including an isolation region in the drift region, in accordance with some embodiments of the present disclosure.
- FIG. 15B is a side cross-sectional view of the structure depicted in FIG. 15A .
- FIG. 16A is a top down view of another embodiment of an LDMOS semiconductor device including an isolation region in the drift region, in which the gate contact is offset from the source contact and the diffusion region contact, in accordance with one embodiment of the present disclosure.
- FIG. 16B is a side cross-sectional view of the structure depicted in FIG. 16A .
- the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the embodiments of the disclosure, as it is oriented in the drawing figures.
- the terms “positioned on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element.
- intervening elements such as an interface structure, e.g. interface layer
- directly contact means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
- the methods and structures disclosed herein form a Vertical Fin Field Effect Transistor (VFET) in combination with a Lateral Diffusion Metal Oxide Semiconductor (LDMOS) device on the same semiconductor substrate.
- VFET Vertical Fin Field Effect Transistor
- LDMOS Lateral Diffusion Metal Oxide Semiconductor
- a field effect transistor (FET) is a semiconductor device in which output current, i.e., source-drain current, is controlled by the voltage applied to a gate structure to the semiconductor device.
- a field effect transistor has three terminals, i.e., gate structure, source region and drain region.
- a “fin structure” refers to a semiconductor material, which is employed as the body of a semiconductor device, in which the gate structure is positioned around the fin structure such that charge flows down the channel of the fin structure
- a finFET is a semiconductor device that positions the channel region of the semiconductor device in a fin structure.
- the source and drain regions of the fin structure are the portions of the fin structure that are on opposing sides of the channel region of the fin structure.
- a finFET semiconductor device has the drain, fin channel, and source device components arranged perpendicular to the plane of the substrate surface, which is referred to as a vertical stack.
- a vertically stacked finFET i.e., Vertical FinFET (VFinFET)
- VFinFET can have a longer gate length (i.e., height) and larger dielectric spacer than a horizontal (i.e., having the drain, fin channel, and source device components arranged parallel with the plane of the substrate surface) finFET having comparable contact gate pitch.
- the Laterally Diffused MOSFET is an asymmetric power MOSFET that in some examples can be designed for low on-resistance and high blocking voltage. These features can be obtained by creating a diffused first conductivity type channel region, e.g., p-type channel region, in a low-doped second conductivity type drain region, e.g., n-type drain region. The low doping on the drain side results in a large depletion layer with high blocking voltage.
- the channel region diffusion can be defined with the same mask as the source region, resulting in a short channel with high current handling capability.
- the LDMOS structure combines a short channel length with high breakdown voltage as desired for high power RF amplifiers, e.g., ranging from 10 MHz to 3.8 GHz, in numerous applications.
- This device is currently the device of choice for RF power amplifiers in base stations of wireless communications systems as well as numerous UHF and L-band power amplifiers in broadcast, communication and radar systems.
- the methods and structures disclosed herein integrate LDMOS devices with VFETs. The methods and structures of the present disclosure are now described with greater detail with reference to FIGS. 1-16B .
- FIG. 1 depicts one embodiment of a substrate 1 that has been etched to provide at least one first fin structure 5 in a lateral device region 15 , and at least one second fin structure 10 in a vertical device region 20 of the substrate 1 .
- the substrate 1 may be a semiconductor.
- the substrate 1 may be crystalline.
- the substrate 1 may be primarily (i.e., with doping) of a single element, for example, silicon (Si) or germanium, (Ge), or the substrate 1 may be a compound, for example, GaAs, SiC, or SiGe.
- the substrate 1 may also have multiple material layers, for example, a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), germanium-on-insulator substrate (GeOI), or silicon-germanium-on-insulator substrate (SGOI).
- the substrate 1 may also have other layers forming the substrate, including high-k oxides and/or nitrides.
- the substrate 1 may be a silicon wafer.
- the substrate is a single crystal silicon wafer.
- the substrate 1 includes a first device region, also referred to as lateral device region 15 , in which the LDMOS device is to be formed, and a second device region, also referred to as a vertical device region 20 , in which the VFET is to be formed.
- the substrate 1 may be processed to provide fin structures 5 , 10 .
- the fin structures 5 , 10 are typically formed using deposition, photolithography, i.e., patterning, and etch processes.
- the patterning process used to define each of the fin structures 5 , 10 is a sidewall image transfer (SIT) process.
- the SIT process can include forming a first mandrel material layer (not shown) on the material layer that provides the fin structures 5 , 10 .
- the first mandrel material layer can include any material (semiconductor, dielectric or conductive) that can be selectively removed from the structure during a subsequently performed etching process.
- the first mandrel material layer can be formed by a deposition method, such as chemical vapor deposition or plasma enhanced chemical vapor deposition.
- the thickness of the first mandrel material layer can be from 50 nm to 300 nm.
- the first mandrel material layer can be patterned by lithography and etching to form a plurality of first mandrel structures on the topmost surface of the semiconductor containing material that provides the fin structures 10 , e.g., the upper surface of the semiconductor substrate 1 .
- the SIT process may continue by forming a dielectric spacer on each sidewall of each of the first mandrel structures.
- the dielectric spacer can be formed by deposition of a dielectric spacer material, and then etching the deposited dielectric spacer material.
- the dielectric spacer material may comprise any dielectric spacer material such as, for example, silicon dioxide, silicon nitride or a dielectric metal oxide. Examples of deposition processes that can be used in providing the dielectric spacer material include, but are not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).
- CVD chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- ALD atomic layer deposition
- etching examples include any etching process such as, e.g., reactive ion etching (RIE). Since the dielectric spacers are used in the SIT process as an etch mask, the width of the each dielectric spacer determines the width of each fin structure 5 , 10 .
- RIE reactive ion etching
- the SIT process continues by removing each the first mandrel structure.
- Each of the first mandrel structures can be removed by an etching process that is selective for removing the mandrel material as compared to semiconductor material of the substrate that provides the fin structures 5 , 10 , e.g., silicon (Si).
- the SIT process continues by transferring the pattern provided by the dielectric spacers into the semiconductor material layer that provides the fin structures 5 , 10 , such as the upper surface of semiconductor substrate 1 .
- the pattern transfer may be achieved by utilizing at least one etching process that can include dry etching, such as reactive ion etching (RIE), plasma etching, ion beam etching or laser ablation, chemical wet etch processes or a combination thereof.
- the etch process used to transfer the pattern may include one or more reactive ion etching (RIE) steps.
- RIE reactive ion etching
- the etching steps pattern the semiconductor substrate 1 to provide the fin structures 10 , 15 .
- the SIT process may conclude with removing the dielectric spacers using an etch process or a planarization process.
- each of the fin structures 5 , 10 may be formed using a photoresist etch mask.
- a photoresist mask is formed overlying the semiconductor composition layer which provides the fin structures 5 , 10 .
- the exposed portions of the semiconductor layer that provides the fin structures 5 , 10 that are not protected by the photoresist mask are removed using a selective etch process.
- a photoresist layer is first positioned on the portion of the semiconductor substrate 1 that provides the fin structures 5 , 10 .
- the photoresist layer may be provided by a blanket layer of photoresist material that is formed utilizing a deposition process such as, e.g., plasma enhanced CVD (PECVD), evaporation or spin-on coating.
- PECVD plasma enhanced CVD
- the blanket layer of photoresist material is then patterned to provide the photoresist mask utilizing a lithographic process that may include exposing the photoresist material to a pattern of radiation and developing the exposed photoresist material utilizing a resist developer.
- a lithographic process may include exposing the photoresist material to a pattern of radiation and developing the exposed photoresist material utilizing a resist developer.
- an etching process may remove the unprotected portions of the semiconductor substrate 1 that provides the fin structures 5 , 10 , e.g., selectively etch the unprotected portions.
- the etch process may be an anisotropic process, such as reactive ion etch (RIE).
- each of the fin structures 5 , 10 may have a height H 1 ranging from 5 nm to 200 nm. In another embodiment, each of the plurality of fin structures 5 , 10 has a height H 1 ranging from 10 nm to 100 nm. In one example, each of the plurality of fin structures 10 has a height H 1 ranging from 20 nm to 50 nm. Each of the plurality of fin structures 10 may have a width W 1 of less than 20 nm. In another embodiment, each of the plurality of fin structures 10 has a width W 1 ranging from 3 nm to 15 nm.
- the present disclosure is not limited to only this example. It is noted that any number of fin structures 5 , 10 may be present in the lateral device region 15 and the vertical device region 20 of the substrate 1 .
- the pitch P 1 separating adjacent fin structures 10 in the vertical device region 20 may range from 15 nm to 500 nm. In another example, the pitch P 1 separating adjacent fin structures 10 in the vertical device region 20 may range from 20 nm to 50 nm.
- the fin structure 10 may be composed of a type IV semiconductor material or a compound semiconductor material.
- type IV semiconductor it is meant that the semiconductor material includes at least one element from Group IVA (i.e., Group 14) of the Periodic Table of Elements.
- type IV semiconductor materials that are suitable for the fin structure include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon doped with carbon (Si:C), silicon germanium doped with carbon (SiGe:C) and a combination thereof.
- the semiconductor substrate 5 is composed of silicon (Si), e.g., single crystal silicon.
- a compound semiconductor composition that may provide the fin structures 10 is a type III-V semiconductor.
- the III-V compound semiconductors are binary, ternary or quaternary alloys including III/V elements.
- III-V compound semiconductors that can be used for the composition of the fin structures 5 , 10 include, but are not limited to alloys of gallium arsenic (GaAs), aluminum arsenic (AlAs), indium gallium arsenic (InGaAs), indium aluminum arsenic (InAlAs), indium aluminum arsenic antimony (InAlAsSb), indium aluminum arsenic phosphorus (InAlAsP), indium gallium arsenic phosphorus (InGaAsP) and combinations thereof.
- the fin structures are not doped with n-type or p-type dopant via external doping methods.
- a dielectric cap 2 may be present atop each of the fin structures 5 , 10 .
- the dielectric cap 2 may be composed of an oxide, nitride or oxynitride material, and may be formed as part of the process sequence that forms the fin structures 5 , 10 .
- the oxide may be silicon oxide.
- the nitride may be silicon nitride.
- FIG. 2 depicts one embodiment of forming at least one conformal dielectric layer 3 , 4 on the fin structures 5 , 10 , and forming isolation regions 6 separating the lateral device region 15 from the vertical device region 20 .
- the term “conformal layer” denotes a layer having a thickness that does not deviate from greater than or less than 30% of an average value for the thickness of the layer.
- the at least one conformal dielectric layer 3 , 4 is a bilayer of an oxide containing layer 3 and a nitride containing layer 4 .
- the oxide containing layer 3 may be blanket deposited atop the structure depicted in FIG. 1 including the fin structures 5 , 10 and the upper surface of the semiconductor substrate that is separating the adjacent fin structures 5 , 10 .
- the oxide containing layer 3 may be composed of silicon oxide.
- the nitride containing layer 4 may be blanket deposited atop the oxide containing layer.
- the nitride containing layer 4 is composed of silicon nitride.
- the at least one conformal dielectric layer 3 , 4 may be deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD).
- CVD chemical vapor deposition
- ALD atomic layer deposition
- the thickness for each of the oxide containing layer 3 and the nitride containing layer 4 may range from 0.5 nm to 15 nm. In other embodiments, the thickness for each of the oxide containing layer 3 and the nitride containing layer 4 may range from 1 nm to 5 nm.
- isolation regions 6 may be formed separating the lateral device region 15 from the vertical device region 20 .
- Forming the isolation regions 6 may include forming a first dielectric layer atop the at least one conformal dielectric layer 3 , 4 , and planarizing the first dielectric layer so that the upper surface of the first dielectric layer is coplanar with the upper surface of the dielectric cap 2 .
- the planarization process may be provided by chemical mechanical planarization (CMP).
- CMP chemical mechanical planarization
- the first dielectric layer and the portions of the substrate 1 at the interface between the lateral device region 15 and the vertical device region 20 may then be etched with a shallow trench isolation region etch for forming a trench structure.
- the etch process may including forming a photoresist mask and then applying an anisotropic etch, such as reactive ion etch (RIE), for forming the trench structure.
- RIE reactive ion etch
- the trench structure may then be filled with an insulating dielectric, such as silicon oxide, which may be deposited using a chemical vapor deposition (CVD) process, such as plasma enhanced chemical vapor deposition.
- CVD chemical vapor deposition
- FIG. 3 depicts one embodiment of forming a drift region 8 in the lateral device region 15 of the substrate 1 .
- the drift region 8 is a component of the LDMOS device is present in the portion of the substrate 1 within the lateral device region 15 between the isolation regions 6 .
- the drift region is typically doped with a conductivity type dopant that is opposite the conductivity type of the LDMOS device.
- the term “conductivity type” denotes whether the dopant provides a p-type conductivity or an n-type conductivity.
- p-type refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons.
- examples of p-type dopants include but are not limited to: boron, aluminum, gallium and indium.
- n-type refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor.
- examples of n-type dopants, i.e., impurities include but are not limited to antimony, arsenic and phosphorous.
- the drift region 8 may be doped to a p-type conductivity.
- the drift region 8 may be doped to an n-type conductivity.
- the first dielectric layer Before forming the drift region 8 , the first dielectric layer may be recessed to reveal the fin structures 5 , 10 . Recessing the first dielectric layer can include a selective etch process, such as a wet chemical etch, or a dry etch, such as reactive ion etch (RIE). The etch process may be selective to the at least one conformal dielectric layer 3 , 4 that is present on the fin structures 5 , 10 .
- RIE reactive ion etch
- a first block mask may be formed over the vertical device region 20 , and the dopant that provides the selected conductivity type is implanted into the exposed lateral device region 15 .
- the first block mask may be a photoresist mask that is formed using photolithography and development processes.
- the dopant that provides the conductivity type may be doped into the portion of the semiconductor substrate 1 in which the drift region 8 is formed at a concentration ranging from 1 ⁇ 10 11 atoms/cm 3 to 1 ⁇ 10 3 atoms/cm 3 .
- the dopant that provides the conductivity type may be doped into the portion of the semiconductor substrate 1 in which the drift region 8 is formed at a concentration ranging from 5 ⁇ 10 11 atoms/cm 3 to 5 ⁇ 10 12 atoms/cm 3 .
- the dopant that provides the conductivity type may be doped into the portion of the semiconductor substrate 1 in which the drift region 8 is formed at a concentration of 1 ⁇ 10 12 atoms/cm 3 .
- the structure is annealed.
- the anneal process may be provided by thermal anneal, such as rapid thermal anneal (RTA), laser annealing, IR heating, furnace annealing and combinations thereof.
- RTA rapid thermal anneal
- the anneal process for forming the drift region 8 may be at a temperature ranging from 800° C. to 1100° C.
- the first block mask that was formed over the vertical device region 20 is removed.
- FIG. 4 depicts one embodiment of forming a dopant region 9 for a first of a source region and a drain region in the vertical device region 20 of the substrate 1 .
- a first of the source region and the drain region it is meant that dopant region provides one of a source region or a drain region, and the other of the source or drain region is formed on an opposing side of the fin structure 10 .
- the doped region 9 is a source region
- the drain region is formed on the opposing surface, i.e., upper surface of the fin structure 10 .
- the doped region is a drain region
- the source region is formed on the opposing surface, i.e., upper surface of the fin structure 10 .
- the conductivity type for the doped region 9 dictates the conductivity type of the VFET.
- the VFETs are n-type semiconductor devices.
- the VFETs are p-type semiconductor devices.
- a second block mask may be formed over the lateral device region 15 , and the dopant that provides the selected conductivity type for the VFETs is implanted into the exposed vertical device region 20 .
- the second block mask may be a photoresist mask that is formed using photolithography and development processes.
- the dopant that provides the conductivity type for the VFETs may be doped into the portion of the semiconductor substrate 1 between the fin structures 10 to provide the doped region 9 for a first of a source region and a drain region at a concentration ranging from 5 ⁇ 10 19 atoms/cm 3 to 5 ⁇ 10 21 atoms/cm 3 .
- the dopant that provides the conductivity type for the VFETs may be doped into the portion of the semiconductor substrate 1 between the fin structures 10 to provide the doped region 9 for a first of a source region and a drain region at a concentration ranging from 5 ⁇ 10 19 atoms/cm 3 to 5 ⁇ 10 20 atoms/cm 3 .
- the structure is annealed to provide a diffused dopant region 9 ′.
- the anneal process may be provided by thermal anneal, such as rapid thermal anneal (RTA), laser annealing, IR heating, furnace annealing and combinations thereof.
- RTA rapid thermal anneal
- the anneal process for forming the doped region 9 may be at a temperature ranging from 800° C. to 1100° C.
- the block mask that was formed over the lateral device region 15 is removed.
- FIG. 5 depicts one embodiment of forming a dielectric layer 11 a , 11 b in the lateral device region 15 of the substrate 1 and the vertical device region 20 of the substrate 1 , wherein a first portion of the dielectric layer 11 a provides a drift region gate dielectric for a LDMOS device being formed in the lateral device region 15 , and a second portion of the dielectric layer 11 b provides a spacer for the VFET being formed in the vertical device region 20 .
- the at least one conformal dielectric layer 3 , 4 may be removed from the upper surfaces of the portions of the substrate separating the fin structures 5 , 10 .
- the at least one conformal dielectric layer 3 , 4 may be removed using an etch process that is selective to the fin structures 5 , 10 and the substrate 1 .
- the lateral portions of the at least one conformal dielectric layer 3 , 4 i.e., the portions of the conformal dielectric layer 3 , 4 that are present on the upper surfaces of the substrate 1 and the upper surface of dielectric cap 2 overlying the fin structures 5 , 10 is removed by an anisotropic etch, such as reactive ion etch (RIE).
- RIE reactive ion etch
- the dielectric layer 11 a , 11 b may be an oxide or a nitride dielectric layer.
- the dielectric layer 11 a , 11 b may be composed of silicon oxide.
- the dielectric layer 11 a , 11 b may be composed of a nitride, such as silicon nitride.
- the dielectric layer 11 a , 11 b may be composed of a high-k dielectric material.
- “high-k” denotes a dielectric material featuring a dielectric constant (k) higher than the dielectric constant of SiO 2 at room temperature.
- the dielectric layer 11 a , 11 b may be composed of a high-k oxide such as, for example, HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 and mixtures thereof.
- a high-k oxide such as, for example, HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 and mixtures thereof.
- high-k dielectric materials for the at least one gate dielectric include hafnium silicate, hafnium silicon oxynitride or combinations thereof.
- the dielectric layer 11 a , 11 b may be formed using a deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or may be formed using a growth process, such as thermal oxidation.
- the dielectric layer 11 a , 11 b may have a thickness ranging from 2 nm to 20 nm. In some examples, the dielectric layer 11 a , 11 b may have a thickness ranging from 2 nm to 10 nm.
- FIG. 6 depicts one embodiment of an optional step of increasing the thickness of a portion of the dielectric layer 11 a that is present in the lateral device region 10 , wherein the thickness of the dielectric layer 11 a is being increased for applications in higher voltages.
- the portion of the dielectric layer 11 c having the greater thickness does not extend across the entire portion of the dielectric layer 11 a that is present in the lateral device region 10 .
- the portion of the dielectric layer 11 c having the greater thickness may be selectively formed by using a block mask, e.g., a photoresist mask, that is covering the portions of the structure depicted in FIG. 5 in which additional dielectric deposition is not desired.
- the block mask has an opening exposing the portion of the dielectric layer 11 a on which addition dielectric material is to be formed producing the greater thickness dielectric layer 11 a .
- the greater thickness dielectric layer 11 c typically has the same composition as the dielectric layer 11 a that is present in the lateral device region 10 .
- the greater thickness dielectric layer 11 c is typically formed using thermal growth or a deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).
- the greater thickness dielectric layer 11 c may have a thickness ranging from 5 nm to 25 nm. In other embodiments, the thickness of the greater thickness dielectric layer 11 c may range from 6 nm to 12 nm. It is noted that the process step depicted in FIG.
- FIGS. 7-10 illustrate a process that does not employ the optional steps and structures depicted in FIG. 6 , the methods and structures depicted in FIGS. 7-10 are equally applicable to the embodiments including the optional method steps and structures that are depicted in FIG. 6 .
- FIG. 7 depicts one embodiment of forming a gate dielectric 12 on the fin structures 5 , 10 .
- Forming the gate dielectric 12 may include removing at least a portion of the at least one conformal dielectric layer 3 , 4 .
- the at least one conformal dielectric layer 3 , 4 may be removed by an etch process.
- the at least one conformal dielectric layer 3 , 4 may be removed by an etch that is selective to the fin structure 5 , 10 and the dielectric layer 11 a , 11 b , 11 c (when present).
- the etch process may be a wet chemical etch, or a dry etch, such as reactive ion etch (RIE).
- RIE reactive ion etch
- the gate dielectric 12 may be formed on the fin structures, as well as the dielectric layer 11 a , 11 b , 11 c (when present).
- the gate dielectric is formed using a conformal deposition process.
- the gate dielectric may be composed of any dielectric material, such as an oxide, nitride or oxynitride material.
- the gate dielectric is a high-k dielectric material.
- the least one gate dielectric layer may be composed of a high-k oxide such as, for example, HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 and mixtures thereof.
- a high-k oxide such as, for example, HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 and mixtures thereof.
- high-k dielectric materials for the at least one gate dielectric include hafnium silicate, hafnium silicon oxynitride or combinations thereof.
- the gate dielectric 12 may be deposited using atomic layer deposition (ALD). In other embodiments, the gate dielectric 12 may be deposited using chemical vapor deposition methods, such as plasma enhanced chemical vapor deposition (PECVD). In one embodiment, the thickness of the at least one gate dielectric layer 12 is greater than 0.8 nm. More typically, the at least one gate dielectric layer 12 has a thickness ranging from about 1.0 nm to about 6.0 nm.
- conformal deposition of the gate dielectric 12 produces a vertical gate dielectric on the channel portion of the fin structures 10 in the vertical device region 20 for the VFETs. In some embodiments, the conformal deposition of the gate dielectric 12 produces a vertical portion of the gate dielectric that is present on the fin structure 5 and leads to a lateral portion of the gate dielectric for the LDMOS that is provided by the dielectric layer 11 a overlying the drift region 8 .
- FIG. 8 depicts forming the material layers for the gate conductors 14 for the LDMOS devices and the VFET devices.
- the material layers for the gate conductors 14 may include a work function metal.
- the work function metal may be selected to provide a p-type work function metal layer and an n-type work function metal layer.
- a “p-type work function metal layer” is a metal layer that effectuates a p-type threshold voltage shift.
- the work function of the p-type work function metal layer ranges from 4.9 eV to 5.2 eV.
- threshold voltage is the lowest attainable gate voltage that will turn on a semiconductor device, e.g., transistor, by making the channel of the device conductive.
- p-type threshold voltage shift as used herein means a shift in the Fermi energy of a p-type semiconductor device towards a valence band of silicon in the silicon containing substrate of the p-type semiconductor device.
- a “valence band” is the highest range of electron energies where electrons are normally present at absolute zero.
- the p-type work function metal layer may be composed of titanium and their nitrided/carbide.
- the p-type work function metal layer is composed of titanium nitride (TiN).
- the p-type work function metal layer may also be composed of TiAlN, Ru, Pt, Mo, Co and alloys and combinations thereof.
- an “n-type work function metal layer” is a metal layer that effectuates an n-type threshold voltage shift.
- “N-type threshold voltage shift” as used herein means a shift in the Fermi energy of an n-type semiconductor device towards a conduction band of silicon in a silicon-containing substrate of the n-type semiconductor device.
- the “conduction band” is the lowest lying electron energy band of the doped material that is not completely filled with electrons.
- the work function of the n-type work function metal layer ranges from 4.1 eV to 4.3 eV.
- the n-type work function metal layer is composed of at least one of TiAl, TaN, TiN, HfN, HfSi, or combinations thereof.
- the material layers for the gate conductors 14 for the LDMOS devices and the VFET devices may also include a metal, such as tungsten (W), tungsten nitride (WN) or combinations thereof.
- the material layers for the gate conductors 14 for the LDMOS devices and the VFET devices may be deposited by PVD, CVD or PE-CVD.
- the PVD methods for forming the gate conductors 14 may include plating, electroplating, electroless plating, sputtering and combinations thereof.
- following deposition the material layers for the gate conductor 14 may be recessed to a desired gate height using an etch process. This etch step may be performed using reactive ion etch (RIE).
- RIE reactive ion etch
- the gate height may be provided by material layers for the gate conductor 14 having a thickness in the range of about 2 nm to about 5 nm, or in the range of about 2 nm to about 3 nm.
- a dielectric spacer layer 16 may be blanket deposited atop the material layer for the gate conductors 14 for the LDMOS devices and the VFET devices.
- the dielectric spacer layer 16 may be composed of a low-k dielectric material.
- the dielectric spacer layer 16 may be composed of the same material as the dielectric layer 11 a that is formed on the drift region 8 in the lateral device region 10 and the dielectric layer 11 b that provides the first spacer in the vertical device region 15 , as described above with reference to FIG. 5 . Therefore, the above description of the dielectric layer 11 a , 11 b depicted in FIG. 5 is suitable for the second spacer layer 16 .
- the second spacer layer 16 may be an oxide.
- the second spacer layer 16 may be deposited using a chemical vapor deposition process, such as plasma enhanced chemical vapor deposition (PECVD). In other examples, the second spacer layer 16 may be deposited using chemical solution deposition or spin on deposition. In some embodiments, the height of the second spacer layer 16 may be reduced to expose a portion of the cap dielectric 2 that is present on the upper surfaces of the fin structures 5 , 10 . The height of the second spacer layer 16 may be reduced by etching, such as reactive ion etching (RIE).
- PECVD plasma enhanced chemical vapor deposition
- RIE reactive ion etching
- FIG. 9 depicting patterning the material layer 14 for the gate structures 21 a , 21 b for the LDMOS devices and the VFET devices.
- the gate structure 21 a , 21 b can be formed using deposition, photolithography and a selective etching process. Specifically, a pattern is produced by applying a photoresist to the surface to be etched; exposing the photoresist to a pattern of radiation; and then developing the pattern into the photoresist utilizing a resist developer. Once the patterning of the photoresist is completed, the sections covered by the photoresist are protected while the exposed regions are removed using a selective etching process that removes the unprotected regions.
- a selective etch process may remove the exposed portions of the second spacer layer 16 and the material layer for the gate conductors 14 , wherein the remaining portions of the second spacer layer 16 and the material layer for the gate conductors 14 define the geometry of the gate structures 21 a , 21 b .
- a dielectric layer may be present filling the space between the gates.
- FIG. 10 depicts forming an epitaxial semiconductor material 17 a on the at least one first fin structure 5 in the lateral device region 15 of the substrate 1 , and forming an epitaxial semiconductor material 17 b on the at least one second fin structure 10 in the vertical device region 20 of the substrate 1 .
- the epitaxial semiconductor material 17 a is typically grown after a dielectric (not depicted) is used to fill in between the gates.
- the epitaxial semiconductor material 17 a that is formed in the lateral device region 15 may provide the source region for the LDMOS device.
- the epitaxial semiconductor material 17 b that is formed in the vertical device region 20 may provide the second of a source or a drain region for the VFETS.
- the epitaxial semiconductor material 17 b when the diffused doped region 9 ′ is a source region, the epitaxial semiconductor material 17 b provides a drain region formed on the opposing surface, i.e., upper surface of the fin structure 10 .
- the epitaxial semiconductor material 17 b when the diffused doped region 9 ′ is a drain region, the epitaxial semiconductor material 17 b provides a source region is formed on the opposing surface, i.e., upper surface of the fin structure 10 .
- An epitaxial semiconductor material is formed using epitaxial growth.
- “Epitaxial growth and/or epitaxial deposition” means the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has substantially the same crystalline characteristics as the semiconductor material of the deposition surface.
- the term “epitaxial semiconductor material” denotes a semiconductor material that has substantially the same crystalline characteristics as the semiconductor material that it has been formed on, i.e., epitaxially formed on.
- the depositing atoms of an epitaxial deposition process arrive at the deposition surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface.
- An epitaxial material has substantially the same crystalline characteristics as the semiconductor material of the deposition surface.
- an epitaxial film deposited on a ⁇ 100 ⁇ crystal surface will take on a ⁇ 100 ⁇ orientation.
- the epitaxial deposition process may be carried out in the deposition chamber of a chemical vapor deposition (CVD) apparatus.
- CVD chemical vapor deposition
- the dielectric cap 2 may be removed to expose the semiconductor surface of the fin structures 5 , 10 that provides the deposition surface for the epitaxial deposition process.
- the dielectric cap 2 may be removed using a selective etch process, such as a wet chemical etch or reactive ion etch. Following removal of the dielectric cap 2 , the epitaxial semiconductor material 17 a , 17 b may be formed.
- the epitaxial semiconductor material 17 a , 17 b may be composed of silicon.
- Examples of silicon gas source for epitaxial deposition of a silicon containing drain region 17 a , 17 b may be selected from the group consisting of hexachlorodisilane (Si 2 Cl 6 ), tetrachlorosilane (SiCl 4 ), dichlorosilane (Cl 2 SiH 2 ), trichlorosilane (Cl 3 SiH), methylsilane ((CH 3 )SiH 3 ), dimethylsilane ((CH 3 ) 2 SiH 2 ), ethylsilane ((CH 3 CH 2 )SiH 3 ), methyldisilane ((CH 3 )Si 2 H 5 ), dimethyldisilane ((CH 3 ) 2 Si 2 H 4 ), hexamethyldisilane ((CH 3 )6Si 2 ) and combinations thereof.
- the epitaxial semiconductor material that provides the drain regions 15 a , 15 b may be composed of germanium.
- germanium gas source for epitaxial deposition may be selected from the group consisting of germane (GeH4), digermane (Ge 2 H 6 ), halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof.
- the epitaxial semiconductor material 17 a , 17 b may be doped to a n-type or p-type conductivity.
- the dopant for the epitaxial semiconductor material 17 a , 17 b may be introduced in-situ during the formation of the base material, i.e., epitaxial semiconductor material.
- Alkylphosphines include trimethylphosphine ((CH 3 ) 3 P), dimethylphosphine ((CH 3 ) 2 PH), triethylphosphine ((CH 3 CH 2 ) 3 P) and diethylphosphine ((CH 3 CH 2 ) 2 PH).
- the p-type gas dopant source for in-situ doping may include diborane.
- the epitaxial semiconductor material 17 a , 17 b may also be formed using gas phase doping or ion implantation.
- the epitaxial semiconductor material 17 a that is formed in the lateral device region 15 and the epitaxial semiconductor material 17 b that is formed in the vertical device region 20 may be composed of the same composition materials or different compositions materials, and may have the same conductivity type or a different conductivity type. Block masks may be used to independently process the lateral device region 15 and the vertical device region 20 .
- an interlevel dielectric layer (not shown) may be formed over the LDMOS device and the VFET device.
- the interlevel dielectric layer may be patterned and etched to provide via openings to the LDMOS device within the lateral device region 15 and the VFET in the vertical device region 20 .
- the openings may then be filled with an electrically conductive material, such as a metal, e.g., aluminum, copper, tungsten, titanium, silver, platinum, palladium, tantalum, gold, and combinations thereof, to provide contacts 19 a , 19 b , 19 c.
- the contacts to the VFET device in the vertical device region 20 may include a contact to the source region (not shown), a contact to the gate region (not shown), and a contact to the drain region 19 c.
- the contacts to the LDMOS device in the lateral device region 15 may include a contact 19 a to the source region, a contact 19 b to the drift region 8 , and a contact to the gate structure (not shown).
- FIG. 10 depicts one embodiment of an electrical device that can include a substrate 1 having a lateral device region 10 and a vertical device region 20 .
- the substrate 1 may be a bulk substrate.
- a first semiconductor device 100 a e.g., LDMOS 100 a
- the first semiconductor device 100 a may include a lateral channel portion that has a length L 1 that is parallel to an upper surface of the substrate 1 on which the first semiconductor device is formed.
- the lateral channel portion may be present in a drift region 8 of an LDMOS semiconductor device.
- the lateral device region 15 includes at least one first fin structure 5 that is a component of the first semiconductor device, e.g., LDMOS.
- the at least one fin structure 5 may provide a vertical channel portion having a length L 2 that is perpendicular to the upper surface of the substrate 1 .
- the vertical device region 20 includes at least one fin structure 10 that provides the vertical channel for the VFET.
- the vertical device region 20 does not include a lateral channel.
- the vertical field effect transistor (VFET) device that may be present in the vertical device region 20 includes a first dopant region 9 ′ for a first of a source region and a drain region provided by a doped portion of the substrate 1 , and a second doped region for a second of the source region and the drain region provided by an second epitaxial semiconductor material 17 b formed on an upper surface of said second fin structure.
- a first spacer is provided by a first dielectric layer 11 a that is present between the gate structure and the first doped region 9 ′, and a second spacer is provided by a dielectric layer 16 b atop the gate conductor 14 b for the gate structure of the VFET.
- the LDMOS device when the first device 100 a is provided by an LDMOS device, the LDMOS device includes a drift region 8 provided by a doped portion of the substrate 1 in the lateral device region 10 ; and a drift region gate dielectric 11 a formed on the drift region 8 of the substrate 1 .
- the drift region gate dielectric 11 a is the portion of the gate dielectric overlying the lateral length L 1 of the channel portion for the LDMOS device.
- the drift region gate dielectric 11 a , 11 c has multiple thickness regions, as depicted in FIG. 6 .
- the drift region gate dielectric 11 a is on a same level as the dielectric layer 11 b that provides the spacer for the VFET.
- the LDMOS device also includes a fin gate dielectric 12 present on the fin structure 5 that is present in the lateral device region 10 .
- the fin gate dielectric 12 is the portion of the gate dielectric that is present on the vertical channel portion of the LDMOS having the length L 2 .
- the LDMOS gate conductor 14 a is present on the drift region gate dielectric 11 a and the fin gate dielectric 12 .
- the LDMOS device that is present in the lateral device region 15 includes an epitaxial semiconductor material 17 a formed on an upper surface of the fin structure 5 .
- the epitaxial semiconductor material 17 a and the drift region 8 are typically doped to a first conductivity type, while the fin structure 5 that is present in the lateral device region 15 is doped to a second conductivity type.
- the epitaxial semiconductor material 17 a and the drift region 8 may be doped to an n-type conductivity, while the fin structure 5 is doped to a p-type conductivity.
- the epitaxial semiconductor material 17 a and the drift region 8 may be doped to a p-type conductivity, while the fin structure 5 is doped to an n-type conductivity.
- FIGS. 11A and 11B depict one embodiment of an LDMOS semiconductor device including a gate contact on an active region of the device, in which the drift region gate dielectric 11 a , i.e., drift oxide, has a single thickness.
- FIG. 11C depicts another embodiment of an LDMOS semiconductor device, in which the drift region gate dielectric 11 a , i.e., drift oxide, has two thicknesses.
- FIGS. 12A and 12B depict one embodiment of an LDMOS semiconductor device having a rectangular contact to the gate region G, in which the gate region contact is offset from the source and drift region contacts.
- FIGS. 14A-14C depict some embodiments of symmetrical LDMOS semiconductor devices.
- FIG. 14B depicts one embodiment of a symmetrical LDMOS device including two source contacts.
- FIG. 14C depicts one embodiment of a symmetrical LDMOS device including a single source contact.
- FIGS. 15A and 15B depict one embodiment of an LDMOS semiconductor device including an isolation region 21 in the drift region 8 .
- FIGS. 16A and 16B depict yet another embodiment of an LDMOS semiconductor device including an isolation region 21 in the drift region 9 , in which the gate contact is offset from the source contact and the diffusion region contact.
- FIGS. 11A-16B may be integrated into the process flow described above with reference to FIGS. 1-10 .
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/730,085 US10269657B2 (en) | 2016-04-15 | 2017-10-11 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/099,913 US9929144B2 (en) | 2016-04-15 | 2016-04-15 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US15/730,085 US10269657B2 (en) | 2016-04-15 | 2017-10-11 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/099,913 Continuation US9929144B2 (en) | 2016-04-15 | 2016-04-15 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
US20180033786A1 US20180033786A1 (en) | 2018-02-01 |
US10269657B2 true US10269657B2 (en) | 2019-04-23 |
Family
ID=60038497
Family Applications (8)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/099,913 Active US9929144B2 (en) | 2016-04-15 | 2016-04-15 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US15/457,492 Active US9875945B2 (en) | 2016-04-15 | 2017-03-13 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US15/637,261 Active US9960155B2 (en) | 2016-04-15 | 2017-06-29 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US15/674,002 Active US10128157B2 (en) | 2016-04-15 | 2017-08-10 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US15/730,085 Active US10269657B2 (en) | 2016-04-15 | 2017-10-11 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US15/800,803 Active US10347624B2 (en) | 2016-04-15 | 2017-11-01 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US15/821,345 Active US10128158B2 (en) | 2016-04-15 | 2017-11-22 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US16/102,955 Active US10720425B2 (en) | 2016-04-15 | 2018-08-14 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/099,913 Active US9929144B2 (en) | 2016-04-15 | 2016-04-15 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US15/457,492 Active US9875945B2 (en) | 2016-04-15 | 2017-03-13 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US15/637,261 Active US9960155B2 (en) | 2016-04-15 | 2017-06-29 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US15/674,002 Active US10128157B2 (en) | 2016-04-15 | 2017-08-10 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/800,803 Active US10347624B2 (en) | 2016-04-15 | 2017-11-01 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US15/821,345 Active US10128158B2 (en) | 2016-04-15 | 2017-11-22 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US16/102,955 Active US10720425B2 (en) | 2016-04-15 | 2018-08-14 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
Country Status (1)
Country | Link |
---|---|
US (8) | US9929144B2 (en) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10727339B2 (en) * | 2014-03-28 | 2020-07-28 | Intel Corporation | Selectively regrown top contact for vertical semiconductor devices |
US9929144B2 (en) * | 2016-04-15 | 2018-03-27 | International Business Machines Corporation | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
US11081398B2 (en) * | 2016-12-29 | 2021-08-03 | Globaleoundries U.S. Inc. | Method and structure to provide integrated long channel vertical FinFet device |
JP6677672B2 (en) * | 2017-03-24 | 2020-04-08 | 株式会社東芝 | Semiconductor device |
KR102465533B1 (en) * | 2017-11-21 | 2022-11-11 | 삼성전자주식회사 | Semiconductor devices having a vertical channel |
US10170577B1 (en) * | 2017-12-04 | 2019-01-01 | International Business Machines Corporation | Vertical transport FETs having a gradient threshold voltage |
US10418484B1 (en) * | 2018-03-14 | 2019-09-17 | Globalfoundries Inc. | Vertical field effect transistors incorporating U-shaped semiconductor bodies and methods |
US10374040B1 (en) * | 2018-06-12 | 2019-08-06 | Globalfoundries Inc. | Method to form low resistance contact |
US10741685B2 (en) * | 2018-09-21 | 2020-08-11 | Globalfoundries Inc. | Semiconductor devices having a fin channel arranged between source and drift regions and methods of manufacturing the same |
US10985272B2 (en) * | 2018-11-05 | 2021-04-20 | Samsung Electronics Co., Ltd. | Integrated circuit devices including vertical field-effect transistors |
CN111524961B (en) | 2019-02-28 | 2021-02-02 | 长江存储科技有限责任公司 | High voltage semiconductor device with increased breakdown voltage and method of manufacturing the same |
US11309405B2 (en) | 2019-06-18 | 2022-04-19 | Samsung Electronics Co., Ltd. | Vertical field effect transistor device having protruded shallow trench isolation and method for manufacturing the same |
US11257913B2 (en) | 2019-10-10 | 2022-02-22 | Samsung Electronics Co., Ltd. | Vertical field effect transistor with self-aligned contact structure and layout |
US11322602B2 (en) | 2019-10-11 | 2022-05-03 | Samsung Electronics Co., Ltd. | Vertical field-effect transistor (VFET) devices and methods of forming the same |
US11282752B2 (en) | 2020-02-05 | 2022-03-22 | Samsung Electronics Co., Ltd. | Method of forming vertical field-effect transistor devices having gate liner |
US11145550B2 (en) * | 2020-03-05 | 2021-10-12 | International Business Machines Corporation | Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistor |
CN113437148B (en) * | 2020-03-23 | 2023-10-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
CN113437149B (en) * | 2020-03-23 | 2023-10-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
US11430888B2 (en) | 2020-07-02 | 2022-08-30 | Micron Technology, Inc. | Integrated assemblies having transistors configured for high-voltage applications |
US11901240B2 (en) * | 2021-01-18 | 2024-02-13 | Samsung Electronics Co., Ltd. | Multi-fin vertical field effect transistor and single-fin vertical field effect transistor on a single integrated circuit chip |
CN113410305B (en) * | 2021-06-15 | 2023-07-04 | 西安微电子技术研究所 | Radiation-resistant reinforced LDMOS transistor and preparation method |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6876035B2 (en) | 2003-05-06 | 2005-04-05 | International Business Machines Corporation | High voltage N-LDMOS transistors having shallow trench isolation region |
US6903421B1 (en) | 2004-01-16 | 2005-06-07 | System General Corp. | Isolated high-voltage LDMOS transistor having a split well structure |
US8138544B2 (en) * | 2004-09-13 | 2012-03-20 | John James Seliskar | Castellated gate MOSFET tetrode capable of fully-depleted operation |
US8168490B2 (en) | 2008-12-23 | 2012-05-01 | Intersil Americas, Inc. | Co-packaging approach for power converters based on planar devices, structure and method |
US20120193707A1 (en) | 2011-01-28 | 2012-08-02 | Richtek Technology Corporation, R.O.C. | High voltage multigate device and manufacturing method thereof |
US8564031B2 (en) | 2011-01-27 | 2013-10-22 | Peking University | High voltage-resistant lateral double-diffused transistor based on nanowire device |
US20130307513A1 (en) | 2011-12-19 | 2013-11-21 | Han Wui Then | High voltage field effect transistors |
US9006811B2 (en) | 2012-12-03 | 2015-04-14 | Infineon Technologies Austria Ag | Semiconductor device including a fin and a drain extension region and manufacturing method |
US9041127B2 (en) | 2013-05-14 | 2015-05-26 | International Business Machines Corporation | FinFET device technology with LDMOS structures for high voltage operations |
US20150162439A1 (en) | 2013-12-06 | 2015-06-11 | Global Foundries Inc. | Semiconductor device including a transistor having a low doped drift region and method for the formation thereof |
US9929144B2 (en) * | 2016-04-15 | 2018-03-27 | International Business Machines Corporation | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
-
2016
- 2016-04-15 US US15/099,913 patent/US9929144B2/en active Active
-
2017
- 2017-03-13 US US15/457,492 patent/US9875945B2/en active Active
- 2017-06-29 US US15/637,261 patent/US9960155B2/en active Active
- 2017-08-10 US US15/674,002 patent/US10128157B2/en active Active
- 2017-10-11 US US15/730,085 patent/US10269657B2/en active Active
- 2017-11-01 US US15/800,803 patent/US10347624B2/en active Active
- 2017-11-22 US US15/821,345 patent/US10128158B2/en active Active
-
2018
- 2018-08-14 US US16/102,955 patent/US10720425B2/en active Active
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6876035B2 (en) | 2003-05-06 | 2005-04-05 | International Business Machines Corporation | High voltage N-LDMOS transistors having shallow trench isolation region |
US6903421B1 (en) | 2004-01-16 | 2005-06-07 | System General Corp. | Isolated high-voltage LDMOS transistor having a split well structure |
US8138544B2 (en) * | 2004-09-13 | 2012-03-20 | John James Seliskar | Castellated gate MOSFET tetrode capable of fully-depleted operation |
US8168490B2 (en) | 2008-12-23 | 2012-05-01 | Intersil Americas, Inc. | Co-packaging approach for power converters based on planar devices, structure and method |
US8564031B2 (en) | 2011-01-27 | 2013-10-22 | Peking University | High voltage-resistant lateral double-diffused transistor based on nanowire device |
US20120193707A1 (en) | 2011-01-28 | 2012-08-02 | Richtek Technology Corporation, R.O.C. | High voltage multigate device and manufacturing method thereof |
US20130307513A1 (en) | 2011-12-19 | 2013-11-21 | Han Wui Then | High voltage field effect transistors |
US9006811B2 (en) | 2012-12-03 | 2015-04-14 | Infineon Technologies Austria Ag | Semiconductor device including a fin and a drain extension region and manufacturing method |
US20150206975A1 (en) | 2012-12-03 | 2015-07-23 | Infineon Technologies Austria Ag | FIN-Type Semiconductor Device and Manufacturing Method |
US9041127B2 (en) | 2013-05-14 | 2015-05-26 | International Business Machines Corporation | FinFET device technology with LDMOS structures for high voltage operations |
US20150162439A1 (en) | 2013-12-06 | 2015-06-11 | Global Foundries Inc. | Semiconductor device including a transistor having a low doped drift region and method for the formation thereof |
US9929144B2 (en) * | 2016-04-15 | 2018-03-27 | International Business Machines Corporation | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor |
Non-Patent Citations (2)
Title |
---|
U.S. Office Action issued in U.S. Appl. No. 16/102,955, dated Jan. 24, 2019, pp. 1-29. |
Yoo, A. et al., "A Low-Voltage Lateral SJ-FINFET with Deep-Trench p-Drift Region" IEEE Electron Device Letters (Aug. 2009) pp. 858-860, vol. 30, No. 8. |
Also Published As
Publication number | Publication date |
---|---|
US9960155B2 (en) | 2018-05-01 |
US20170365529A1 (en) | 2017-12-21 |
US20170309616A1 (en) | 2017-10-26 |
US20170301590A1 (en) | 2017-10-19 |
US10347624B2 (en) | 2019-07-09 |
US20180033786A1 (en) | 2018-02-01 |
US20170301666A1 (en) | 2017-10-19 |
US10128158B2 (en) | 2018-11-13 |
US9875945B2 (en) | 2018-01-23 |
US20180082998A1 (en) | 2018-03-22 |
US10128157B2 (en) | 2018-11-13 |
US9929144B2 (en) | 2018-03-27 |
US10720425B2 (en) | 2020-07-21 |
US20180374841A1 (en) | 2018-12-27 |
US20180096901A1 (en) | 2018-04-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10720425B2 (en) | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor | |
US9583585B2 (en) | Gate structure integration scheme for fin field effect transistors | |
US9559119B2 (en) | High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process | |
US11374111B2 (en) | Forming replacement low-k spacer in tight pitch fin field effect transistors | |
US10347765B2 (en) | Split fin field effect transistor enabling back bias on fin type field effect transistors | |
US10916651B2 (en) | Body contact in fin field effect transistor design | |
US10304742B2 (en) | Forming insulator fin structure in isolation region to support gate structures | |
US11316015B2 (en) | Silicon germanium FinFET with low gate induced drain leakage current |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ANDERSON, BRENT A.;LOISEAU, ALAIN;SIGNING DATES FROM 20160414 TO 20160415;REEL/FRAME:043838/0925 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |