US10262706B1 - Anti-floating circuit - Google Patents

Anti-floating circuit Download PDF

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Publication number
US10262706B1
US10262706B1 US15/989,487 US201815989487A US10262706B1 US 10262706 B1 US10262706 B1 US 10262706B1 US 201815989487 A US201815989487 A US 201815989487A US 10262706 B1 US10262706 B1 US 10262706B1
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type transistor
coupled
circuit
signal
terminal
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US15/989,487
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Jung-Tsun Chuang
Shao-Chang Huang
Ching-Wen Chen
Chieh-Yao Chuang
Yu-Yen Lin
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Vanguard International Semiconductor Corp
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Vanguard International Semiconductor Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356086—Bistable circuits with additional means for controlling the main nodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Definitions

  • the invention relates to an anti-floating circuit, and more particularly to an anti-floating circuit which comprises a pull-high circuit and a pull-low circuit.
  • each integrated circuit operates according to at least one input signal.
  • the input signal is not the correct signal, a false action may be caused in the integrated circuit.
  • An anti-floating circuit generates a first output signal according to a first input signal in a first mode and sets the first output signal to a first predetermined value in a second mode.
  • the anti-floating circuit comprises a first pull-high circuit, a first pull-low circuit and a first control circuit.
  • the first pull-high circuit comprises a first P-type transistor and a second P-type transistor.
  • the first P-type transistor comprises a source coupled to a first power terminal and a drain outputting the first output signal.
  • the second P-type transistor comprises a source coupled to the first power terminal, a drain coupled to a gate of the first P-type transistor and a gate coupled to the drain of the first P-type transistor.
  • the first pull-low circuit comprises a first N-type transistor and a second N-type transistor.
  • the first N-type transistor comprises a gate receiving a first inverted signal and a source coupled to a second power terminal.
  • the second N-type transistor comprises a gate receiving the first input signal and a source coupled to the second power terminal.
  • the first control circuit is coupled between the first pull-high circuit and the first pull-low circuit. In the first mode, the first control circuit turns on a first path between the first P-type transistor and the first N-type transistor and a second path between the second P-type transistor and the second N-type transistor and turns off a third path between the first P-type transistor and the second power terminal. In the second mode, the first control circuit turns off the first and second paths and turns on the third path.
  • FIG. 1A is a schematic diagram of an exemplary embodiment of an anti-floating circuit according to various aspects of the present disclosure.
  • FIG. 1B is a schematic diagram of another exemplary embodiment of the anti-floating circuit according to various aspects of the present disclosure.
  • FIG. 2A is a schematic diagram of an exemplary embodiment of a signal generator circuit according to various aspects of the present disclosure.
  • FIG. 2B is a schematic diagram of another exemplary embodiment of the signal generator circuit according to various aspects of the present disclosure.
  • FIG. 3A is a schematic diagram of an exemplary embodiment of a pulse generator circuit according to various aspects of the present disclosure.
  • FIG. 3B is a schematic diagram of another exemplary embodiment of the pulse generator circuit according to various aspects of the present disclosure.
  • FIG. 4 is a schematic diagram of an exemplary embodiment of a delay circuit according to various aspects of the present disclosure.
  • FIG. 5 is a schematic diagram of another exemplary embodiment of the delay circuit according to various aspects of the present disclosure.
  • FIG. 1A is a schematic diagram of an exemplary embodiment of an anti-floating circuit according to various aspects of the present disclosure.
  • the anti-floating circuit 100 A comprises a signal generator circuit 110 and a core circuit 120 .
  • the signal generator circuit 110 is coupled between a power terminal PW 1 and a power terminal PW 2 and generates an output signal OUT 1 .
  • the signal generator circuit 110 is a level shifter. In this case, the signal generator circuit 110 transforms an input signal IN 1 to generate the output signal OUT 1 .
  • the output signal OUT 1 When the input signal IN 1 is at a first level, the output signal OUT 1 is at a second level. When the input signal IN 1 is at a third level, the output signal OUT 1 is at a fourth level.
  • the second level is higher than the first level.
  • the first level is approximately 3.3V and the second level is approximately 6V ⁇ 7V.
  • the third level may be equal to the fourth level, such as 0V.
  • the first level is higher than the second level and the fourth level is higher than the third level.
  • the fourth level may be higher than the first level.
  • the first level is about 3.3V and the fourth level is about 6V ⁇ 7V.
  • the second level may be equal to the third level, such as 0V.
  • the output signal OUT 1 when the input signal IN 1 is at a fifth level (e.g. a high level), the output signal OUT 1 is at a sixth level (e.g. a low level).
  • the output signal OUT 1 is at an eighth level (e.g. another high level).
  • the eighth level is higher than the fifth level.
  • the fifth level is about 3.3V and the eighth level is about 6V ⁇ 7V.
  • the sixth level may be equal to the seventh level, such as 0V.
  • the core circuit 120 is coupled between the power terminals PW 1 and PW 2 and receives the output signal OUT 1 .
  • the core circuit 120 is a non-volatile memory (NVM), but the disclosure is not limited thereto.
  • the core circuit 120 may be another memory circuit.
  • the core circuit 120 comprises a plurality of elements. For brevity, only the elements related to the invention are shown in FIG. 1A and the load 122 represent the other elements in the core circuit 120 .
  • the core circuit 120 at least comprises a switch 121 .
  • the switch 121 is coupled between the power terminal PW 1 and the load 122 .
  • the switch 122 determines whether to transmit the voltage of the power terminal PW 1 to the load 122 according to the output signal OUT 1 . For example, when the output signal OUT 1 is at a first state (e.g. a low level or a high level), the switch 121 transmits the voltage of the power terminal PW 1 to the load 122 . In this case, when the output signal OUT 1 is at a second state (e.g. a high level or a low level), the switch 121 does not transmit the voltage of the power terminal PW 1 to the load 122 .
  • a first state e.g. a low level or a high level
  • the switch 121 transmits the voltage of the power terminal PW 1 to the load 122 .
  • a second state e.g. a high level or a low level
  • the switch 121 is a P-type transistor, but the disclosure is not limited thereto. In other embodiment, the switch 121 may be coupled between the power terminal PW 2 and the load 122 and determines whether to transmit the voltage of the power terminal PW 2 to the load 122 according to the output signal OUT 1 .
  • the signal generator circuit 110 Since the signal generator circuit 110 generates the output signal OUT 1 according to the input signal IN 1 , when the input signal IN 1 is not ready to be transmitted to the signal generator circuit 110 , the output signal OUT 1 may be at a floating level. Therefore, because the output signal OUT 1 is at an error level, the switch 121 may be turned on causing a false action to occur in the core circuit 120 . Furthermore, while the switch 121 is turned on, if an electrostatic discharge (ESD) event occurs between the power terminals PW 1 and PW 2 , an ESD current passes from the switch 121 to the core circuit 120 , damaging the core circuit 120 .
  • ESD electrostatic discharge
  • the signal generator circuit 110 sets the level of the output signal OUT 1 to a predetermined level so that the switch 121 is turned off. Therefore, the false action does not occur in the core circuit 120 .
  • the switch 121 is turned off, the ESD current does not pass into the core circuit 120 .
  • the signal generator circuit 110 In a ready mode, since the input signal IN 1 has reached the target level, the signal generator circuit 110 generates the output signal OUT 1 according to the input signal IN 1 . In this mode, since the power terminals PW 1 and PW 2 have received corresponding operation voltages (e.g. 6V and 0V). Therefore, the signal generator circuit 110 sets the high level of the output signal OUT 1 so that it is equal to the voltage of the power terminal PW 1 and sets the low level of the output signal OUT 1 so that it is equal to the voltage of the power terminal PW 2 .
  • FIG. 1B is a schematic diagram of another exemplary embodiment of the anti-floating circuit according to various aspects of the present disclosure.
  • FIG. 1B is similar to FIG. 1A except that the anti-floating circuit 100 B shown in FIG. 1B further comprises a signal generator circuit 130 .
  • the signal generator circuit 130 is also coupled between the power terminals PW 1 and PW 2 and generates an output signal OUT 2 according to an input signal IN 2 .
  • the signal generator circuit 130 is a level shifter.
  • the signal generator circuit 130 transforms the input signal IN 2 to generate the output signal OUT 2 .
  • the input signal IN 1 may be the same as or different from the input signal IN 2 . Since the operation of the signal generator circuit 130 is the same as the operation of the signal generator circuit 110 , the description of the operation of the signal generator circuit 130 is omitted.
  • the core circuit 120 further comprises a switch 123 .
  • the switch 123 is coupled to the load 122 in series and determines whether to transmit the voltage of the power terminal PW 2 to the load 122 according to the output signal OUT 2 . For example, when the output signal OUT 2 is at a first state, such as a low level or a high level, the switch 123 does not transmit the power of the power terminal PW 2 to the load 122 . In this case, when the output signal OUT 2 is at a second state, such as a high level or a low level, the switch 123 transmits the voltage of the power terminal PW 2 to the load 122 .
  • the switch 123 is an N-type transistor, but the disclosure is not limited thereto. In other embodiments, the switch 123 is a P-type transistor.
  • the kind of switch 121 and the kind of switch 123 are the same.
  • the switches 121 and 123 are P-type transistors or N-type transistors.
  • the kind of switch 121 is different from the kind of switch 123 .
  • the switch 121 is a P-type transistor
  • the switch 123 is an N-type transistor.
  • the switch 123 is a P-type transistor.
  • the switch 123 is also turned on.
  • the switch 123 is also turned off.
  • the signal generator circuit 110 sets the level of the output signal OUT 1 to a first predetermined value and the signal generator circuit 130 sets the level of the output signal OUT 2 to a second predetermined value so that the switches 121 and 123 are turned off. Since the switches 121 and 123 are turned off, a false action does not occur in the core circuit 120 . Furthermore, since the switches 121 and 123 are turned off, an ESD current does not enter the core circuit 120 .
  • the signal generator circuits 110 and 130 When the input signal IN 1 reaches a first target level and the input signal IN 2 reaches a second target level, the signal generator circuits 110 and 130 operate in a ready mode. In this mode, the signal generator circuit 110 generates the output signal OUT 1 according to the input signal IN 1 to turn on or off the switch 122 . Additionally, the signal generator circuit 130 generates the output signal OUT 2 according to the input signal IN 2 to turn on or off the switch 123 . Since the signal generator circuits 110 and 130 generate the accurate output signals OUT 1 and OUT 2 , the false action does not occur in the core circuit 120 .
  • FIG. 2A is a schematic diagram of an exemplary embodiment of a signal generator circuit according to various aspects of the present disclosure.
  • the signal generator circuit 200 A comprises a pull-high circuit 210 , a control circuit 220 and a pull-low circuit 230 .
  • the pull-high circuit 210 comprises P-type transistors 211 and 212 .
  • the source of the P-type transistor 211 is coupled to the power terminal PW 1 .
  • the drain of the P-type transistor 212 is coupled to the gate of the P-type transistor 211 and the control circuit 220 .
  • the gate of the P-type transistor 212 is coupled to the drain of the P-type transistor 211 .
  • the output signal OUT shown in FIG. 2A serves as the output signal OUT 1 or OUT 2 .
  • the pull-low circuit 230 comprises N-type transistors 231 and 232 .
  • the gate of the N-type transistor 231 receives an inverted signal INB.
  • the source of the N-type transistor 231 is coupled to the power terminal PW 2 .
  • the drain of the N-type transistor 231 is coupled to the control circuit 220 .
  • the gate of the N-type transistor 232 receives the input signal IN.
  • the source of the N-type transistor 232 is coupled to the power terminal PW 2 .
  • the drain of the N-type transistor 232 is coupled to the control circuit 220 .
  • the inverted signal INB is an inversion signal of the input signal IN.
  • the signal generator circuit 200 A when the signal generator circuit 200 A serves as the signal generator circuit 110 or 130 shown in FIG. 1B , the input signal IN shown in FIG. 2A serves as the input signal IN 1 or IN 2 .
  • the signal generator circuit 200 A further comprises an inverter (not shown), which inverts the input signal IN to generate the inverted signal INB.
  • the inverter is disposed outside of the signal generator circuit 200 A.
  • the control circuit 220 is coupled between the pull-high circuit 210 and the pull-low circuit 230 .
  • a ready mode e.g. the input signal IN is ready
  • the control circuit 220 turns on a path PA 1 between the P-type transistor 211 and the N-type transistor 231 and a path PA 2 between the P-type transistor 212 and the N-type transistor 232 .
  • the control circuit 220 turns off a path PA 3 between the P-type transistor 211 and the power terminal PW 2 .
  • the signal generator circuit 200 A generates the output signal OUT according to the input signal IN.
  • the signal generator circuit 200 A When the input signal IN has not reached a target level or the input signal IN has not entered the signal generator circuit 200 A yet, the signal generator circuit 200 A operates in a not-ready mode. In the not-ready mode, the control circuit 220 turns off the paths PA 1 and PA 2 and turns on the path PA 3 . In this mode, the control circuit 220 sets the level of the output signal OUT to a predetermined value to turn off the switch (e.g. the switch 121 shown in FIG. 1A ) disposed in the core circuit to avoid a false action occurring in the core circuit.
  • the switch e.g. the switch 121 shown in FIG. 1A
  • the control circuit 220 comprises control elements 221 ⁇ 223 .
  • the control element 221 is coupled between the drain of the P-type transistor 211 and the drain of the N-type transistor 231 .
  • the control element 221 turns on or off the path PA 1 according to a pulse signal OS_NB.
  • a ready mode i.e. the input signal IN is ready
  • the pulse signal OS_NB is at a first level. Therefore, the control element 221 turns on the path PA 1 .
  • the pulse signal OS_NB is at a second level. Therefore, the control element 221 turns off the path PA 1 .
  • control element 221 is not limited in the present disclosure.
  • the control element 221 is an N-type transistor 224 .
  • the gate of the N-type transistor 224 receives the pulse signal OS_NB.
  • the drain of the N-type transistor 224 is coupled to the drain of the P-type transistor 211 .
  • the source of the N-type transistor 224 is coupled to the drain of the N-type transistor 231 .
  • the pulse signal OS_NB is at a high level so that the N-type transistor 224 is turned on. Therefore, the path PA 1 is turned on.
  • the pulse signal OS_NB is at a low level so that the N-type transistor 224 is turned off. Therefore, the path PA 1 is turned off.
  • the control element 221 is a P-type transistor.
  • the control element 222 is coupled between the drain of the P-type transistor 212 and the drain of the N-type transistor 232 .
  • the control element 222 controls the path PA 2 according to the pulse signal OS_NB.
  • the pulse signal OS_NB In the ready mode (e.g. the input signal IN has reached a target level), the pulse signal OS_NB is at a first level. Therefore, the control element 222 turns on the path PA 2 .
  • the pulse signal OS_NB is at a second level. Therefore, the control element 222 does not turn on the path PA 2 .
  • control element 222 is an N-type transistor 225 .
  • the gate of the N-type transistor 225 receives the pulse signal OS_NB.
  • the drain of the N-type transistor 225 is coupled to the drain of the P-type transistor 212 .
  • the source of the N-type transistor 225 is coupled to the drain of the N-type transistor 232 .
  • the pulse signal OS_NB is at a high level so that the N-type transistor 225 is turned on. Therefore, the path PA 2 is turned on.
  • the pulse signal OS_NB is at a low level so that the N-type transistor 225 is turned off. Therefore, the path PA 2 does not be turned on.
  • the control element is a P-type transistor.
  • the control element 223 is coupled between the gate of the P-type transistor 211 and the power terminal PW 2 .
  • the control element 223 turns on or off the path PA 3 between the P-type transistor 211 and the power terminal PW 2 according to the pulse signal OS_N.
  • the pulse signal OS_N is at a third level. Therefore, the control element 223 turns on the path PA 3 .
  • the pulse signal OS_N is at a fourth level. Therefore, the control element does not turn on the path PA 3 .
  • the control element 223 is an N-type transistor 226 .
  • the gate of the N-type transistor 226 receives the pulse signal OS_N.
  • the drain of the N-type transistor 226 is coupled to the gate of the P-type transistor 211 .
  • the source of the N-type transistor 226 is coupled to the power terminal PW 2 .
  • the pulse signal OS_N is at a low level so that the N-type transistor 226 is turned off. Therefore, the path PA 3 is turned off.
  • the control element 223 is a P-type transistor.
  • the pulse signal OS_N is opposite to the pulse signal OS_NB, but the disclosure is not limited thereto.
  • the pulse generator circuit 240 When the control elements 221 and 222 are N-type transistors and the control element 223 is a P-type transistor, the pulse generator circuit 240 generates a single pulse signal to control the control elements 221 ⁇ 223 . In another embodiment, when the control elements 221 and 222 are P-type transistors and the control element 223 is an N-type transistor, the pulse generator circuit 240 only generate a pulse signal to control the control elements 221 ⁇ 223 .
  • the pulse signals OS_NB and OS_N are generated by the pulse generator circuit 240 .
  • the pulse generator circuit 240 is coupled between the power terminals PW 1 and PW 2 .
  • the pulse generator circuit 240 generates the pulse signals OS_NB and OS_N according to the voltages of the power terminals PW 1 and PW 2 .
  • different pulse generator circuits may generate different pulse signals.
  • the number of pulse signal generated by the pulse generator circuit of the signal generator circuit 110 may be the same as or different from the number of pulse signal generated by the pulse generator circuit of the signal generator circuit 130 . Additionally, at least one of the pulse signals generated by the pulse generator circuit of the signal generator circuit 110 may be the same as or different from at least one of the pulse signal generated by the pulse generator circuit of the signal generator circuit 130 .
  • the operating configuration of the pulse generator circuit 240 is described in greater detail with reference to FIGS. 3A and 3B .
  • FIG. 2B is a schematic diagram of another exemplary embodiment of the signal generator circuit according to various aspects of the present disclosure.
  • FIG. 2B is similar to FIG. 2A except that the signal generator circuit 200 B shown in FIG. 2B further comprises an inverter 250 .
  • the inverter 250 is coupled between the power terminals PW 1 and PW 2 .
  • the input terminal of the inverter 250 is coupled to the drain of the P-type transistor 211 to receive the output signal OUT.
  • the output terminal of the inverter 250 is configured to provide the output signal OUTB.
  • the output signal OUTB is capable of serving as the output signal OUT 1 or OUT 2 in FIG. 1B .
  • the inverter 250 comprises a P-type transistor 251 and an N-type transistor 252 .
  • the source of the P-type transistor 251 is coupled to the power terminal PW 1 .
  • the gate of the P-type transistor 251 is coupled to the drain of the P-type transistor 211 .
  • the drain of the P-type transistor 251 provides the output signal OUTB.
  • the gate of the N-type transistor 252 is coupled to the drain of the P-type transistor 211 .
  • the drain of the N-type transistor 252 is coupled to the drain of the P-type transistor 251 .
  • the source of the N-type transistor 252 is coupled to the power terminal PW 2 .
  • FIG. 3A is a schematic diagram of an exemplary embodiment of a pulse generator circuit according to various aspects of the present disclosure.
  • the pulse generator circuit 300 A comprises a delay circuit 310 and a logic circuit 320 .
  • the delay circuit 310 and the logic circuit 320 are coupled between the power terminals PW 1 and PW 2 .
  • the voltages of the power terminals PW 1 and PW 2 are served as the operation voltages of the delay circuit 310 and the logic circuit 320 .
  • the delay circuit 310 delays the voltage of the power terminal PW 1 to generate a delay signal VD.
  • the logic circuit 320 generates the pulse signal OS_N according to the level V PW1 of the power terminal PW 1 and the delay signal VD. In this embodiment, when the level V PW1 of the power terminal PW 1 and the delay signal VD are at high levels, the pulse signal OS_N is at a low level. When one of the level V PW1 of the power terminal PW 1 and the delay signal VD is at a low level, the pulse signal OS_N is at a high level.
  • the logic circuit 320 is a NAND gate 321 .
  • One input terminal of the NAND gate 321 receives the level V PW1 of the power terminal PW 1 .
  • Another input terminal of the NAND gate 321 receives the delay signal VD.
  • the output terminal of the NAND gate 321 provides the pulse signal OS_N.
  • other circuit structure can serve as the logic circuit 320 .
  • the pulse generator circuit 300 A provides the pulse signal OS_N to the gates of the control elements 221 ⁇ 223 .
  • the pulse signal OS_N is at a high level to turn on the control elements 221 and 222 and turn off the control element 223 . Therefore, the paths PA 1 and PA 2 are turned on and the path PA 3 is turned off.
  • the signal generator circuit 200 A generates the output signal OUT according to the input signal IN.
  • the pulse signal OS_N is at a low level to turn off the control elements 221 and 222 and turn on the control element 223 . Therefore, the paths PA 1 and PA 2 are turned off and the path PA 3 is turned on.
  • the signal generator circuit 200 A sets the output signal OUT to a predetermined level to turn off the switch 121 of the core circuit 120 , avoiding a false action in the core circuit 120 and avoiding an ESD current entering the core circuit 120 .
  • the pulse generator circuit 240 when the control elements 221 and 222 are P-type transistors and the control element 223 is an N-type transistor, the pulse generator circuit 240 only generates a single pulse signal to control the control elements 221 ⁇ 223 simultaneously.
  • FIG. 3B is a schematic diagram of another exemplary embodiment of the pulse generator circuit according to various aspects of the present disclosure.
  • FIG. 3B is similar to FIG. 3A except that the pulse generator circuit 300 B of FIG. 3B further comprises an inverter 330 .
  • the inverter 330 inverts the pulse signal OS_N to generate the pulse signal OS_NB.
  • the pulse signal OS_N is at a high level and the pulse signal OS_NB is at a low level in a not-ready mode. Therefore, the paths PA 1 and PA 2 are turned off and the path PA 3 is turned on. In this mode, the signal generator circuit 200 A sets the level of the output signal OUT to a predetermined value.
  • the pulse signal OS_N is at a low level and the pulse signal OS_NB is at a high level. Therefore, the paths PA 1 and PA 2 are turned on and the path PA 3 is turned off. In this mode, the signal generator circuit 200 A generates the output signal OUT according to the input signal IN.
  • FIG. 4 is a schematic diagram of an exemplary embodiment of a delay circuit according to various aspects of the present disclosure.
  • the delay circuit 400 comprises inverters 410 and 430 and capacitors 420 and 440 .
  • the number of inverters is not limited in the present disclosure.
  • the delay circuit 400 comprises even inverters.
  • the inverter 410 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 411 and an output terminal 412 .
  • the input terminal 411 is coupled to the power terminal PW 1 .
  • the inverter 410 comprises a P-type transistor 413 and an N-type transistor 414 .
  • the gate of the P-type transistor 413 is coupled to the input terminal 411 .
  • the source of the P-type transistor 413 is coupled to the power terminal PW 1 .
  • the drain of the P-type transistor 413 is coupled to the output terminal 412 .
  • the gate of the N-type transistor 414 is coupled to the input terminal 411 .
  • the source of the N-type transistor 414 is coupled to the power terminal PW 2 .
  • the drain of the N-type transistor 414 is coupled to the output terminal 412 .
  • the capacitor 420 is coupled between the power terminal PW 1 and the output terminal 412 .
  • the capacitor 420 is a P-type transistor 421 .
  • the gate of the P-type transistor 421 is coupled to the output terminal 421 .
  • the drain and the source of the P-type transistor 421 are coupled to the power terminal PW 1 .
  • the inverter 430 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 431 and an output terminal 432 .
  • the input terminal 431 is coupled to the output terminal 412 .
  • the output terminal 432 is configured to provide the delay signal VD.
  • the inverter 430 comprises a P-type transistor 433 and an N-type transistor 434 .
  • the gate of the P-type transistor 433 is coupled to the input terminal 431 .
  • the source of the P-type transistor 433 is coupled to the power terminal PW 1 .
  • the drain of the P-type transistor 433 is coupled to the output terminal 432 .
  • the gate of the N-type transistor 434 is coupled to the input terminal 431 .
  • the source of the N-type transistor 434 is coupled to the power terminal PW 2 .
  • the drain of the N-type transistor 434 is coupled to the output terminal 432 .
  • the capacitor 440 is coupled between the power terminal PW 2 and the output terminal 432 .
  • the capacitor 440 is an N-type transistor 441 .
  • the gate of the N-type transistor 441 is coupled to the output terminal 432 .
  • the drain and the source of the N-type transistor 441 are coupled to the power terminal PW 2 .
  • FIG. 5 is a schematic diagram of another exemplary embodiment of the delay circuit according to various aspects of the present disclosure.
  • the delay circuit 500 at least comprises inverters 510 and 520 .
  • the inverter 510 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 511 and an output terminal 512 .
  • the input terminal 511 is coupled to the power terminal PW 1 .
  • the inverter 510 comprises a P-type transistor 513 and an N-type transistor 514 .
  • the gate of the P-type transistor 513 is coupled to the input terminal 511 .
  • the source of the P-type transistor 513 is coupled to the power terminal PW 1 .
  • the drain of the P-type transistor 513 is coupled to the output terminal 512 .
  • the gate of the N-type transistor 514 is coupled to the input terminal 511 .
  • the source of the N-type transistor 514 is coupled to the power terminal PW 2 .
  • the drain of the N-type transistor 514 is coupled to
  • the inverter 520 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 521 and an output terminal 522 .
  • the input terminal 521 is coupled to the output terminal 512 .
  • the inverter 520 comprises a P-type transistor 523 and an N-type transistor 524 .
  • the gate of the P-type transistor 523 is coupled to the input terminal 521 .
  • the source of the P-type transistor 523 is coupled to the power terminal PW 1 .
  • the drain of the P-type transistor 523 is coupled to the output terminal 522 .
  • the gate of the N-type transistor 524 is coupled to the input terminal 521 .
  • the source of the N-type transistor 524 is coupled to the power terminal PW 2 .
  • the drain of the N-type transistor 524 is coupled to the output terminal 522 .
  • the output terminal 522 is configured to provide the delay signal VD.
  • the delay circuit 500 further comprises inverters 530 and 540 .
  • the inverter 530 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 531 and an output terminal 532 .
  • the input terminal 531 is coupled to the output terminal 522 .
  • the inverter 530 comprises a P-type transistor 533 and an N-type transistor 534 .
  • the gate of the P-type transistor 533 is coupled to the input terminal 531 .
  • the source of the P-type transistor 533 is coupled to the power terminal PW 1 .
  • the drain of the P-type transistor 533 is coupled to the output terminal 532 .
  • the gate of the N-type transistor 534 is coupled to the output terminal 531 .
  • the source of the N-type transistor 534 is coupled to the power terminal PW 2 .
  • the drain of the N-type transistor 534 is coupled to the output terminal 532 .
  • the inverter 540 is coupled between the power terminals PW 1 and PW 2 and comprises an input terminal 541 and an output terminal 542 .
  • the input terminal 541 is coupled to the output terminal 532 .
  • the inverter 540 comprises a P-type transistor 543 and an N-type transistor 544 .
  • the gate of the P-type transistor 543 is coupled to the input terminal 541 .
  • the source of the P-type transistor 543 is coupled to the power terminal PW 1 .
  • the drain of the P-type transistor 543 is coupled to the output terminal 542 .
  • the gate of the N-type transistor 544 is coupled to the input terminal 541 .
  • the source of the N-type transistor 544 is coupled to the power terminal PW 2 .
  • the drain of the N-type transistor 544 is coupled to the output terminal 542 to provide the delay signal VD.
  • the number of inverters is not limited in the present disclosure.
  • the delay circuit 500 comprises even inverters.

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Abstract

An anti-floating circuit including a first pull-high circuit, a first pull-low circuit and a first control circuit is provided. The first pull-high circuit includes a first P-type transistor and a second P-type transistor and is coupled to a first power terminal. The first pull-low circuit includes a first N-type transistor and a second N-type transistor and is coupled to a second power terminal. A first path is between the first P-type transistor and the first N-type transistor. A second path is between the second P-type transistor and the second N-type transistor. A third path is between the first P-type transistor and the second power terminal. In the first mode, the control circuit turns on the first and second paths and turns off the third path. In the second mode, the control circuit turns off the first and second paths and turns on the third path.

Description

BACKGROUND OF THE INVENTION Field of the Invention
The invention relates to an anti-floating circuit, and more particularly to an anti-floating circuit which comprises a pull-high circuit and a pull-low circuit.
Description of the Related Art
With the development of technology, the size of integrated circuits has been greatly reduced. Generally, each integrated circuit operates according to at least one input signal. However, when the input signal is not the correct signal, a false action may be caused in the integrated circuit.
BRIEF SUMMARY OF THE INVENTION
An anti-floating circuit generates a first output signal according to a first input signal in a first mode and sets the first output signal to a first predetermined value in a second mode. The anti-floating circuit comprises a first pull-high circuit, a first pull-low circuit and a first control circuit. The first pull-high circuit comprises a first P-type transistor and a second P-type transistor. The first P-type transistor comprises a source coupled to a first power terminal and a drain outputting the first output signal. The second P-type transistor comprises a source coupled to the first power terminal, a drain coupled to a gate of the first P-type transistor and a gate coupled to the drain of the first P-type transistor. The first pull-low circuit comprises a first N-type transistor and a second N-type transistor. The first N-type transistor comprises a gate receiving a first inverted signal and a source coupled to a second power terminal. The second N-type transistor comprises a gate receiving the first input signal and a source coupled to the second power terminal. The first control circuit is coupled between the first pull-high circuit and the first pull-low circuit. In the first mode, the first control circuit turns on a first path between the first P-type transistor and the first N-type transistor and a second path between the second P-type transistor and the second N-type transistor and turns off a third path between the first P-type transistor and the second power terminal. In the second mode, the first control circuit turns off the first and second paths and turns on the third path.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1A is a schematic diagram of an exemplary embodiment of an anti-floating circuit according to various aspects of the present disclosure.
FIG. 1B is a schematic diagram of another exemplary embodiment of the anti-floating circuit according to various aspects of the present disclosure.
FIG. 2A is a schematic diagram of an exemplary embodiment of a signal generator circuit according to various aspects of the present disclosure.
FIG. 2B is a schematic diagram of another exemplary embodiment of the signal generator circuit according to various aspects of the present disclosure.
FIG. 3A is a schematic diagram of an exemplary embodiment of a pulse generator circuit according to various aspects of the present disclosure.
FIG. 3B is a schematic diagram of another exemplary embodiment of the pulse generator circuit according to various aspects of the present disclosure.
FIG. 4 is a schematic diagram of an exemplary embodiment of a delay circuit according to various aspects of the present disclosure.
FIG. 5 is a schematic diagram of another exemplary embodiment of the delay circuit according to various aspects of the present disclosure.
 DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated for illustrative purposes and not drawn to scale. The dimensions and the relative dimensions do not correspond to actual dimensions in the practice of the invention.
FIG. 1A is a schematic diagram of an exemplary embodiment of an anti-floating circuit according to various aspects of the present disclosure. The anti-floating circuit 100A comprises a signal generator circuit 110 and a core circuit 120. The signal generator circuit 110 is coupled between a power terminal PW1 and a power terminal PW2 and generates an output signal OUT1. In one embodiment, the signal generator circuit 110 is a level shifter. In this case, the signal generator circuit 110 transforms an input signal IN1 to generate the output signal OUT1.
When the input signal IN1 is at a first level, the output signal OUT1 is at a second level. When the input signal IN1 is at a third level, the output signal OUT1 is at a fourth level. In one embodiment, the second level is higher than the first level. For example, the first level is approximately 3.3V and the second level is approximately 6V˜7V. In addition, the third level may be equal to the fourth level, such as 0V.
In another embodiment, the first level is higher than the second level and the fourth level is higher than the third level. In this case, the fourth level may be higher than the first level. For example, the first level is about 3.3V and the fourth level is about 6V˜7V. Additionally, the second level may be equal to the third level, such as 0V.
In another embodiment, when the input signal IN1 is at a fifth level (e.g. a high level), the output signal OUT1 is at a sixth level (e.g. a low level). When the input signal IN1 is at a seventh level (e.g. another low level), the output signal OUT1 is at an eighth level (e.g. another high level). In this case, the eighth level is higher than the fifth level. For example, the fifth level is about 3.3V and the eighth level is about 6V˜7V. Furthermore, the sixth level may be equal to the seventh level, such as 0V.
The core circuit 120 is coupled between the power terminals PW1 and PW2 and receives the output signal OUT1. In one embodiment, the core circuit 120 is a non-volatile memory (NVM), but the disclosure is not limited thereto. In other embodiments, the core circuit 120 may be another memory circuit. Generally, the core circuit 120 comprises a plurality of elements. For brevity, only the elements related to the invention are shown in FIG. 1A and the load 122 represent the other elements in the core circuit 120.
As shown in FIG. 1A, the core circuit 120 at least comprises a switch 121. In this embodiment, the switch 121 is coupled between the power terminal PW1 and the load 122. The switch 122 determines whether to transmit the voltage of the power terminal PW1 to the load 122 according to the output signal OUT1. For example, when the output signal OUT1 is at a first state (e.g. a low level or a high level), the switch 121 transmits the voltage of the power terminal PW1 to the load 122. In this case, when the output signal OUT1 is at a second state (e.g. a high level or a low level), the switch 121 does not transmit the voltage of the power terminal PW1 to the load 122. In one embodiment, the switch 121 is a P-type transistor, but the disclosure is not limited thereto. In other embodiment, the switch 121 may be coupled between the power terminal PW2 and the load 122 and determines whether to transmit the voltage of the power terminal PW2 to the load 122 according to the output signal OUT1.
Since the signal generator circuit 110 generates the output signal OUT1 according to the input signal IN1, when the input signal IN1 is not ready to be transmitted to the signal generator circuit 110, the output signal OUT1 may be at a floating level. Therefore, because the output signal OUT1 is at an error level, the switch 121 may be turned on causing a false action to occur in the core circuit 120. Furthermore, while the switch 121 is turned on, if an electrostatic discharge (ESD) event occurs between the power terminals PW1 and PW2, an ESD current passes from the switch 121 to the core circuit 120, damaging the core circuit 120.
Therefore, in a not-ready mode, since the input signal IN1 has not reached a target level, the signal generator circuit 110 sets the level of the output signal OUT1 to a predetermined level so that the switch 121 is turned off. Therefore, the false action does not occur in the core circuit 120. In addition, in this mode, if an ESD event occurs between the power terminals PW1 and PW2, since the switch 121 is turned off, the ESD current does not pass into the core circuit 120.
In a ready mode, since the input signal IN1 has reached the target level, the signal generator circuit 110 generates the output signal OUT1 according to the input signal IN1. In this mode, since the power terminals PW1 and PW2 have received corresponding operation voltages (e.g. 6V and 0V). Therefore, the signal generator circuit 110 sets the high level of the output signal OUT1 so that it is equal to the voltage of the power terminal PW1 and sets the low level of the output signal OUT1 so that it is equal to the voltage of the power terminal PW2.
FIG. 1B is a schematic diagram of another exemplary embodiment of the anti-floating circuit according to various aspects of the present disclosure. FIG. 1B is similar to FIG. 1A except that the anti-floating circuit 100B shown in FIG. 1B further comprises a signal generator circuit 130. In this embodiment, the signal generator circuit 130 is also coupled between the power terminals PW1 and PW2 and generates an output signal OUT2 according to an input signal IN2. In one embodiment, the signal generator circuit 130 is a level shifter. In this case, the signal generator circuit 130 transforms the input signal IN2 to generate the output signal OUT2. In other embodiments, the input signal IN1 may be the same as or different from the input signal IN2. Since the operation of the signal generator circuit 130 is the same as the operation of the signal generator circuit 110, the description of the operation of the signal generator circuit 130 is omitted.
In this embodiment, the core circuit 120 further comprises a switch 123. The switch 123 is coupled to the load 122 in series and determines whether to transmit the voltage of the power terminal PW2 to the load 122 according to the output signal OUT2. For example, when the output signal OUT2 is at a first state, such as a low level or a high level, the switch 123 does not transmit the power of the power terminal PW2 to the load 122. In this case, when the output signal OUT2 is at a second state, such as a high level or a low level, the switch 123 transmits the voltage of the power terminal PW2 to the load 122. In one embodiment, the switch 123 is an N-type transistor, but the disclosure is not limited thereto. In other embodiments, the switch 123 is a P-type transistor.
In some embodiments, the kind of switch 121 and the kind of switch 123 are the same. For example, the switches 121 and 123 are P-type transistors or N-type transistors. In another embodiment, the kind of switch 121 is different from the kind of switch 123. For example, when the switch 121 is a P-type transistor, the switch 123 is an N-type transistor. When the switch 121 is an N-type transistor, the switch 123 is a P-type transistor. In other embodiments, when the switch 121 is turned on, the switch 123 is also turned on. When the switch 121 is turned off, the switch 123 is also turned off.
In a not-ready mode, since the input signals IN1 and IN2 has not reached the corresponding target levels, the signal generator circuit 110 sets the level of the output signal OUT1 to a first predetermined value and the signal generator circuit 130 sets the level of the output signal OUT2 to a second predetermined value so that the switches 121 and 123 are turned off. Since the switches 121 and 123 are turned off, a false action does not occur in the core circuit 120. Furthermore, since the switches 121 and 123 are turned off, an ESD current does not enter the core circuit 120.
When the input signal IN1 reaches a first target level and the input signal IN2 reaches a second target level, the signal generator circuits 110 and 130 operate in a ready mode. In this mode, the signal generator circuit 110 generates the output signal OUT1 according to the input signal IN1 to turn on or off the switch 122. Additionally, the signal generator circuit 130 generates the output signal OUT2 according to the input signal IN2 to turn on or off the switch 123. Since the signal generator circuits 110 and 130 generate the accurate output signals OUT1 and OUT2, the false action does not occur in the core circuit 120.
FIG. 2A is a schematic diagram of an exemplary embodiment of a signal generator circuit according to various aspects of the present disclosure. The signal generator circuit 200A comprises a pull-high circuit 210, a control circuit 220 and a pull-low circuit 230. The pull-high circuit 210 comprises P- type transistors 211 and 212. The source of the P-type transistor 211 is coupled to the power terminal PW1. The drain of the P-type transistor 212 is coupled to the gate of the P-type transistor 211 and the control circuit 220. The gate of the P-type transistor 212 is coupled to the drain of the P-type transistor 211. In one embodiment, when the signal generator circuit 200A serves as the signal generator circuit 110 or 130 shown in FIG. 1B, the output signal OUT shown in FIG. 2A serves as the output signal OUT1 or OUT2.
The pull-low circuit 230 comprises N- type transistors 231 and 232. The gate of the N-type transistor 231 receives an inverted signal INB. The source of the N-type transistor 231 is coupled to the power terminal PW2. The drain of the N-type transistor 231 is coupled to the control circuit 220. The gate of the N-type transistor 232 receives the input signal IN. The source of the N-type transistor 232 is coupled to the power terminal PW2. The drain of the N-type transistor 232 is coupled to the control circuit 220. In this embodiment, the inverted signal INB is an inversion signal of the input signal IN.
In one embodiment, when the signal generator circuit 200A serves as the signal generator circuit 110 or 130 shown in FIG. 1B, the input signal IN shown in FIG. 2A serves as the input signal IN1 or IN2. In other embodiments, the signal generator circuit 200A further comprises an inverter (not shown), which inverts the input signal IN to generate the inverted signal INB. In some embodiments, the inverter is disposed outside of the signal generator circuit 200A.
The control circuit 220 is coupled between the pull-high circuit 210 and the pull-low circuit 230. In a ready mode (e.g. the input signal IN is ready), the control circuit 220 turns on a path PA1 between the P-type transistor 211 and the N-type transistor 231 and a path PA2 between the P-type transistor 212 and the N-type transistor 232. At this time, the control circuit 220 turns off a path PA3 between the P-type transistor 211 and the power terminal PW2. In this mode, the signal generator circuit 200A generates the output signal OUT according to the input signal IN.
When the input signal IN has not reached a target level or the input signal IN has not entered the signal generator circuit 200A yet, the signal generator circuit 200A operates in a not-ready mode. In the not-ready mode, the control circuit 220 turns off the paths PA1 and PA2 and turns on the path PA3. In this mode, the control circuit 220 sets the level of the output signal OUT to a predetermined value to turn off the switch (e.g. the switch 121 shown in FIG. 1A) disposed in the core circuit to avoid a false action occurring in the core circuit.
In this embodiment, the control circuit 220 comprises control elements 221˜223. The control element 221 is coupled between the drain of the P-type transistor 211 and the drain of the N-type transistor 231. The control element 221 turns on or off the path PA1 according to a pulse signal OS_NB. In a ready mode (i.e. the input signal IN is ready), the pulse signal OS_NB is at a first level. Therefore, the control element 221 turns on the path PA1. In a not-ready mode (i.e. the input signal IN is not ready), the pulse signal OS_NB is at a second level. Therefore, the control element 221 turns off the path PA1.
The kind of control element 221 is not limited in the present disclosure. In this embodiment, the control element 221 is an N-type transistor 224. The gate of the N-type transistor 224 receives the pulse signal OS_NB. The drain of the N-type transistor 224 is coupled to the drain of the P-type transistor 211. The source of the N-type transistor 224 is coupled to the drain of the N-type transistor 231. In the ready mode, the pulse signal OS_NB is at a high level so that the N-type transistor 224 is turned on. Therefore, the path PA1 is turned on. In the not-ready mode, the pulse signal OS_NB is at a low level so that the N-type transistor 224 is turned off. Therefore, the path PA1 is turned off. In other embodiments, the control element 221 is a P-type transistor.
The control element 222 is coupled between the drain of the P-type transistor 212 and the drain of the N-type transistor 232. The control element 222 controls the path PA2 according to the pulse signal OS_NB. In the ready mode (e.g. the input signal IN has reached a target level), the pulse signal OS_NB is at a first level. Therefore, the control element 222 turns on the path PA2. In the not-ready mode (e.g. the input signal IN has not reached the target level), the pulse signal OS_NB is at a second level. Therefore, the control element 222 does not turn on the path PA2.
The kind of control element 222 is not limited in the present disclosure. In this embodiment, the control element 222 is an N-type transistor 225. The gate of the N-type transistor 225 receives the pulse signal OS_NB. The drain of the N-type transistor 225 is coupled to the drain of the P-type transistor 212. The source of the N-type transistor 225 is coupled to the drain of the N-type transistor 232. In the ready mode, the pulse signal OS_NB is at a high level so that the N-type transistor 225 is turned on. Therefore, the path PA2 is turned on. In the not-ready mode, the pulse signal OS_NB is at a low level so that the N-type transistor 225 is turned off. Therefore, the path PA2 does not be turned on. In some embodiments, the control element is a P-type transistor.
The control element 223 is coupled between the gate of the P-type transistor 211 and the power terminal PW2. The control element 223 turns on or off the path PA3 between the P-type transistor 211 and the power terminal PW2 according to the pulse signal OS_N. In a not-ready mode, the pulse signal OS_N is at a third level. Therefore, the control element 223 turns on the path PA3. In a ready mode, the pulse signal OS_N is at a fourth level. Therefore, the control element does not turn on the path PA3.
The invention does not limit the kind of the control element 223. In this embodiment, the control element 223 is an N-type transistor 226. The gate of the N-type transistor 226 receives the pulse signal OS_N. The drain of the N-type transistor 226 is coupled to the gate of the P-type transistor 211. The source of the N-type transistor 226 is coupled to the power terminal PW2. In the ready mode, the pulse signal OS_N is at a low level so that the N-type transistor 226 is turned off. Therefore, the path PA3 is turned off. In the not-ready mode, since the pulse signal OS_N is at a high level, the N-type transistor 226 is turned on. Therefore, the path PA3 is turned on. In some embodiments, the control element 223 is a P-type transistor.
In one embodiment, the pulse signal OS_N is opposite to the pulse signal OS_NB, but the disclosure is not limited thereto. When the control elements 221 and 222 are N-type transistors and the control element 223 is a P-type transistor, the pulse generator circuit 240 generates a single pulse signal to control the control elements 221˜223. In another embodiment, when the control elements 221 and 222 are P-type transistors and the control element 223 is an N-type transistor, the pulse generator circuit 240 only generate a pulse signal to control the control elements 221˜223.
In this embodiment, the pulse signals OS_NB and OS_N are generated by the pulse generator circuit 240. The pulse generator circuit 240 is coupled between the power terminals PW1 and PW2. The pulse generator circuit 240 generates the pulse signals OS_NB and OS_N according to the voltages of the power terminals PW1 and PW2. In some embodiments, different pulse generator circuits may generate different pulse signals.
Taking FIG. 1B as an example, the number of pulse signal generated by the pulse generator circuit of the signal generator circuit 110 may be the same as or different from the number of pulse signal generated by the pulse generator circuit of the signal generator circuit 130. Additionally, at least one of the pulse signals generated by the pulse generator circuit of the signal generator circuit 110 may be the same as or different from at least one of the pulse signal generated by the pulse generator circuit of the signal generator circuit 130. The operating configuration of the pulse generator circuit 240 is described in greater detail with reference to FIGS. 3A and 3B.
FIG. 2B is a schematic diagram of another exemplary embodiment of the signal generator circuit according to various aspects of the present disclosure. FIG. 2B is similar to FIG. 2A except that the signal generator circuit 200B shown in FIG. 2B further comprises an inverter 250. The inverter 250 is coupled between the power terminals PW1 and PW2. The input terminal of the inverter 250 is coupled to the drain of the P-type transistor 211 to receive the output signal OUT. The output terminal of the inverter 250 is configured to provide the output signal OUTB. In one embodiment, the output signal OUTB is capable of serving as the output signal OUT1 or OUT2 in FIG. 1B.
In this embodiment, the inverter 250 comprises a P-type transistor 251 and an N-type transistor 252. The source of the P-type transistor 251 is coupled to the power terminal PW1. The gate of the P-type transistor 251 is coupled to the drain of the P-type transistor 211. The drain of the P-type transistor 251 provides the output signal OUTB. The gate of the N-type transistor 252 is coupled to the drain of the P-type transistor 211. The drain of the N-type transistor 252 is coupled to the drain of the P-type transistor 251. The source of the N-type transistor 252 is coupled to the power terminal PW2.
FIG. 3A is a schematic diagram of an exemplary embodiment of a pulse generator circuit according to various aspects of the present disclosure. The pulse generator circuit 300A comprises a delay circuit 310 and a logic circuit 320. The delay circuit 310 and the logic circuit 320 are coupled between the power terminals PW1 and PW2. The voltages of the power terminals PW1 and PW2 are served as the operation voltages of the delay circuit 310 and the logic circuit 320.
The delay circuit 310 delays the voltage of the power terminal PW1 to generate a delay signal VD. The logic circuit 320 generates the pulse signal OS_N according to the level VPW1 of the power terminal PW1 and the delay signal VD. In this embodiment, when the level VPW1 of the power terminal PW1 and the delay signal VD are at high levels, the pulse signal OS_N is at a low level. When one of the level VPW1 of the power terminal PW1 and the delay signal VD is at a low level, the pulse signal OS_N is at a high level.
In one embodiment, the logic circuit 320 is a NAND gate 321. One input terminal of the NAND gate 321 receives the level VPW1 of the power terminal PW1. Another input terminal of the NAND gate 321 receives the delay signal VD. The output terminal of the NAND gate 321 provides the pulse signal OS_N. In other embodiments, other circuit structure can serve as the logic circuit 320.
Taking FIG. 2A as an example, assume that the control elements 221 and 222 are N-type transistors and the control element 223 is a P-type transistor. In this case, the pulse generator circuit 300A provides the pulse signal OS_N to the gates of the control elements 221˜223. In a ready mode, the pulse signal OS_N is at a high level to turn on the control elements 221 and 222 and turn off the control element 223. Therefore, the paths PA1 and PA2 are turned on and the path PA3 is turned off. At this time, the signal generator circuit 200A generates the output signal OUT according to the input signal IN. In a not-ready mode, the pulse signal OS_N is at a low level to turn off the control elements 221 and 222 and turn on the control element 223. Therefore, the paths PA1 and PA2 are turned off and the path PA3 is turned on. At this time, the signal generator circuit 200A sets the output signal OUT to a predetermined level to turn off the switch 121 of the core circuit 120, avoiding a false action in the core circuit 120 and avoiding an ESD current entering the core circuit 120. In other embodiments, when the control elements 221 and 222 are P-type transistors and the control element 223 is an N-type transistor, the pulse generator circuit 240 only generates a single pulse signal to control the control elements 221˜223 simultaneously.
FIG. 3B is a schematic diagram of another exemplary embodiment of the pulse generator circuit according to various aspects of the present disclosure. FIG. 3B is similar to FIG. 3A except that the pulse generator circuit 300B of FIG. 3B further comprises an inverter 330. The inverter 330 inverts the pulse signal OS_N to generate the pulse signal OS_NB. Taking FIG. 2A as an example, the pulse signal OS_N is at a high level and the pulse signal OS_NB is at a low level in a not-ready mode. Therefore, the paths PA1 and PA2 are turned off and the path PA3 is turned on. In this mode, the signal generator circuit 200A sets the level of the output signal OUT to a predetermined value. In a ready mode, the pulse signal OS_N is at a low level and the pulse signal OS_NB is at a high level. Therefore, the paths PA1 and PA2 are turned on and the path PA3 is turned off. In this mode, the signal generator circuit 200A generates the output signal OUT according to the input signal IN.
FIG. 4 is a schematic diagram of an exemplary embodiment of a delay circuit according to various aspects of the present disclosure. The delay circuit 400 comprises inverters 410 and 430 and capacitors 420 and 440. The number of inverters is not limited in the present disclosure. In one embodiment, the delay circuit 400 comprises even inverters.
In this embodiment, the inverter 410 is coupled between the power terminals PW1 and PW2 and comprises an input terminal 411 and an output terminal 412. The input terminal 411 is coupled to the power terminal PW1. In one embodiment, the inverter 410 comprises a P-type transistor 413 and an N-type transistor 414. The gate of the P-type transistor 413 is coupled to the input terminal 411. The source of the P-type transistor 413 is coupled to the power terminal PW1. The drain of the P-type transistor 413 is coupled to the output terminal 412. The gate of the N-type transistor 414 is coupled to the input terminal 411. The source of the N-type transistor 414 is coupled to the power terminal PW2. The drain of the N-type transistor 414 is coupled to the output terminal 412.
The capacitor 420 is coupled between the power terminal PW1 and the output terminal 412. In this embodiment, the capacitor 420 is a P-type transistor 421. The gate of the P-type transistor 421 is coupled to the output terminal 421. The drain and the source of the P-type transistor 421 are coupled to the power terminal PW1.
The inverter 430 is coupled between the power terminals PW1 and PW2 and comprises an input terminal 431 and an output terminal 432. The input terminal 431 is coupled to the output terminal 412. The output terminal 432 is configured to provide the delay signal VD. In one embodiment, the inverter 430 comprises a P-type transistor 433 and an N-type transistor 434. The gate of the P-type transistor 433 is coupled to the input terminal 431. The source of the P-type transistor 433 is coupled to the power terminal PW1. The drain of the P-type transistor 433 is coupled to the output terminal 432. The gate of the N-type transistor 434 is coupled to the input terminal 431. The source of the N-type transistor 434 is coupled to the power terminal PW2. The drain of the N-type transistor 434 is coupled to the output terminal 432.
The capacitor 440 is coupled between the power terminal PW2 and the output terminal 432. In this embodiment, the capacitor 440 is an N-type transistor 441. The gate of the N-type transistor 441 is coupled to the output terminal 432. The drain and the source of the N-type transistor 441 are coupled to the power terminal PW2.
FIG. 5 is a schematic diagram of another exemplary embodiment of the delay circuit according to various aspects of the present disclosure. The delay circuit 500 at least comprises inverters 510 and 520. The inverter 510 is coupled between the power terminals PW1 and PW2 and comprises an input terminal 511 and an output terminal 512. The input terminal 511 is coupled to the power terminal PW1. In one embodiment, the inverter 510 comprises a P-type transistor 513 and an N-type transistor 514. The gate of the P-type transistor 513 is coupled to the input terminal 511. The source of the P-type transistor 513 is coupled to the power terminal PW1. The drain of the P-type transistor 513 is coupled to the output terminal 512. The gate of the N-type transistor 514 is coupled to the input terminal 511. The source of the N-type transistor 514 is coupled to the power terminal PW2. The drain of the N-type transistor 514 is coupled to the output terminal 512.
The inverter 520 is coupled between the power terminals PW1 and PW2 and comprises an input terminal 521 and an output terminal 522. The input terminal 521 is coupled to the output terminal 512. In one embodiment, the inverter 520 comprises a P-type transistor 523 and an N-type transistor 524. The gate of the P-type transistor 523 is coupled to the input terminal 521. The source of the P-type transistor 523 is coupled to the power terminal PW1. The drain of the P-type transistor 523 is coupled to the output terminal 522. The gate of the N-type transistor 524 is coupled to the input terminal 521. The source of the N-type transistor 524 is coupled to the power terminal PW2. The drain of the N-type transistor 524 is coupled to the output terminal 522. In one embodiment, when the delay circuit 500 only comprises the inverters 510 and 520, the output terminal 522 is configured to provide the delay signal VD.
In other embodiments, the delay circuit 500 further comprises inverters 530 and 540. The inverter 530 is coupled between the power terminals PW1 and PW2 and comprises an input terminal 531 and an output terminal 532. The input terminal 531 is coupled to the output terminal 522. In one embodiment, the inverter 530 comprises a P-type transistor 533 and an N-type transistor 534. The gate of the P-type transistor 533 is coupled to the input terminal 531. The source of the P-type transistor 533 is coupled to the power terminal PW1. The drain of the P-type transistor 533 is coupled to the output terminal 532. The gate of the N-type transistor 534 is coupled to the output terminal 531. The source of the N-type transistor 534 is coupled to the power terminal PW2. The drain of the N-type transistor 534 is coupled to the output terminal 532.
The inverter 540 is coupled between the power terminals PW1 and PW2 and comprises an input terminal 541 and an output terminal 542. The input terminal 541 is coupled to the output terminal 532. In one embodiment, the inverter 540 comprises a P-type transistor 543 and an N-type transistor 544. The gate of the P-type transistor 543 is coupled to the input terminal 541. The source of the P-type transistor 543 is coupled to the power terminal PW1. The drain of the P-type transistor 543 is coupled to the output terminal 542. The gate of the N-type transistor 544 is coupled to the input terminal 541. The source of the N-type transistor 544 is coupled to the power terminal PW2. The drain of the N-type transistor 544 is coupled to the output terminal 542 to provide the delay signal VD. The number of inverters is not limited in the present disclosure. In one embodiment, the delay circuit 500 comprises even inverters.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). For example, it should be understood that the system, device and method may be realized in software, hardware, firmware, or any combination thereof. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (20)

What is claimed is:
1. An anti-floating circuit generating a first output signal according to a first input signal in a first mode and setting the first output signal to a first predetermined value in a second mode, comprising:
a first pull-high circuit comprising:
a first P-type transistor comprising a source coupled to a first power terminal and a drain outputting the first output signal; and
a second P-type transistor comprising a source coupled to the first power terminal, a drain coupled to a gate of the first P-type transistor and a gate coupled to the drain of the first P-type transistor;
a first pull-low circuit comprising:
a first N-type transistor comprising a gate receiving a first inverted signal and a source coupled to a second power terminal; and
a second N-type transistor comprising a gate receiving the first input signal and a source coupled to the second power terminal; and
a first control circuit coupled between the first pull-high circuit and the first pull-low circuit,
wherein in the first mode, the first control circuit turns on a first path between the first P-type transistor and the first N-type transistor and a second path between the second P-type transistor and the second N-type transistor and turns off a third path between the first P-type transistor and the second power terminal, and
wherein in the second mode, the first control circuit turns off the first and second paths and turns on the third path.
2. The anti-floating circuit as claimed in claim 1, wherein in the first mode, when the first input signal is at a first level, the first output signal is at a second level, and when the first input signal is at a third level, the first output signal is at a fourth level, and wherein the first level is lower than the second level, and the third level is equal to the fourth level.
3. The anti-floating circuit as claimed in claim 1, wherein in the first mode, when the first input signal is at a first level, the first output signal is at a second level, and when the first input signal is at a third level, the first output signal is at a fourth level, and wherein the first level is lower than the fourth level and second level is equal to the third level.
4. The anti-floating circuit as claimed in claim 1, wherein the first input signal is opposite to the first inverted signal.
5. The anti-floating circuit as claimed in claim 1, wherein the first control circuit comprises:
a first control element coupled between the first P-type transistor and the first N-type transistor;
a second control element coupled between the second P-type transistor and the second N-type transistor; and
a third control element coupled between the first P-type transistor and the second power terminal,
wherein in the first mode, the first control element turns on the first path according to a first pulse signal, the second control element turns on the second path according to the first pulse signal, and the third control element turns off the third path according to a second pulse signal,
wherein in the second mode, the first control element turns off the first path according to the first pulse signal, the second control element turns off the second path according to the first pulse signal and the third control element turns on the third path according to the second pulse signal.
6. The anti-floating circuit as claimed in claim 5, wherein the first control element is a third N-type transistor, the second control element is a fourth N-type transistor and the third control element is a fifth N-type transistor.
7. The anti-floating circuit as claimed in claim 6,
wherein the third N-type transistor comprises a drain coupled to the drain of the first P-type transistor, a source coupled to the drain of the first N-type transistor and a gate receiving the first pulse signal,
wherein the fourth N-type transistor comprises a source coupled to the drain of the second N-type transistor and a gate receiving the first pulse signal, and
wherein the fifth N-type transistor comprises a drain coupled to the gate of the first P-type transistor, a source coupled to the second power terminal and a gate receiving the second pulse signal.
8. The anti-floating circuit as claimed in claim 5, further comprising:
a pulse generator circuit configured to generate the first and second pulse signals, wherein the first pulse signal is opposite to the second pulse signal.
9. The anti-floating circuit as claimed in claim 8, wherein the pulse generator circuit comprises:
a delay circuit coupled to the first power terminal to generate a delay signal; and
a logic circuit generating the second pulse signal according to a voltage level of the first power terminal and the delay signal.
10. The anti-floating circuit as claimed in claim 9, wherein the delay circuit comprises:
a first inverter coupled between the first and second power terminals and comprising a first input terminal and a first output terminal, wherein the first input terminal is coupled to the first power terminal;
a first capacitor coupled between the first power terminal and the first output terminal;
a second inverter coupled between the first and second power terminals and comprising a second input terminal and a second output terminal, wherein the second input terminal is coupled to the first output terminal, and the second output terminal is coupled to the logic circuit; and
a second capacitor coupled between the second output terminal and the second power terminal.
11. The anti-floating circuit as claimed in claim 10, wherein the first capacitor is a third P-type transistor and the second capacitor is a third N-type transistor.
12. The anti-floating circuit as claimed in claim 11, wherein a gate of the third P-type transistor is coupled to the first output terminal, a drain and a source of the third P-type transistor are coupled to the first power terminal, a gate of the third N-type transistor is coupled to the second output terminal and a drain and a source of the third N-type transistor are coupled to the second power terminal.
13. The anti-floating circuit as claimed in claim 9, wherein the delay circuit comprises:
a first inverter coupled between the first and second power terminal and comprising a first input terminal and a first output terminal, wherein the first input terminal is coupled to the first power terminal; and
a second inverter coupled between the first and second power terminals and comprising a second input terminal and a second output terminal, wherein the second input terminal is coupled to the first output terminal and the second output terminal is coupled to the logic circuit.
14. The anti-floating circuit as claimed in claim 9, wherein the logic circuit is a NAND gate.
15. The anti-floating circuit as claimed in claim 9, wherein the pulse generator circuit further comprises:
an inverter circuit inverting the second pulse signal to generate the first pulse signal.
16. The anti-floating circuit as claimed in claim 1, further comprising:
a core circuit coupled between the first and second power terminals; and
a switch transmitting a voltage of the first power terminal or a voltage of the second power terminal to the core circuit according to the first output signal.
17. The anti-floating circuit as claimed in claim 1, further comprising:
an inverter inverting the first output signal to generate a second output signal;
a core circuit coupled between the first and second power terminals; and
a switch transmitting a voltage of the first power terminal or a voltage of the second power terminal to the core circuit according to the second output signal.
18. The anti-floating circuit as claimed in claim 1, further comprising:
a second pull-high circuit comprising:
a third P-type transistor comprising a source coupled to the first power terminal and a drain outputting a second output signal; and
a fourth P-type transistor comprising a source coupled to the first power terminal, a drain coupled to a gate of the third P-type transistor and a gate coupled to the drain of the third P-type transistor;
a second pull-low circuit comprising:
a third N-type transistor comprising a gate receiving a second inverted signal and a source coupled to the second power terminal; and
a fourth N-type transistor comprising a gate receiving a second input signal and a source coupled to the second power terminal; and
a second control circuit coupled between the second pull-high circuit and the second pull-low circuit,
wherein in the first mode, the second control circuit turns on a fourth path between the third P-type transistor and the third N-type transistor and a fifth path between the fourth P-type transistor and the fourth N-type transistor and turns off a sixth path between the third P-type transistor and the second power terminal, and
wherein in the second mode, the second control circuit turns off the fourth and fifth paths and turns on the sixth path.
19. The anti-floating circuit as claimed in claim 18, wherein the second control circuit comprises:
a first control element coupled between the third P-type transistor and the third N-type transistor;
a second control element coupled between the fourth P-type transistor and the fourth N-type transistor; and
a third control element coupled between the third P-type transistor and the second power terminal,
wherein in the first mode, the first control element turns on the fourth path according to a third pulse signal, the second control element turns on the fifth path according to the third pulse signal, and the third control element turns off the sixth path according to a fourth pulse signal, and
wherein in the second mode, the first control element turns off the fourth path according to the third pulse signal, the second control element turns off the fifth path according to the third pulse signal, and the third control element turns on the sixth path according to the fourth pulse signal.
20. The anti-floating circuit as claimed in claim 19, further comprising:
a core circuit coupled between the first and second power terminals;
a first switch transmitting a voltage of the first power terminal to the core circuit according to the first output signal; and
a second switch transmitting a voltage of the second power terminal to the core circuit according to the second output signal.
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Citations (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444408A (en) * 1993-12-13 1995-08-22 Micron Technology, Inc. Active pull-up voltage spike reducer
US5952847A (en) * 1996-06-25 1999-09-14 Actel Corporation Multiple logic family compatible output driver
US20020097606A1 (en) * 2001-01-24 2002-07-25 Takayuki Kurokawa Semiconductor circuit
US20030179032A1 (en) * 2002-03-25 2003-09-25 Tomohiro Kaneko Level shifter circuit and semiconductor device including the same
US7196547B2 (en) * 2004-06-08 2007-03-27 Nec Electronics Corporation Level shifter and buffer circuit
US20070070780A1 (en) * 2005-09-29 2007-03-29 Hynix Semiconductor Inc. Output driving device
US20080238523A1 (en) * 2007-03-31 2008-10-02 Thorp Tyler J Level shifter circuit incorporating transistor snap-back protection
US20080238522A1 (en) * 2007-03-31 2008-10-02 Thorp Tyler J Method for incorporating transistor snap-back protection in a level shifter circuit
US7446566B1 (en) * 2007-10-16 2008-11-04 Freescale Semiconductor, Inc. Level shifter
US20090096484A1 (en) * 2007-10-12 2009-04-16 Mediatek Inc. Level shifters
US7733126B1 (en) * 2009-03-31 2010-06-08 Freescale Semiconductor, Inc. Negative voltage generation
US7755392B1 (en) * 2009-05-21 2010-07-13 Ememory Technology Inc. Level shift circuit without high voltage stress of transistors and operating at low voltages
US7834662B2 (en) * 2006-12-13 2010-11-16 Apple Inc. Level shifter with embedded logic and low minimum voltage
US7915920B2 (en) * 2006-12-13 2011-03-29 Apple Inc. Low latency, power-down safe level shifter
US7994821B1 (en) * 2010-04-02 2011-08-09 Altera Corporation Level shifter circuits and methods
US8102728B2 (en) * 2009-04-07 2012-01-24 Apple Inc. Cache optimizations using multiple threshold voltage transistors
US8319540B2 (en) * 2010-07-01 2012-11-27 Integrated Device Technology, Inc. Apparatuses and methods for a voltage level shifting
US8384431B2 (en) * 2010-12-09 2013-02-26 Integrated Device Technology, Inc. Voltage level shifting apparatuses and methods
US8406068B2 (en) * 2009-09-18 2013-03-26 Stmicroelectronics S.R.L. Voltage shifter for high voltage operations
US20130250704A1 (en) * 2012-03-22 2013-09-26 Elpida Memory Inc. Semiconductor device having level shifter
US8575962B2 (en) * 2011-08-29 2013-11-05 Freescale Semiconductor, Inc. Integrated circuit having critical path voltage scaling and method therefor
US8587359B2 (en) * 2009-08-07 2013-11-19 Atmel Corporation Level shifter with output latch
US8604868B2 (en) * 2011-04-01 2013-12-10 Stmicroelectronics S.R.L. Dynamic biasing circuit for a protection stage using low voltage transistors
US20140145777A1 (en) * 2012-11-29 2014-05-29 Infineon Technologies Austria Ag System and Method for a Level Shifter
US20140197872A1 (en) * 2013-01-17 2014-07-17 Stmicroelectronics S.R.L. Level shifter device
US20140266384A1 (en) * 2013-03-14 2014-09-18 Taiwna Semiconductor Manufacturing Co. Ltd. Systems and method for level shifters
US20140269112A1 (en) * 2013-03-15 2014-09-18 Qualcomm Incorporated Apparatus and method for writing data to memory array circuits
US9191007B1 (en) * 2014-06-20 2015-11-17 Freescale Semiconductor, Inc. Latching level shifter and method of operation
US20150365085A1 (en) * 2014-06-17 2015-12-17 Boe Technology Group Co., Ltd. Dual Pull-Down Control Module, Shift Register Unit, Gate Driver, and Display Panel
US20160042794A1 (en) * 2014-08-07 2016-02-11 Macronix International Co., Ltd. Level shifter and decoder for memory
US20160118987A1 (en) * 2014-10-28 2016-04-28 Lattice Semiconductor Corporation Level Shifter With Low Static Power Dissipation
US20160118985A1 (en) * 2013-06-11 2016-04-28 Agency For Science, Technology And Research Circuit arrangement and method of operating the same
US20160329887A1 (en) * 2015-05-06 2016-11-10 SK Hynix Inc. Transmitting/receiving system
US9595967B2 (en) * 2015-02-20 2017-03-14 Kabushiki Kaisha Toshiba Level shift circuit and driver circuit
US20170193885A1 (en) * 2016-01-04 2017-07-06 Boe Technology Group Co., Ltd. Shift register unit, driving method, gate driving circuit and display device
US9768779B2 (en) * 2015-06-05 2017-09-19 Qualcomm Incorporated Voltage level shifters employing preconditioning circuits, and related systems and methods
US20170364170A1 (en) * 2015-08-20 2017-12-21 Boe Technology Group Co., Ltd. Shift Register Unit, Drive Method Thereof, Gate Drive Device, and Display Device
US20180090924A1 (en) 2016-09-26 2018-03-29 Infineon Technologies Ag Power switch device
US20180191347A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Voltage level shifter monitor with tunable voltage level shifter replica circuit
US10115450B1 (en) * 2017-06-08 2018-10-30 International Business Machines Corporation Cascode complimentary dual level shifter

Patent Citations (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444408A (en) * 1993-12-13 1995-08-22 Micron Technology, Inc. Active pull-up voltage spike reducer
US5952847A (en) * 1996-06-25 1999-09-14 Actel Corporation Multiple logic family compatible output driver
US20020097606A1 (en) * 2001-01-24 2002-07-25 Takayuki Kurokawa Semiconductor circuit
US20030179032A1 (en) * 2002-03-25 2003-09-25 Tomohiro Kaneko Level shifter circuit and semiconductor device including the same
US7196547B2 (en) * 2004-06-08 2007-03-27 Nec Electronics Corporation Level shifter and buffer circuit
US20070070780A1 (en) * 2005-09-29 2007-03-29 Hynix Semiconductor Inc. Output driving device
US7834662B2 (en) * 2006-12-13 2010-11-16 Apple Inc. Level shifter with embedded logic and low minimum voltage
US7915920B2 (en) * 2006-12-13 2011-03-29 Apple Inc. Low latency, power-down safe level shifter
US20080238523A1 (en) * 2007-03-31 2008-10-02 Thorp Tyler J Level shifter circuit incorporating transistor snap-back protection
US20080238522A1 (en) * 2007-03-31 2008-10-02 Thorp Tyler J Method for incorporating transistor snap-back protection in a level shifter circuit
US20090096484A1 (en) * 2007-10-12 2009-04-16 Mediatek Inc. Level shifters
US7446566B1 (en) * 2007-10-16 2008-11-04 Freescale Semiconductor, Inc. Level shifter
US7733126B1 (en) * 2009-03-31 2010-06-08 Freescale Semiconductor, Inc. Negative voltage generation
US8102728B2 (en) * 2009-04-07 2012-01-24 Apple Inc. Cache optimizations using multiple threshold voltage transistors
US7755392B1 (en) * 2009-05-21 2010-07-13 Ememory Technology Inc. Level shift circuit without high voltage stress of transistors and operating at low voltages
US8587359B2 (en) * 2009-08-07 2013-11-19 Atmel Corporation Level shifter with output latch
US8406068B2 (en) * 2009-09-18 2013-03-26 Stmicroelectronics S.R.L. Voltage shifter for high voltage operations
US7994821B1 (en) * 2010-04-02 2011-08-09 Altera Corporation Level shifter circuits and methods
US8319540B2 (en) * 2010-07-01 2012-11-27 Integrated Device Technology, Inc. Apparatuses and methods for a voltage level shifting
US8384431B2 (en) * 2010-12-09 2013-02-26 Integrated Device Technology, Inc. Voltage level shifting apparatuses and methods
US8604868B2 (en) * 2011-04-01 2013-12-10 Stmicroelectronics S.R.L. Dynamic biasing circuit for a protection stage using low voltage transistors
US8575962B2 (en) * 2011-08-29 2013-11-05 Freescale Semiconductor, Inc. Integrated circuit having critical path voltage scaling and method therefor
US20130250704A1 (en) * 2012-03-22 2013-09-26 Elpida Memory Inc. Semiconductor device having level shifter
US20140145777A1 (en) * 2012-11-29 2014-05-29 Infineon Technologies Austria Ag System and Method for a Level Shifter
US20140197872A1 (en) * 2013-01-17 2014-07-17 Stmicroelectronics S.R.L. Level shifter device
US20140266384A1 (en) * 2013-03-14 2014-09-18 Taiwna Semiconductor Manufacturing Co. Ltd. Systems and method for level shifters
US20140269112A1 (en) * 2013-03-15 2014-09-18 Qualcomm Incorporated Apparatus and method for writing data to memory array circuits
US20160118985A1 (en) * 2013-06-11 2016-04-28 Agency For Science, Technology And Research Circuit arrangement and method of operating the same
US20150365085A1 (en) * 2014-06-17 2015-12-17 Boe Technology Group Co., Ltd. Dual Pull-Down Control Module, Shift Register Unit, Gate Driver, and Display Panel
US9191007B1 (en) * 2014-06-20 2015-11-17 Freescale Semiconductor, Inc. Latching level shifter and method of operation
US20160042794A1 (en) * 2014-08-07 2016-02-11 Macronix International Co., Ltd. Level shifter and decoder for memory
US20160118987A1 (en) * 2014-10-28 2016-04-28 Lattice Semiconductor Corporation Level Shifter With Low Static Power Dissipation
US9595967B2 (en) * 2015-02-20 2017-03-14 Kabushiki Kaisha Toshiba Level shift circuit and driver circuit
US20160329887A1 (en) * 2015-05-06 2016-11-10 SK Hynix Inc. Transmitting/receiving system
US9768779B2 (en) * 2015-06-05 2017-09-19 Qualcomm Incorporated Voltage level shifters employing preconditioning circuits, and related systems and methods
US20170364170A1 (en) * 2015-08-20 2017-12-21 Boe Technology Group Co., Ltd. Shift Register Unit, Drive Method Thereof, Gate Drive Device, and Display Device
US20170193885A1 (en) * 2016-01-04 2017-07-06 Boe Technology Group Co., Ltd. Shift register unit, driving method, gate driving circuit and display device
US20180090924A1 (en) 2016-09-26 2018-03-29 Infineon Technologies Ag Power switch device
US20180191347A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Voltage level shifter monitor with tunable voltage level shifter replica circuit
US10115450B1 (en) * 2017-06-08 2018-10-30 International Business Machines Corporation Cascode complimentary dual level shifter

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