US10102146B2 - Memory system and operating method for improving rebuild efficiency - Google Patents

Memory system and operating method for improving rebuild efficiency Download PDF

Info

Publication number
US10102146B2
US10102146B2 US15/082,990 US201615082990A US10102146B2 US 10102146 B2 US10102146 B2 US 10102146B2 US 201615082990 A US201615082990 A US 201615082990A US 10102146 B2 US10102146 B2 US 10102146B2
Authority
US
United States
Prior art keywords
section
lba table
memory
lba
super
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US15/082,990
Other languages
English (en)
Other versions
US20160283401A1 (en
Inventor
Shwetashree VIRAJAMANGALA
Nagabhushan HEGDE
Frederick K. H. Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Priority to US15/082,990 priority Critical patent/US10102146B2/en
Priority to TW105115833A priority patent/TWI696915B/zh
Priority to CN201610392627.5A priority patent/CN107239228B/zh
Publication of US20160283401A1 publication Critical patent/US20160283401A1/en
Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SK HYNIX MEMORY SOLUTIONS INC.
Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HEGDE, NAGABHUSHAN, LEE, FREDERICK K. H., VIRAJAMANGALA, SHWETASHREE
Application granted granted Critical
Publication of US10102146B2 publication Critical patent/US10102146B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/122—Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages

Definitions

  • Exemplary embodiments of the present disclosure relate to a memory system and an operating method thereof.
  • the computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. Due to this fact, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having memory devices, that is, a data storage device.
  • the data storage device is used as a main memory device or an auxiliary memory device of the portable electronic devices.
  • Data storage devices using memory devices provide excellent stability, durability, high information access speed, and low power consumption, since they have no moving parts. Examples of data storage devices having such advantages include universal serial bus (USB) memory devices, memory cards having various interfaces, and solid state drives (SSD).
  • USB universal serial bus
  • SSD solid state drives
  • the systems may include a memory device including a plurality of closed super blocks and an open super block, a logical block addressing (LBA) table including a plurality of sections; and a controller suitable for, after a power loss, determining a most recently saved section of the LBA table, a previous section saved prior to the most recently saved section of the LBA table, and a least recently saved section of the LBA table, reading the open super block and updating entries in the LBA table from the most recently saved section through to the least recently saved section, reading a newest closed super block from the plurality of super blocks and updating entries in the LBA table from the previous section saved prior to the most recently saved section through to the least recently saved section; and reading an oldest super block and updating entries in the LBA table in the least recently saved section.
  • LBA logical block addressing
  • the methods may include, after a power loss, determining a most recently saved section of a logical block addressing (LBA) table, a previous section saved prior to the most recently saved section of the LBA table, and a least recently saved section of the LBA table, reading an open super block and updating entries in the LBA table from the most recently saved section through to the least recently saved section, reading a newest closed super block from a plurality of closed super blocks and updating entries in the LBA table from the previous section saved prior to the most recently saved section through to the least recently saved section, and reading an oldest super block and updating entries in the LBA table in the least recently saved section.
  • LBA logical block addressing
  • FIG. 1 is a block diagram schematically illustrating a memory system in accordance with an embodiment of the present invention.
  • FIG. 2 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.
  • FIG. 3 is a circuit diagram illustrating a memory block of a memory device in accordance with an embodiment of the present invention.
  • FIG. 4 is a diagram illustrating a control unit of a memory controller in accordance with an embodiment of the present invention.
  • FIG. 5 is a diagram of a memory system according to aspects of the invention.
  • FIG. 6 is a flowchart of steps in a method for rebuilding an LBA table in accordance with aspects of the invention.
  • FIG. 7 is a diagram illustrating an LBA table and a memory array according to aspects of the invention.
  • FIG. 8 is a flowchart of steps in a method for rebuilding an LBA table using bitmaps according to aspects of the invention.
  • FIG. 9 is a diagram of a bitmap according to aspects of the invention.
  • FIG. 10 is a diagram of an LBA table and a bitmap buffer in accordance with aspects of the invention.
  • the invention can be implemented in numerous ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer readable storage medium; and/or a processor, such as a processor suitable for executing instructions stored on and/or provided by a memory coupled to the processor.
  • these implementations, or any other form that the invention may take, may be referred to as techniques.
  • the order of the steps of disclosed processes may be altered within the scope of the invention.
  • a component such as a processor or a memory described as being suitable for performing a task may be implemented as a general component that is temporarily suitable for performing the task at a given time or a specific component that is manufactured to perform the task.
  • the term ‘processor’ refers to one or more devices, circuits, and/or processing cores suitable for processing data, such as computer program instructions.
  • FIG. 1 is a block diagram schematically illustrating a memory system 10 in accordance with an embodiment of the present invention.
  • the memory system 10 may include a memory controller 100 and a semiconductor memory device 200 .
  • the memory controller 100 may control overall operations of the semiconductor memory device 200 .
  • the semiconductor memory device 200 may perform one or more erase, program, and read operations under the control of the memory controller 100 .
  • the semiconductor memory device 200 may receive a command CMD, an address ADDR and data DATA through input/output lines.
  • the semiconductor memory device 200 may receive power PWR through a power line and a control signal CTRL through a control line.
  • the control signal may include a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and so on.
  • the memory controller 100 and the semiconductor memory device 200 may be integrated in a single semiconductor device.
  • the memory controller 100 and the semiconductor memory device 200 may be integrated in a single semiconductor device such as a solid state drive (SSD).
  • the solid state drive may include a storage device for storing data therein.
  • operation speed of a host (not shown) coupled to the memory system 10 may remarkably improve.
  • the memory controller 100 and the semiconductor memory device 200 may be integrated in a single semiconductor device such as a memory card.
  • the memory controller 100 and the semiconductor memory device 200 may be integrated in a single semiconductor device to configure a memory card such as a PC card of personal computer memory card international association (PCMCIA), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a reduced-size multimedia card (RS-MMC), a micro-size version of MMC (MMCmicro), a secure digital (SD) card, a mini secure digital (miniSD) card, a micro secure digital (microSD) card, a secure digital high capacity (SDHC), and a universal flash storage (UFS).
  • PCMCIA personal computer memory card international association
  • CF compact flash
  • SM smart media
  • MMC multimedia card
  • RS-MMC reduced-size multimedia card
  • MMCmicro micro-size version of MMC
  • SD secure digital
  • miniSD mini secure digital
  • microSD micro secure digital
  • the memory system 10 may be provided as one of various elements including an electronic device such as a computer, an ultra-mobile PC (UMPC), a workstation, a net-book computer, a personal digital assistant (PDA), a portable computer, a web tablet PC, a wireless phone, a mobile phone, a smart phone, an e-book reader, a portable multimedia player (PMP), a portable game device, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device of a data center, a device capable of receiving and transmitting information in a wireless environment, one of electronic devices of a home network, one of electronic devices of a computer network, one of electronic devices of a telematics network, a radio-frequency identification (RFID) device, or elements devices
  • RFID
  • FIG. 2 is a detailed block diagram illustrating a memory system in accordance with an embodiment of the present invention.
  • the memory system of FIG. 2 may depict the memory system 10 shown in FIG. 1 .
  • the memory system 10 may include a memory controller 100 and a semiconductor memory device 200 .
  • the memory system 10 may operate in response to a request from a host device, and in particular, store data to be accessed by the host device.
  • the host device may be implemented with any one of various kinds of electronic devices.
  • the host device may include an electronic device such as a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder and a digital video player.
  • the host device may include a portable electronic device such as a mobile phone, a smart phone, an e-book, an MP3 player, a portable multimedia player (PMP), and a portable game player.
  • PMP portable multimedia player
  • the memory device 200 may store data to be accessed by the host device.
  • the memory device 200 may be implemented with a volatile memory device such as a dynamic random access memory (DRAM) and a static random access memory (SRAM) or a non-volatile memory device such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric random access memory (FRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM) and a resistive RAM (RRAM).
  • ROM read only memory
  • MROM mask ROM
  • PROM programmable ROM
  • EPROM erasable programmable ROM
  • EEPROM electrically erasable programmable ROM
  • FRAM ferroelectric random access memory
  • PRAM phase change RAM
  • MRAM magnetoresistive RAM
  • RRAM resistive RAM
  • the controller 100 may control storage of data in the memory device 200 .
  • the controller 100 may control the memory device 200 in response to a request from the host device.
  • the controller 100 may provide the data read from the memory device 200 , to the host device, and store the data provided from the host device into the memory device 200 .
  • the controller 100 may include a storage unit 110 , a control unit 120 , the error correction code (ECC) unit 130 , a host interface 140 and a memory interface 150 , which are coupled through a bus 160 .
  • ECC error correction code
  • the storage unit 110 may serve as a working memory of the memory system 10 and the controller 100 , and store data for driving the memory system 10 and the controller 100 .
  • the storage unit 110 may store data used by the controller 100 and the memory device 200 for such operations as read, write, program and erase operations.
  • the storage unit 110 may be implemented with a volatile memory.
  • the storage unit 110 may be implemented with a static random access memory (SRAM) or a dynamic random access memory (DRAM).
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • the storage unit 110 may store data used by the host device in the memory device 200 for the read and write operations.
  • the storage unit 110 may include a program memory, a data memory, a write buffer, a read buffer, a map buffer, and so forth.
  • the control unit 120 may control general operations of the memory system 10 , and a write operation or a read operation for the memory device 200 , in response to a write request or a read request from the host device.
  • the control unit 120 may drive firmware, which is referred to as a flash translation layer (FTL), to control the general operations of the memory system 10 .
  • FTL flash translation layer
  • the FTL may perform operations such as logical to physical (L2P) mapping, wear leveling, garbage collection, and bad block handling.
  • L2P mapping is known as logical block addressing (LBA).
  • the ECC unit 130 may detect and correct errors in the data read from the memory device 200 during the read operation.
  • the ECC unit 130 may not correct error bits when the number of the error bits is greater than or equal to a threshold number of correctable error bits, and may output an error correction fail signal indicating failure in correcting the error bits.
  • the ECC unit 130 may perform an error correction operation based on a coded modulation such as a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a turbo product code (TPC), a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), a Block coded modulation (BCM), and so on.
  • a coded modulation such as a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a turbo product code (TPC), a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), a Block coded modulation (BCM), and so on.
  • the host interface 140 may communicate with the host device through one or more of various interface protocols such as a universal serial bus (USB), a multi-media card (MMC), a peripheral component interconnect express (PCI-E), a small computer system interface (SCSI), a serial-attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).
  • USB universal serial bus
  • MMC multi-media card
  • PCI-E peripheral component interconnect express
  • SCSI small computer system interface
  • SAS serial-attached SCSI
  • SATA serial advanced technology attachment
  • PATA parallel advanced technology attachment
  • ESDI enhanced small disk interface
  • IDE integrated drive electronics
  • the memory interface 150 may provide an interface between the controller 100 and the memory device 200 to allow the controller 100 to control the memory device 200 in response to a request from the host device.
  • the memory interface 150 may generate control signals for the memory device 200 and process data under the control of the CPU 120 .
  • the memory interface 150 may generate control signals for the memory and process data under the control of the CPU 120 .
  • the memory device 200 may include a memory cell array 210 , a control circuit 220 , a voltage generation circuit 230 , a row decoder 240 , a page buffer 250 , a column decoder 260 , and an input/output circuit 270 .
  • the memory cell array 210 may include a plurality of memory blocks 211 and may store data therein.
  • the voltage generation circuit 230 , the row decoder 240 , the page buffer 250 , the column decoder 260 and the input/output circuit 270 form a peripheral circuit for the memory cell array 210 .
  • the peripheral circuit may perform a program, read, or erase operation of the memory cell array 210 .
  • the control circuit 220 may control the peripheral circuit.
  • the voltage generation circuit 230 may generate operation voltages having various levels. For example, in an erase operation, the voltage generation circuit 230 may generate operation voltages having various levels such as an erase voltage and a pass voltage.
  • the row decoder 240 may be connected to the voltage generation circuit 230 , and the plurality of memory blocks 211 .
  • the row decoder 240 may select at least one memory block among the plurality of memory blocks 211 in response to a row address RADD generated by the control circuit 220 , and transmit operation voltages supplied from the voltage generation circuit 230 to the selected memory blocks among the plurality of memory blocks 211 .
  • the page buffer 250 is connected to the memory cell array 210 through bit lines BL (not shown).
  • the page buffer 250 may precharge the bit lines BL with a positive voltage, transmit/receive data to/from a selected memory block in program and read operations, or temporarily store transmitted data, in response to a page buffer control signal generated by the control circuit 220 .
  • the column decoder 260 may transmit/receive data to/from the page buffer 250 or transmit/receive data to/from the input/output circuit 270 .
  • the input/output circuit 270 may transmit, to the control circuit 220 , a command and an address, transmitted from an external device (e.g., the memory controller 100 ), transmit data from the external device to the column decoder 260 , or output data from the column decoder 260 to the external device, through the input/output circuit 270 .
  • an external device e.g., the memory controller 100
  • the control circuit 220 may control the peripheral circuit in response to the command and the address.
  • FIG. 3 is a circuit diagram illustrating a memory block of a semiconductor memory device in accordance with an embodiment of the present invention.
  • a memory block of FIG. 3 may be the memory blocks 211 of the memory cell array 200 shown in FIG. 2 .
  • the memory blocks 211 may include a plurality of cell strings 221 coupled to bit lines BL 0 to BLm ⁇ 1, respectively.
  • the cell string of each column may include one or more drain selection transistors DST and one or more source selection transistors SST.
  • a plurality of memory cells or memory cell transistors may be serially coupled between the selection transistors DST and SST.
  • Each of the memory cells MC 0 to MCn ⁇ 1 may be formed of a multi-level cell (MLC) storing data information of multiple bits in each cell.
  • the cell strings 221 may be electrically coupled to the corresponding bit lines BL 0 to BLm ⁇ 1, respectively.
  • the memory blocks 211 may include a NAND-type flash memory cell.
  • the memory blocks 211 are not limited to the NAND flash memory, but may include NOR-type flash memory, hybrid flash memory in which two or more types of memory cells are combined, and one-NAND flash memory in which a controller is embedded inside a memory chip.
  • FIG. 4 is a diagram illustrating a control unit of a memory controller in accordance with an embodiment of the present invention.
  • the control unit of FIG. 4 may depict the control unit 120 of the controller 100 in FIG. 2 .
  • control unit 120 of the controller 100 may be coupled to the memory device 200 including a plurality of a super blocks through an interface (e.g., the memory interface 150 of FIG. 2 ).
  • the control unit 120 may include a logical block addressing (LBA) table 410 , an information storage unit 420 , a rebuild unit 430 and a garbage collection (GC) unit 440 .
  • the LBA table 410 may be a mapping table from logical block address (LBA) to physical address that is part of the flash translation layer (FTL).
  • the rebuild unit 430 may be configured to rebuild the LBA table 410 based on information during SPOR.
  • the GC unit 440 may perform any needed garbage collection operation during SPOR. It is noted that FIG. 4 merely illustrates that the control unit 120 includes elements for the operation with respect to SPOR.
  • the “erase-before-write” limitation of the memory device such as a flash memory requires a special layer of system software called a flash translation layer (FTL) to emulate a block device interface for backward compatibility.
  • FTL flash translation layer
  • File systems and applications may use flash memory as if they were using a hard disk.
  • Logical to Physical (L2P) mapping system known as logical block addressing (LBA) is part of the FTL.
  • LBA table may be in a dynamic random access memory (DRAM), which is a volatile memory
  • DRAM dynamic random access memory
  • firmware must be able to rebuild the up-to-date table when power is on.
  • writing the LBA table to the memory device e.g., NAND flash memory
  • SPOR fast sudden power-off recovery
  • Embodiments and examples disclosed herein improve the performance of a memory system (e.g., a solid state drive (SSD)) and in particular the overall SPOR time (e.g., reduce the amount of time between when power is restored to the memory system after a sudden power loss and when a host is able to begin writing to the memory system).
  • a memory system e.g., a solid state drive (SSD)
  • the overall SPOR time e.g., reduce the amount of time between when power is restored to the memory system after a sudden power loss and when a host is able to begin writing to the memory system.
  • Embodiments disclosed herein include methods, systems, processes and devices that reduce the number of super blocks needed to be read from a memory device (e.g., NAND flash memory) at power up as well as accelerating the performance of garbage collection.
  • a memory device e.g., NAND flash memory
  • the system 50 includes a DRAM 500 and a memory 502 .
  • the device 500 includes an LBA table 510 , a DRAM bitmap storage 550 and a power-off capacitor 570 .
  • the device 500 may be housed on a volatile memory (e.g., a DRAM) such that, in the event of a sudden power loss, the LBA table 510 is required to be rebuilt.
  • the DRAM bitmap storage 550 may be configured for storing bitmaps corresponding to each of the super blocks that are stored on the memory 502 .
  • the power-off capacitor 570 is configured to store enough power such that, in the event of a power loss, there is sufficient time to transfer contents of the DRAM bitmap storage (and/or other operations) to the memory bitmap storage 560 of the memory 502 .
  • the memory 502 includes, among other components, a plurality of super blocks, where each of the super blocks may include a meta-page MP when closed, an open block for host writes 530 , an open block for garbage collection (GC) 540 , etc.
  • the memory 502 may be a NAND memory implemented as an SSD, or other types of suitable memory as will be understood to those of skill in the art from the description herein.
  • the memory also includes a memory bitmap storage 560 that is configured to store bitmaps corresponding to super blocks of the memory 502 , and the bitmap storage 560 may be configured to receive bitmaps stored at the DRAM bitmap storage 550 .
  • Previous rebuilding procedures or SPOR processes require time consuming steps, such as requiring hardware (e.g., memory 502 ) access to read every super block and to identify closed and open blocks by reading every valid block from previous signature scans. Bubble sorting of valid blocks may also be required, which again is time consuming.
  • previous methods involve having sections of the LBA table saved periodically in a round-robin fashion, together with a list of the current “dirty” superblocks.
  • a dirty superblock is one that contains at least one LBA whose corresponding entry in the LBA table is not up-to-date, i.e., dirty).
  • the saved LBA table is reloaded into DRAM and the meta pages of the dirty superblocks, including any open superblock(s), are replayed as in a normal rebuild.
  • one straightforward method is to have fewer number of dirty superblocks.
  • fewer dirty superblocks implies sections of the LBA table need to be saved more frequently during run time, which impacts drive performance.
  • more system blocks may be needed for storing the saved LBA table, which means fewer empty user data blocks available for over-provisioning, thus increasing write amplification and ultimately leads to lower TBD (total bytes written) for a drive.
  • TBD total bytes written
  • FIG. 6 is a flowchart 60 of steps for rebuilding an LBA table.
  • FIG. 7 is a diagram of an LBA table 700 and a memory array 702 .
  • an LBA table of 128 sections is used for descriptive purposes. Also, the following metrics are used for exemplary purposes:
  • At block 600 at least the most recently saved section, the previous section saved prior to the most recently saved section, and the least recently saved section of the LBA table 700 from a power loss are determined.
  • the LBA table 700 is one that follows a round-robin scheme, although this is for illustration and is not intended to limit the invention to such schemes.
  • the last section is saved, the first section is then used.
  • section 128 is the “last” section and section 1 is the “first section”.
  • a power loss 704 is shown occurring after section 3 is saved but before section 4.
  • section 3 would be the most recently saved section
  • section 2 would be the previous section saved prior to the most recently saved section
  • section 4 would be the least recently saved section of the LBA table 700 .
  • Each of the sections may correspond to a super block, such as the super blocks in memory array 702 .
  • One section of the LBA table 700 may be saved to the memory 502 each time a super block is closed. Thus, in the example, there are 128 dirty super blocks at any given time. N is used to denote the newest closed super block.
  • the open super block is read and the entries in the LBA table corresponding to the open super block from the most recently saved section through the least recently saved section are updated.
  • the open super block is read, and the entries in the LBA table are updated from section 3 (most recently saved section) through section 4 (least recently saved section).
  • section 3 is updated, then section 2 is updated, then section 1 is updated, then section 128 is updated and so forth until section 4 is updated.
  • the newest closed super block is read and the entries in the LBA table corresponding to the newest closed super block from the previous section saved prior to the most recently saved section through the least recently saved section are updated.
  • the closed super block N would be read and the entries from section 2 of the LBA table 700 (the previous section saved prior to the most recently saved section, i.e. section 3) through section 4 of the LBA table 700 (the least recently saved section) are updated.
  • the oldest closed super block is read and the entries in the LBA table corresponding to the oldest closed super block in the least recently saved section are updated.
  • the closed super block N-126 is read and section 4 (the least recently saved section of the LBA table 700 ) is updated.
  • the described method of FIG. 6 is not limited to the enunciated steps. For example, similar steps may be conducted for each of the closed super blocks. These methods may include steps such as:
  • this method exploits the fact that any corresponding entry residing in sections of the LBA table 700 that are saved after a dirty superblock is closed already contains the physical address to the corresponding logical page in that dirty superblock. Thus, there is no need to update such an entry. (Note, however, that this does not mean that the entry is clean, since that LBA can be rewritten again in the subsequent dirty superblocks).
  • the LBAs in each dirty superblock may be evenly distributed over the entire LBA range.
  • the amount of updates saved per instance of sudden power loss will be a random number.
  • the amount of updates saved when averaged over many instances of sudden power loss is still 50%, since sudden power loss can occur after any one of the 128 sections of the LBA table 700 is saved with equal probability.
  • the amount of savings exhibits a statistical distribution with an average value of 50% and a non-zero variance.
  • the average value is 50% and a zero variance.
  • the amount of savings per instance of sudden power loss is also 50%.
  • the variance which is workload dependent, can be determined by simulations.
  • the only additional information required is knowing which section of the LBA table 700 was last saved to memory before sudden power loss occurs.
  • the section number can then be saved to the system area in memory within the time span provided by the power off capacitor 570 .
  • FIG. 8 is a flowchart 80 of steps for using bitmaps for LBA table rebuild.
  • FIG. 9 is a diagram of an example bitmap.
  • FIG. 10 is a diagram of an LBA table 1000 and a bitmap buffer 1002 , the bitmap buffer 1002 being stored as a circular buffer.
  • bitmap for each dirty super block is generated and stored.
  • the bitmaps may be stored, for example, in the DRAM bitmap storage 550 , the memory bitmap storage 560 , etc.
  • the appropriate bitmaps are updated each time the LBA table is updated.
  • Each bitmap 900 may indicate whether a logical page in a corresponding dirty super block is valid. Thus, every time the LBA table 1000 is updated during a normal write or trim operation, the appropriate bitmaps are also updated. For example, the bitmap 900 shows a 8 kB bitmap for a dirty super block. The values in each bit correspond to weather the logical page corresponding to that bit is valid.
  • the bitmaps are saved to a non-volatile memory.
  • the bitmaps may be saved and updated on the DRAM bitmap storage 550 , but, at a sudden power loss, the bitmaps are transferred (e.g., saved) from the DRAM bitmap storage 550 to the memory bitmap storage 560 within the time permitted by the power off capacitor 570 .
  • bitmaps may be loaded into the DRAM, and, at step 808 , bitmaps and meta-pages of each dirty super block are scanned together the LBAs that correspond to valid logical address are determined, such that these LBAs are updated.
  • LBA table 1000 and the bitmaps may be first loaded into DRAM.
  • the bitmap and the meta pages of each dirty superblock are then scanned together, and only LBAs that correspond to valid logical pages are considered for updating. This ensures that entries corresponding to non-trimmed LBAs are updated at most once in the LBA table 1000 , while those corresponding to trimmed LBAs are not updated at all.
  • entries for non-trimmed LBAs can be updated multiple times without the bitmaps, while information about trimmed LBAs are lost after sudden power loss. In essence, the more invalid logical pages there are in the dirty superblocks, the more reduction in updates the bitmaps offer when compared to the case of no bitmaps.
  • the number of invalid logical pages in the dirty superblocks is a function of both over-provisioning and the type of workload.
  • the more hot data there are in a workload the more invalid logical pages there are in the dirty superblocks, as LBAs corresponding to hot data will be overwritten more frequently in the dirty superblocks. If there are 5% of invalid logical pages in the 128 dirty superblocks, for instance, the overall reduction in updates compared with the original replay mechanism will be 52.5%.
  • bitmaps offers another very important advantage: the order in which the meta pages are replayed can be changed. Since only LBAs that correspond to valid logical pages are considered for updating, it is impossible to overwrite an entry in the LBA table with the physical address of an old logical page, even if the meta pages are replayed in a random order. As it turns out, the best replay order is to replay the meta pages in exact reverse order to which the logical pages are written, i.e., the meta data in the open superblock are scanned first, followed by the meta pages in the most recently closed dirty superblock, then the meta pages in the 2nd most recently closed dirty superblock, and so on.
  • section 3 of the LBA table 1000 will be guaranteed clean, since no more updating is needed for this section according to the trend described in the previous section.
  • section 2 of the LBA table 700 , 1000 is guaranteed clean, as no more updating is required for this section.
  • the same pattern repeats for the remaining dirty superblocks. In essence, after updating is completed for each dirty superblock, an additional section of the LBA table 700 , 1000 becomes clean.
  • the controller can start to accept host read and write commands. If a host read or write command points to a clean section of the LBA table 700 , 1000 , the command will be immediately executed. Otherwise, execution will be delayed until that section of the LBA table becomes clean.
  • the initial number of dirty superblocks to process therefore, should be chosen based on the maximum delay a host read or write command will encounter if it points to a dirty section of the LBA table. This number will be small, since the number of average updates needed for a superblock decreases when the meta pages are replayed in reverse order.
  • This 1 MB of DRAM can be implemented as a circular buffer 1002 , as the memory space can be reused after completing 1 round of saving.
  • 1 MB of data takes up exactly 1 strip of a system area superblock, and requires about 1.4 ms to encode.
  • programming time is no more than 3 ms. Therefore, the total time required to save to NAND after sudden power loss occurs is well within the 20 ms of extended power provided by the super capacitor 570 .
  • the meta pages for the open superblock can also be saved to the system area when sudden power loss occurs. This avoids scanning the meta data of each logical page during rebuild and further shortens rebuild time.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
US15/082,990 2015-03-26 2016-03-28 Memory system and operating method for improving rebuild efficiency Active US10102146B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US15/082,990 US10102146B2 (en) 2015-03-26 2016-03-28 Memory system and operating method for improving rebuild efficiency
TW105115833A TWI696915B (zh) 2015-03-26 2016-05-20 提高重建效率的記憶體系統和操作方法
CN201610392627.5A CN107239228B (zh) 2015-03-26 2016-06-06 提高重建效率的存储器系统和操作方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562138619P 2015-03-26 2015-03-26
US15/082,990 US10102146B2 (en) 2015-03-26 2016-03-28 Memory system and operating method for improving rebuild efficiency

Publications (2)

Publication Number Publication Date
US20160283401A1 US20160283401A1 (en) 2016-09-29
US10102146B2 true US10102146B2 (en) 2018-10-16

Family

ID=56975870

Family Applications (1)

Application Number Title Priority Date Filing Date
US15/082,990 Active US10102146B2 (en) 2015-03-26 2016-03-28 Memory system and operating method for improving rebuild efficiency

Country Status (3)

Country Link
US (1) US10102146B2 (zh)
CN (1) CN107239228B (zh)
TW (1) TWI696915B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190188082A1 (en) * 2017-12-19 2019-06-20 SK Hynix Inc. Memory system and operating method thereof
US11360889B2 (en) * 2018-12-21 2022-06-14 SK Hynix Inc. Memory system and operating method thereof performing garbage collection and write operations in parallel on different dies
US11893272B2 (en) 2021-03-04 2024-02-06 Samsung Electronics Co., Ltd. Memory storage device, method for operating the storage device and method for operating a host device

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102449192B1 (ko) * 2015-09-10 2022-09-29 삼성전자주식회사 데이터 저장 장치의 작동 방법과 이를 포함하는 데이터 처리 시스템의 작동 방법
US9904607B2 (en) * 2015-11-13 2018-02-27 International Business Machines Corporation Logical to physical table restoration from stored journal entries
KR102593352B1 (ko) * 2016-05-04 2023-10-26 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
CN107678679B (zh) * 2016-08-02 2020-09-08 建兴储存科技(广州)有限公司 运用于固态储存装置的超级区块的扫描方法
US11579789B2 (en) * 2017-09-29 2023-02-14 Apple Inc. Techniques for managing context information for a storage device
KR20190072306A (ko) * 2017-12-15 2019-06-25 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작 방법
TWI640927B (zh) * 2017-12-29 2018-11-11 國科美國研究實驗室 Power management method for data storage device
KR102430798B1 (ko) * 2018-01-11 2022-08-10 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작방법
CN110489052B (zh) * 2018-05-14 2022-11-25 慧荣科技股份有限公司 数据储存装置
KR20200071282A (ko) * 2018-12-11 2020-06-19 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작방법
KR20200079852A (ko) * 2018-12-26 2020-07-06 에스케이하이닉스 주식회사 메모리 시스템 및 그것의 동작방법
KR20200115831A (ko) * 2019-03-27 2020-10-08 에스케이하이닉스 주식회사 컨트롤러, 메모리 시스템 및 그것의 동작 방법
US11372754B2 (en) * 2020-06-12 2022-06-28 Western Digital Technologies, Inc. Storage system and method for enabling a software-defined dynamic storage response

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070136553A1 (en) * 2005-12-13 2007-06-14 Sinclair Alan W Logically-addressed file storage systems
US20070136555A1 (en) * 2005-12-13 2007-06-14 Sinclair Alan W Logically-addressed file storage methods
US20080212769A1 (en) * 2006-10-23 2008-09-04 Sarvar Patel Processing method for message integrity with tolerance for non-sequential arrival of message data
US20090168525A1 (en) * 2007-12-27 2009-07-02 Pliant Technology, Inc. Flash memory controller having reduced pinout
US20090204824A1 (en) * 2007-12-31 2009-08-13 Lin Jason T System, method and memory device providing data scrambling compatible with on-chip copy operation
US20120254503A1 (en) * 2011-03-28 2012-10-04 Western Digital Technologies, Inc. Power-safe data management system
US20140129874A1 (en) * 2012-11-07 2014-05-08 Apple Inc. Redundancy schemes for non-volatile memory using parity zones having new and old parity blocks
US8838911B1 (en) * 2011-03-09 2014-09-16 Verint Systems Inc. Systems, methods, and software for interleaved data stream storage
US9032138B2 (en) 2011-11-23 2015-05-12 Samsung Electronics Co., Ltd. Storage device based on a flash memory and user device including the same
US20170060768A1 (en) * 2015-09-02 2017-03-02 SK Hynix Inc. Supporting invalidation commands for non-volatile memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101350771B (zh) * 2008-07-07 2010-12-29 中国人民解放军国防科学技术大学 三态内容可寻址存储器条目免排序存储方法及其系统
CN101477492B (zh) * 2009-01-21 2010-12-29 华中科技大学 一种用于固态硬盘的循环重写闪存均衡方法
US8239614B2 (en) * 2009-03-04 2012-08-07 Micron Technology, Inc. Memory super block allocation
US8458133B2 (en) * 2011-01-24 2013-06-04 Apple Inc. Coordinating sync points between a non-volatile memory and a file system
CN105183401A (zh) * 2015-10-30 2015-12-23 深圳市泽云科技有限公司 一种固态硬盘数据恢复方法、装置及系统

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070136553A1 (en) * 2005-12-13 2007-06-14 Sinclair Alan W Logically-addressed file storage systems
US20070136555A1 (en) * 2005-12-13 2007-06-14 Sinclair Alan W Logically-addressed file storage methods
US20080212769A1 (en) * 2006-10-23 2008-09-04 Sarvar Patel Processing method for message integrity with tolerance for non-sequential arrival of message data
US20090168525A1 (en) * 2007-12-27 2009-07-02 Pliant Technology, Inc. Flash memory controller having reduced pinout
US20090204824A1 (en) * 2007-12-31 2009-08-13 Lin Jason T System, method and memory device providing data scrambling compatible with on-chip copy operation
US8838911B1 (en) * 2011-03-09 2014-09-16 Verint Systems Inc. Systems, methods, and software for interleaved data stream storage
US20120254503A1 (en) * 2011-03-28 2012-10-04 Western Digital Technologies, Inc. Power-safe data management system
US9032138B2 (en) 2011-11-23 2015-05-12 Samsung Electronics Co., Ltd. Storage device based on a flash memory and user device including the same
US20140129874A1 (en) * 2012-11-07 2014-05-08 Apple Inc. Redundancy schemes for non-volatile memory using parity zones having new and old parity blocks
US20170060768A1 (en) * 2015-09-02 2017-03-02 SK Hynix Inc. Supporting invalidation commands for non-volatile memory

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
C. Zhang et al, Deterministic Crash Recovery for NAND Flash Based Storage Systems, Proc. 2014 51st ACM/EDAC/IEEE Design Automation Conference, pp. 1-6, Jun. 2014.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190188082A1 (en) * 2017-12-19 2019-06-20 SK Hynix Inc. Memory system and operating method thereof
US10949305B2 (en) * 2017-12-19 2021-03-16 SK Hynix Inc. Memory system and operating method thereof
US11360889B2 (en) * 2018-12-21 2022-06-14 SK Hynix Inc. Memory system and operating method thereof performing garbage collection and write operations in parallel on different dies
US11893272B2 (en) 2021-03-04 2024-02-06 Samsung Electronics Co., Ltd. Memory storage device, method for operating the storage device and method for operating a host device

Also Published As

Publication number Publication date
US20160283401A1 (en) 2016-09-29
CN107239228B (zh) 2020-06-12
TWI696915B (zh) 2020-06-21
TW201734801A (zh) 2017-10-01
CN107239228A (zh) 2017-10-10

Similar Documents

Publication Publication Date Title
US10102146B2 (en) Memory system and operating method for improving rebuild efficiency
US10180805B2 (en) Memory system and operating method thereof
US10318414B2 (en) Memory system and memory management method thereof
US10901656B2 (en) Memory system with soft-read suspend scheme and method of operating such memory system
US10847231B2 (en) Memory system with adaptive read-threshold scheme and method of operating such memory system
US10296452B2 (en) Data separation by delaying hot block garbage collection
US10482038B2 (en) Programmable protocol independent bar memory for SSD controller
US10403369B2 (en) Memory system with file level secure erase and operating method thereof
US10007451B2 (en) Scalable SPOR algorithm for flash memories
US11003587B2 (en) Memory system with configurable NAND to DRAM ratio and method of configuring and using such memory system
CN107544925B (zh) 存储器系统及加速引导时间的方法
US20160334999A1 (en) Reduction of maximum latency using dynamic self-tuning for redundant array of independent disks
US9946644B2 (en) Memory system and operating method thereof
US11005503B2 (en) Memory system with hybrid decoding scheme and method of operating such memory system
US11271589B2 (en) Memory system with error-reduction scheme for decoding and method of operating such memory system
US10671323B2 (en) Memory system with shared buffer architecture for multiple decoders and method of operating such memory system
US11204839B2 (en) Memory system with low-latency read recovery and method of operating the memory system
US11356123B2 (en) Memory system with low-complexity decoding and method of operating such memory system
US11115062B2 (en) Memory system with adaptive threshold decoding and method of operating such memory system
US10141072B2 (en) Efficient encoder based on modified RU algorithm
CN110047554B (zh) 具有超级芯片删除恢复的存储器系统及其操作方法
CN112068983A (zh) 存储器系统及其操作方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: SK HYNIX INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SK HYNIX MEMORY SOLUTIONS INC.;REEL/FRAME:044899/0443

Effective date: 20171214

AS Assignment

Owner name: SK HYNIX INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:VIRAJAMANGALA, SHWETASHREE;HEGDE, NAGABHUSHAN;LEE, FREDERICK K. H.;SIGNING DATES FROM 20180525 TO 20180531;REEL/FRAME:045963/0030

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4