UA95824U - Immittance LOGIC LC-ELEMENT "OR" - Google Patents

Immittance LOGIC LC-ELEMENT "OR"

Info

Publication number
UA95824U
UA95824U UAU201407602U UAU201407602U UA95824U UA 95824 U UA95824 U UA 95824U UA U201407602 U UAU201407602 U UA U201407602U UA U201407602 U UAU201407602 U UA U201407602U UA 95824 U UA95824 U UA 95824U
Authority
UA
Ukraine
Prior art keywords
terminal
capacitor
common bus
immittance
bus
Prior art date
Application number
UAU201407602U
Other languages
Russian (ru)
Ukrainian (uk)
Inventor
Mykola Antonovych Filyniuk
Svitlana Yevhenivna Fursa
Liudmyla Bronislavivna Lischynska
Yulia Vasylivna Dovgosheia
Original Assignee
Vinnitsia Nat Technical Univ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vinnitsia Nat Technical Univ filed Critical Vinnitsia Nat Technical Univ
Priority to UAU201407602U priority Critical patent/UA95824U/en
Publication of UA95824U publication Critical patent/UA95824U/en

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Abstract

LC-immittance logic element "OR" comprises two input and output devices, power bus, common bus, two switches, two limiting resistors, two separation capacitors, a transistor, a limiting resistor. There are introduced a throttle, two capacitors, as the transistor there is used a field effect transistor, the second terminal of the first limiting resistor is connected to the first capacitor, the capacitor with the resistor form a low frequency filter, the second capacitor terminal is connected to the common bus, the second terminal of the second limiting resistor is connected to the power bus and the first terminal of the second capacitor, respectively, together those form a low frequency filter, the second terminal of the second capacitor is connected to the common bus, the second terminal of the second capacitor is coupled to the first terminal of the output terminal, the second terminal of which is connected to the common bus, the source of the FET is connected with the second key which is connected to the second immittance converter, which is connected to the common bus, in addition, the source of the FET is coupled to the first throttle terminal the second terminal of which is connected to the common bus.
UAU201407602U 2014-07-07 2014-07-07 Immittance LOGIC LC-ELEMENT "OR" UA95824U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
UAU201407602U UA95824U (en) 2014-07-07 2014-07-07 Immittance LOGIC LC-ELEMENT "OR"

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
UAU201407602U UA95824U (en) 2014-07-07 2014-07-07 Immittance LOGIC LC-ELEMENT "OR"

Publications (1)

Publication Number Publication Date
UA95824U true UA95824U (en) 2015-01-12

Family

ID=52988733

Family Applications (1)

Application Number Title Priority Date Filing Date
UAU201407602U UA95824U (en) 2014-07-07 2014-07-07 Immittance LOGIC LC-ELEMENT "OR"

Country Status (1)

Country Link
UA (1) UA95824U (en)

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