UA91818U - Generator of frequency marks - Google Patents
Generator of frequency marksInfo
- Publication number
- UA91818U UA91818U UAU201403271U UAU201403271U UA91818U UA 91818 U UA91818 U UA 91818U UA U201403271 U UAU201403271 U UA U201403271U UA U201403271 U UAU201403271 U UA U201403271U UA 91818 U UA91818 U UA 91818U
- Authority
- UA
- Ukraine
- Prior art keywords
- input
- output
- analog signal
- pulse former
- signal multiplier
- Prior art date
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
A generator of frequency marks includes first and second analog signal multipliers, low-pass filter, reference generator, adder unit, frequency divider, first and second pulse formers. First input of the first analog signal multiplier is the input of the device, its second input is connected to the first reference generator, output of the first analog signal multiplier is connected to inputs of the first pulse former and low-pass filter. Output of the low-pass filter is connected to first input of the second analog signal multiplier, which output through the second pulse former is connected to the first input of the adder unit, which second input is connected to output of the first pulse former, and output of the first reference generator is connected to input of the frequency divider, which output is connected to second input of the second analog signal multiplier. Additionally the second reference generator, third analog signal multiplier, third pulse former and computing block are incorporated. First input of the third analog signal multiplier is connected to the input of the device, and its second input is connected to the second reference generator, the output of the third analog signal multiplier is connected to the input of the third pulse former, which output is connected to the first input of the computing block, the second input of this one is connected to the output of the first pulse former, the third input of the computing block is connected to output of the second pulse former, the fourth input of the computing block is connected to the output of the adder unit, and the output of the computing block is the output of the device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
UAU201403271U UA91818U (en) | 2014-03-31 | 2014-03-31 | Generator of frequency marks |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
UAU201403271U UA91818U (en) | 2014-03-31 | 2014-03-31 | Generator of frequency marks |
Publications (1)
Publication Number | Publication Date |
---|---|
UA91818U true UA91818U (en) | 2014-07-10 |
Family
ID=56282655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
UAU201403271U UA91818U (en) | 2014-03-31 | 2014-03-31 | Generator of frequency marks |
Country Status (1)
Country | Link |
---|---|
UA (1) | UA91818U (en) |
-
2014
- 2014-03-31 UA UAU201403271U patent/UA91818U/en unknown
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