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Application filed by Институт Кибернетики Им. В.М.Глушкова Нан УкраиныfiledCriticalИнститут Кибернетики Им. В.М.Глушкова Нан Украины
Priority to UAU201303253UpriorityCriticalpatent/UA83134U/en
Publication of UA83134UpublicationCriticalpatent/UA83134U/en
A binary adder comprises first and second computing units, wherein first and second inputs of the binary adder are connected to corresponding inputs of first computing unit which output is connected to first input of second computing unit which second input is connected to third input of the binary adder, and output of second computing unit is connected to first output of the binary adder. Analog adder and two inverters are additionally introduced.