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Application filed by Запорізький Державний Університет, Запорожский государственный университетfiledCriticalЗапорізький Державний Університет
Priority to UA98052805ApriorityCriticalpatent/UA30568A/en
Publication of UA30568ApublicationCriticalpatent/UA30568A/en
The invention relates to the field of solid-state electronics and electronics and can be used at manufacturing the solid-state power devices, photodevices etc. The method includes the alloyed epitaxial silicone layer onto the chair plate made of alloyed silicon of monocrystal. As well as introduction into the epitaxial layer or chair plate of additional impurity that compensates a difference of lattice spacing for the chair plate and layer.
UA98052805A1998-05-291998-05-29Method for manufacturing silicone monolayer structures
UA30568A
(en)
A method for forming a power semiconductor as in figure 5 having a substrate (2), a voltage sustaining epitaxial layer (1) with at least a trench (52), a doped region (5a) adjacent and surrounding the trench.