UA147014U - DEVICE FOR CORRECTING ERROR PACKAGES USING CYCLIC CODE INTERMEDIATION - Google Patents

Abstract

The device for correcting error packets by interleaving cyclic codes consists of an interleaving unit, a communication channel, a recovery unit, the input of which is connected to the output of the communication channel, the input of which is connected to the output of the interleaving unit. Introduced demultiplexer, block of p n-bit registers, parallel encoder (n, k) -Heming code, parallel decoder (n, k) -code of Heming and multiplexer, the information output of which is the information output of the device, the information input of which is connected to information input of the demultiplexer, the p-bit information output of which is connected in accordance with p inputs of the register block, p outputs of which are connected in accordance with p inputs of the parallel encoder (n, k) -Heming code, p outputs of which are connected in accordance with p the inputs of the interleaving unit, p outputs of the recovery unit are connected in accordance with p inputs of the parallel decoder (n, k) -code of Heming, p outputs of which are connected in accordance with p information inputs of the multiplexer.

Description

The useful model belongs to computer technology and can be used in digital channels of data transmission and storage, in particular in mobile communication, in computer networks.

A well-known non-algebraic decoder of corrective codes (patent of Ukraine for a utility model Mo 84354 m. kl. НО4И 1/00, bull. Mo 20, 20131, containing a syndromic (n-K)-bit shift register with feedback, the outputs of each trigger which is connected to the inputs of the logical unit for checking syndromes according to the specified criteria, a buffer n-bit shift register, the output of which is connected to the error corrector, a device for decoupling input signals, the output of which is connected to the input of the syndromic (n-K) -bit shift register with feedback, its first input is connected to the input of the decoder, the output key is connected to the output of the error corrector and to the first output of the decoder (Output 1), an information group selection device, which is characterized by that two circuits with keys are additionally introduced, and one of them is installed between the output of the (n-K)-th cell of the buffer (n-K)-bit shift register and the second input of the device for decoupling input signals, the second is connected to output of the first trigger si ndromic (n-K)-bit shift register with feedback, and its other end is connected to the second output of the decoder (Output 1), while the syndrome modifier is again introduced, the first input of which is connected to the syndromic output (n -K)-bit shift register with feedback, the second - with the output of the logic block for checking syndromes according to the specified criteria, and the output of the syndrome modifier is connected to the third input of the junction device, and the syndromic (p -

K)-bit shift register with feedback.

The disadvantage of the known device is the complexity of the decoding procedure and a long time interval for error detection.

The closest in terms of technical substance to the proposed one is a device for correcting error packets in jamming-resistant codes (Clark J., Jr., Kane J. Kodirovanei s ispravleniemi syazhnykh v sistemas zividrovoi svyazya: translated from English. Moscow: Radio and Communication, 1987, p . 323), containing an encoder, an interleaving unit, a communication channel, a recovery unit and a decoder, the output of which is connected to the output of the device, the input of which is connected to the input of the encoder, the output of which is connected to the input of the interleaving unit, the output which is connected to the input of the communication channel, the output of which is connected to the input of the recovery unit, the output of which is connected to the input of the decoder.

The disadvantages of this device for correcting error packets in jam-resistant codes are low speed and limited functionality due to the large time spent on performing interleaving and deinterleaving operations, as well as correcting only a limited configuration of errors.

The useful model is based on the task of creating a device for correcting error packets using cyclic code interleaving, in which, due to the introduction of new blocks and connections, increased speed is achieved by accelerating the execution of interleaving and deinterleaving operations and expanding the functional capabilities of the device.

The task is solved due to the fact that the device for correcting error packets using cyclic code interleaving, which consists of an interleaving unit, a communication channel, a recovery unit, the input of which is connected to the output of the communication channel, the input of which is connected to the output of the interleaving block, introduced demultiplexer, block with

P n-bit registers, a parallel Hamming code encoder (Kk ), a parallel Hamming code decoder (Kk ) and a multiplexer, the information output of which is the information output of the device, the information input of which is connected to the information input of the demultiplexer, p -bit information output which is connected, respectively, to p inputs of the register block, p outputs of which are connected, respectively, to p inputs of the parallel coder (TQ of the Hamming code, p outputs of which are connected, respectively, to p inputs of the interleaving block, p outputs of the recovery unit are connected, respectively, to p inputs of the parallel decoder (TC of the Hamming code, p outputs of which are connected, respectively, to p information inputs of the multiplexer.

In fig. 1 presents the functional scheme of the device for correcting error packets using the interleaving of cyclic codes; in fig. 2 - the scheme of the parallel coder 6 (Kk )- code

Heming; in fig. C - the circuit of the parallel decoder 7 (LK). Hamming code; in fig. 4 - diagram of a linear sequential circuit (LSC); in fig. 5 - an example of LPS.

The device for correcting error packets using cyclic code interleaving (Fig. 1) contains an interleaving unit 1, a communication channel 2, a recovery unit 3, a demultiplexer 4, a unit 5 with. 7 n bit registers, parallel encoder 6 (TC of the Hamming code, parallel decoder 7 (TOK of the Hamming code, multiplexer 8, the output of which is connected to the information output 9 of the device, and the information input 10 of which is connected to the information input of the demultiplexer 4, p - the bit information output of which is connected to the p serial inputs of the block of registers 5, the serial outputs of which are connected to the p inputs of the parallel encoder 6 (the current of the Hamming code, the p outputs of which are connected to the p inputs of the interleaving block 1, with the information serial output of which data through the communication channel 2 is sent to the information serial input of the recovery unit 3, the P bit information output of which is connected, respectively, to the p inputs of the parallel decoder 7 (Ku. of the Hamming code, the p outputs of which are connected, respectively, to p information inputs of the multiplexer 8.

The parallel encoder 6 (TOK of the Hamming code (Fig. 2) consists of p identical sequential coding nodes, the /!th node contains LIS 11, switch 12, information input 13, information output 14; (! Z1tr ).

The parallel decoder of the 7 (Kk ) Hamming code (Fig. 3) consists of p identical sequential decoding nodes, ! -th node contains LPS 15;, error detection unit 16;, error correction unit 17, information input 18, information output 19; (! Z1tr ).

NOV 11; and NOV 15; (Fig. 4) bits 7 (hep-K) contain memory elements 20.0, 201,20, ..., 20. (7-1); adders modulo two 21.0, 21.1,...,214, 21 (-1,; information input 22, information output 23.

The device works like this.

The initial information /"-bit sequence X, which enters the input 10 of the device, is divided into p information words Y, , LENGTH K and stored for (RK) clocks of time in a block of 5 with P "7 bit registers (K -t/r. and -1tr and

Further, on the transmitter side, with the help of a parallel encoder 6 (TOK of the Hamming code, an interference-resistant coding operation is performed in parallel for all p information words of the code. The information word Y is considered as a K-bit information word of the cyclic (TC) Hamming code.

During the first K clocks of the time for coding, the first information word I is sequentially received from the first register of block 5 of the P number of bit registers. Next, for execution

The remaining information words 1551551, () are received from the interference-resistant coding operation with a time shift of one cycle relative to the adjacent information words.

During encoding to K bit information word Y; "7-bit (t-p-K) control word E of the Hamming code is added, as a result of which an array is formed from P n. bit code words 2; ; which form the coded sequence x,; .

YaeЯ»ozy de DE, Her, i-1r (2)

Simultaneously with coding, with a delay of one cycle, interleaving takes place using the interleaving unit 1 and transmitting the sequence (2) through the serial communication channel 2 in an interleaved form (first the first bits of all code words, then the second bits of all code words): , /7th digits of all codewords).The total duration of interference-resistant coding and interleaving for all p codewords is (P what! ) clocks.

When the sequence X arrives from the communication channel to the input of the receiver, it is simultaneously deinterleaved with the help of the recovery unit Z (initially it arrives

, str. . 7 p is the first code word in its entirety; then completely the second code word ut, because the code word is 2, . at. . is 3, then, with a delay of one cycle relative to the adjacent words, the corresponding code word is decoded using a parallel decoder 7 (the Hamming code CURRENT. As a result, an array of p K-bit information words (1) is restored, from which a t-bit sequence is formed X with corrected errors within the correcting ability of the Hamming code.

Serial Lead coding node, which is part of the parallel coder 6 (Ku. Hamming code, works as follows (7 Sh Ir),

The parallel encoder 6 (Ku. of the Hamming code implements the operation of systematic coding of the cyclic (Ku. of the Hamming code, i.e., to its information input 13; the K. digit . not И, . . . not the information word /, but from its information output 14; comes /"- one-bit code word 7. During the first K cycles of the coding operation, the switch 12; is in a position that allows the transmission of data from the input 13; directly to the output 14;. During the same time interval, the LPS 11; works in the formation mode 7 - digit (7 - -K) control

IS . . m words !/ Hamming code. During the following / cycles of the coding operation, switch 12; is in a position that allows the transfer of the word / to output 14..

The serial i-th decoding node, which is part of the parallel decoder 7 (Kk ) - the Hamming code, works as follows. This decoder has two modes of operation, each of which is executed in no more than /" time clocks: the error detection mode and the error correction mode. In the first mode, the code word ! is received at input 18, and with the help of LPS 15, it is calculated error syndrome 5et.().

Block 16; error detection parses error syndrome value 5beg(): null value . . . and, syndrome indicates the absence of errors in the code word '. This completes the work of the i-th decoding node. A non-zero value of the syndrome indicates the presence of at least one error in the code word!. To correct this error, unit 17 is activated; error correction. Error correction is carried out according to the Megitt method. The corrected code word is transmitted from LPS 15; on the way out on the 19th.

LPS 11; th LPS 15; represent a linear automaton that functions according to the following function of transitions зо 5(г 1) - Ах b() вх Де) (3) и - А -|а, | In-", | / . . (y) - where "7 - discrete time; t, "i - characteristic matrices; izko- (Di)- and, . . . state word (0) | in! - input word; xX is the operation of multiplication modulo 2, her is the operation of addition modulo 2.

The characteristic matrices of LIS have the form: 0 00... 85 bo 1.0shЩ.0.. 8. 81

A-|0 1 0 .. in,| В-|в, 0 001 b , 8 , (43

Matrix B | the last column of the matrix A in (4) contains the coefficients of the generating polynomial in the cyclic Hamming code of degree 7:

n 2 i- k v(x)- in two wolf ears where the coefficients are 5; can take values of 0.1), / 0-1

LPS 11; in the parallel encoder 6 (the current of the Hamming code and LPS 15; in the parallel decoder 7 (the current of the Hamming code should be built on the basis of one generating polynomial of the cyclic code. . p. -1 g. . g. .

If the matrix A has a coefficient of 5) ; Then there is a connection between the LPS output and the corresponding adder inputs modulo two, otherwise there is no corresponding connection. If in the matrix B p. -1 g. Mr. . factor 5; ; Then there is a connection between the LPS input and the corresponding adder inputs by . . . g. .-0 modulo two, otherwise there is no corresponding connection. If the coefficients 5) are simultaneously in the matrices

AB; then the LPS lacks the 7th adder modulo two.

Thanks to the interleaving, error packets up to p bits long in the X sequence are transformed into single errors in separate 7-bit code words, which allows them to be corrected using a cyclic (Kk ) Hamming code. - 4

For example, for the generating polynomial 8(х)-1 хх (7,4)- the Hamming code, the LPS will have the following characteristic matrices 0 001 1 1001 1

A - B - 0100 0 0010 0 (c)

When using characteristic matrices (5), hardware implementation of VOC 11; ii LPS 15; contain 4 memory elements 20.0, 20.1, 20.2, 20.3, two adders modulo two 21.0, 2141, information input 22, information output 23 (Fig. 5). Based on this LPS, the parallel 6 (7,4) Hamming code encoder contains four 4-bit serial encoding nodes, and the 7 (7,4) parallel Hamming code decoder contains four 4-bit serial decoding nodes. As a result, it is possible to correct a packet of errors up to 4 bits long in the 16-bit X information sequence.

In the known device, the coding and interleaving operations are performed separately, which requires a total of 2 rp time clocks.

For a cyclic Hamming code, the operations of systematic coding and interleaving require P" clocks of time each. In the proposed device, these operations are performed in parallel: each subsequent bit of the initial sequence X is coded and interleaved with a delay of one clock relative to the previous bit. Therefore, the total time spent on the side the transmitter consists of only (P what! ) clocks.

Similarly, for the cyclic Hamming code, the decoding and deinterleaving operations require P" clocks of time each. In the proposed device, these operations are performed in parallel: each subsequent bit of the code word is decoded and deinterleaved with a delay of one clock relative to the previous bit. Therefore, the total time spent on the receiver side also make up only ( рп т) measures.

Thanks to the presence of the demultiplexer 4, the multiplexer 8 can perform coding and decoding operations with interleaving when the data is received sequentially in the communication channels.

Claims (1)

FORMULATION OF THE UTILITY MODEL A device for correcting error packets by interleaving cyclic codes, which consists of an interleaving unit, a communication channel, a recovery unit, the input of which is connected to the output of the communication channel, the input of which is connected to the output of the interleaving unit, which differs in that a demultiplexer, a block of p n-bit registers, a parallel encoder of the (n, K) Hamming code, a parallel decoder of the (n, K) Hamming code and a multiplexer, the information output of which is the information output of the device, the information input which is connected to the information input of the demultiplexer, the p-bit information output of which is connected, respectively, to the p inputs of the block of registers, the p outputs of which are connected to the p inputs of the parallel encoder (n, K) Hamming code, the p outputs of which are connected to are connected, respectively, to r inputs of the interleaving unit, p outputs of the recovery unit are connected, respectively, to r inputs of the parallel Hamming (n, K)-code decoder, whose p outputs are connected, respectively, to p information those inputs of the multiplexer. - I zhk x i s in 3. -K a she Fig. 1 mon we: BUT, | | Now, write, write tire is