UA101638C2 - Data processing device and data processing method - Google Patents

Abstract

A data processing device and method in which resistance to an error of the code bit of an LDPC code such as a burst error or an erasure can be improved. If two or more code bits of the LDPC (Low Density Parity Check) code is one symbol, a column twist interleaver (24) performs rearrangement processing to rearrange the code bits of the LDPC code so that the code bits corresponding to one arbitrary row of a cheek matrix arc not mapped by the one symbol. The data processing device and method can be applied to, e.g., a transmitter to transmit an LDPC code.

Description

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

The field of technology to which the invention belongs

The present invention relates to a data processing device and to a data processing method, in particular to a data processing device and to a data processing method that can improve, for example, resistance to packet errors or erasures, for example, Low Density Parity Code (LDC).

Technical level

The GORS code has a high ability to correct errors and in recent years has become widely used in transmission systems, including satellite digital broadcasting systems, such as, for example, the OMV-5.2 system used in Europe (see, for example, Non-Patent Document 1). Further, studies were conducted to adapt the GORS code also to terrestrial digital broadcasting of the next generation.

A recent study found that the GORS code provides bandwidth close to the limit

Shannon, as the length of the code increases, similar to turbo code, etc. Further, since the GORS code has the property that the minimum distance increases in proportion to the length of the code, its feature is that it has an excellent characteristic of the block error probability. In addition, its advantage lies in the fact that the so-called phenomenon of the ceiling of errors, which is observed in the decoding characteristics of the turbo code, etc., rarely occurs.

Below is described, in particular, such a GORS code as described above. It should be noted that the GORS code is a linear code, and although it does not necessarily have to be a two-dimensional code, the following description is given on the assumption that it is a two-dimensional code.

The GORS code has the most significant characteristic that the parity check matrix defining the GORS code is a sparse matrix. Here, a sparse matrix is a matrix in which the number of elements whose value is "1" is very small (a matrix in which almost all elements are "0".

Fig. 1 shows an example of the HORS code parity check matrix.

In the matrix H of parity checks in Fig. 1 the weight of each column (column weight) (number of units) (weight) is "Z" and the weight of each row (row weight) is "b".

When coding with GORS codes (GORS coding), for example, the generating matrix C is formed on the basis of the parity check matrix H, and this generating matrix C is multiplied by bits of two-dimensional information to obtain a code word (I OROS code).

In particular, the encoding device performing GORS encoding first calculates the generating matrix b that satisfies the expression CH"-O, together with the transposed matrix H" from the parity check matrix H. Here, if the generating matrix of OS is a matrix of size K x M, the coding device multiplies the generating matrix, co, by a bit line (vector y) with K information bits to obtain a code word c (- b) of M bits. This code word (GORS code) produced by the coding device is received by the receiving party through a predetermined communication path.

The decoding of the GORS code can be carried out using the algorithm proposed by Gallagher as probabilistic decoding (probabilistic decoding), that is, the algorithm for transmitting a message by trust propagation on the so-called Tanner graph, which includes a variable node (also called a message node) and a verification node. In the following description, each variable node and validation node are simply referred to as a node.

Fig. 2 illustrates the procedure for decoding the GORS code.

It should be noted that in the following description, the real numerical value, where "0" is the probability in the value of the nth code digit in the GORS code (one code word), accepted by the receiving party, is presented in the logarithmic ratio of probabilities and is called the accepted poi value. Next, the message coming out of the check node is represented as c), and the message coming out of the variable node is represented as m.

First, when decoding the GORS code, as can be seen from Fig. 2, the GORS code is accepted, and the message (message of the verification node) and; is initialized to "0", and in addition, the variable K, which is assumed to be a whole as a cyclic variable of repeated processes, is initialized to "0" at step 511, after which the processing proceeds to step 512. At step 512, a mathematical operation represented by the expression (1) is performed (mathematical operation of the variable node) on the basis of the accepted value of tso, obtained by receiving the GORS code, to find the message (message of the variable node) m. Next, the mathematical operation represented by expression (2) (mathematical operation of the verification node) is performed based on the message m; to determine the message i).

The expression pi mi -Tsoi- U tsi i-1 0)

IExpression 21 сх ас-1 : ип з - ее и- (2)

Here, du and as in expression (1) and expression (2) are parameters that can be chosen arbitrarily and represent the number of units in the vertical direction (column) and horizontal direction (row) of the parity check matrix H. For example, in the case of code (3, 6) we have du-zZ and do-6.

It should be noted that in the mathematical operation of the variable node in expression (1) and the mathematical operation of the check node in expression (2), the range of the mathematical operation is from 1 to du - 1 or from 1 to as - 1, because the message entered from the edge ( the line crossing the variable node and the check node) from which the message should be output is not the object of a mathematical operation. Meanwhile, the mathematical operation of the verification node in expression (2) is carried out by constructing a table for the function in advance

B(mi, mg), represented by expression (3), defined by one output in relation to two inputs mi and m", and using this table sequentially (recursively), as represented by expression (4).

IVExpression C) x - 2iapy""Yappu/2apnm" /2)1- (um) (3)

Expression 4) chu - (M, A(Ma, A(uz,.. P(ma, 2 Ma; -1)))) (4)

In step 512, the variable K is incremented by "1", and processing proceeds to step 513. In step 513, a decision is made whether the variable K exceeds a predetermined number C of times of repeated decoding.

If at step 513 it is decided that the variable K is not higher than C, processing returns to step 512, and then the same processing is repeated.

On the other hand, if it is decided in step 513 that the variable K exceeds C, processing proceeds to step 514, in which the message mi is determined and output as the result of decoding to be output by performing the mathematical operation represented by expression (5), whereby the process of decoding the GORS code ends.

IExpression 5) a mi-tsoi U tsi

I-1 (5)

Here, the mathematical operation on the expression (5) is carried out, in contrast to the mathematical operation of the variable node on the expression (1), using the message и; from all edges connected to the variable node.

Fig. C illustrates an example of the HORS (3, 6) code parity check matrix (coding rate 1/2, code length 12).

In the matrix H of parity checks in Fig. The weight of the column is 3, and the weight of the row is 6, similarly to the example in Fig. 1.

Fig. 4 shows the Tanner graph for the parity check matrix H of FIG. 3.

Here in Fig. 4, the check node is represented by the "«" icon, and the variable node is represented by the "-" icon.

A check node and a variable node correspond to a row and a column of the parity check matrix H, respectively. The connection between a check node and a parity node is an edge and corresponds to the "1" element in the parity check matrix.

In particular, when the element in the |th row of the ith column of the parity check matrix is equal to 1, the ith variable node (node "-") from above and the |th check node (node "-") from above are connected by an edge. This edge represents that the code bit corresponding to the variable node has a constraint condition corresponding to the check node.

In the product-of-sums algorithm (product-of-sums algorithm), which is a method of decoding for AND ORS codes, the mathematical operation of the variable node and the mathematical operation of the verification node are performed multiple times.

Fig. 5 illustrates a variable node mathematical operation performed on a variable node.

In relation to the variable node, the message m corresponding to the edge to be calculated is determined by the mathematical operation of the variable node according to expression (1), which uses the messages и and Ц2 from other edges connecting to this variable node, and the accepted value of poi . Also, the message corresponding to any other edge is defined similarly.

Fig. 6 illustrates the mathematical operation of the verification node performed in the verification node.

Here, the mathematical operation of the verification node according to expression (2) can be carried out if we rewrite expression (2) into expression (6) using the relationship in the expression a (b-:ehrIpOa|) z Ip(Tsb|)) (zidp(a) - vdp(r). It should be noted that 5idp(a) is equal to 1 when x 2 0, but is equal to -1 when "0.

IExpression 6) sht mi cy-2giapy. P ip) - : 2 and-1

And | according to m ds-1. m -2giapp |ehri U. ni epn 2 | х P zogtaln Z) - ny 2 ny 2 i -1 i-1 (6) in : 5 | (|| b -2giapp ehri-| U -Ipiiapn - x Pziop(mi) i- 2 i-

Next, if x » 0, the function φ (x) - Ип(app(x/2)), then, since the expression ф" (x) - app (х) is satisfied, expression (b) can be transformed into expression (7) .

IExpression 7 with ais -1 ace - 1 sh-F7 Um) x Pidp) i-1 i-1 (7)

In the verification node, the mathematical operation of the verification node according to expression (2) is performed according to expression (7).

In particular, in the verification node, the message c) corresponding to the edge to be calculated is determined by the mathematical operation of the verification node according to expression (7) using the messages mi, mg, mz, ma and m5 from other edges connecting to this node checks Also, the message corresponding to any other edge is defined similarly.

It should be noted that the function φ(х) in expression (7) can also be represented in the form Ф(х) - Ип((ех 1у'у(ех- 1)), and if х » 0, then ф(х) - Ф"(x). When the functions ф(x) and ф"(x) are implemented in hardware, where they are sometimes implemented using a lookup table (OT), such lookup tables become the same lookup table.

Non-patent document 1: OMV-5.2: ET5I EM 302 307 M1.1.2 (2006-06).

The essence of the invention

Technical problem

Although GORS codes are known to exhibit very high bandwidth in the additive white Gaussian noise (AM/CM) communication path, in recent years it has become clear that even in other communication paths they have a higher error correction capacity than traditional convolutional codes or connection codes from convolutional codes and Reed-Solomon (KB) codes.

In short, if a code with good performance in the AMMOM communication path is chosen, then this code often has better performance than other codes, also in other communication paths.

In this case, it is proposed that, for example, in the case when the GORS codes are used for terrestrial digital broadcasting, the GORS codes provided for in the UOMV-5.2 standards and the modulation systems proposed in the OMV-T standards are combined and an interleaver (bit interleaver) is provided for interleaving of code bits of the GORS code between GORS coding and modulation to improve the performance of IGORS codes in the AUMOM communication path.

However, packet errors or erasures sometimes occur in the communication path that is meant when considering surface waves. For example, in a multiplexing system with orthogonal frequency division of channels (OBOM) in a multipath environment, in which the ratio of useful and unwanted signals (0/)) is equal to 0 av (the power of the unwanted signal - the echo is equal to the power of the useful signal - the main path), the power of a particular symbol becomes zero (erasure) in response to the delay of the echo (of tracts other than the main tract).

Further, also in the case of jitter (a communication path in which an echo is added, the delay of which is zero and to which the Doppler frequency is applied), when B/) is equal to 0 av, there is a case in which the power of the entire OBOM symbol at a specific time decreases to zero (erasure) due to the Doppler frequency.

Conventionally, in addition, a communication path in which such packet errors or erasures occur as described above uses an error correcting code with high performance in the communication path

AJMIM

At the same time, when decoding GORS codes, since the mathematical operation of the variable node according to expression (1), in which the addition of (accepted values of tsoi)) code bits of the GORS code, as can be seen from Fig. 5, the parity check is carried out in the column of the H matrix, and therefore, the node of the variable corresponding to the code bit of the code

GORS, if an error occurs in the code bit used for this mathematical operation of the variable node, the precision of the message to be found falls.

Then, since when decoding the GORS code, the message found in the variable node connecting to the verification node is used to perform the mathematical operation of the verification node according to the expression (7) in the verification node, if the number of verification nodes, where (the code bits of the GORS code, corresponding to) the set of variable nodes connected to it show an error (including erasure), at the same time becomes large, the quality of decoding deteriorates.

For example, if two or more variable nodes connected to a validation node suffer from erasure at the same time, that validation node returns a message that the probability that the value could be 0 and the probability that the value could be equal to 1, equal to each other for all nodes of the variable. In this case, those validation nodes in which this probability level message does not contribute one cycle of decoding processing (one set of variable node math operation and validation node math operation), and as a result, an increased number of repetitions of decoding processing is required. Consequently, the decoding quality deteriorates. Further, the power consumption in the receiving device 12, which performs decoding of the I ORS code, increases.

Accordingly, a method of improving resistance to packet errors or erasure while maintaining quality in the communication path with AM/USM is currently needed.

Here, it is proposed that the performance of GORS codes in the AM/UM communication path be improved by providing an interleaver to interleave the code bits of the GORS code between IOR coding and modulation as described above, and if this interleaver can perform interleaving to reduce the probability that that a set of variable nodes (code bits of GORS codes corresponding to these nodes) connected to the verification node can detect an error, then the quality of decoding can be improved.

The present invention is made taking into account such a situation as described above, and makes it possible to improve the resistance to errors of the code bits of the ORS code, such as packet errors or erasures.

Technical solution

The data processing device according to the first object of the present invention is a data processing device that interleaves data and contains a permutation means to perform when the code bits of the code

GORS (low-density parity-checked) is transmitted as a symbol or symbols formed by each of its two or more code bits, the process of permuting the code bits of a GORS code so that a set of code bits corresponding to the value 1 included in one arbitrary row of the check matrix on parity, not included in the same symbol.

The data processing method according to the first object of the present invention is a data processing method for a data processing device that interleaves data, which includes a step carried out by the data processing device to perform when the code bits of the GORS code (low density with parity control) transmitted as a symbol or symbols formed by each of its two or more code bits, permuting the code bits of the GORS code so that a set of code bits corresponding to the value 1, included in one arbitrary line of the parity check matrix, are not included in the same symbol.

In such a first object, as described above, when a GORS (low density parity-checked) code is transmitted as a symbol or symbols formed by each of two or more of its code bits, the data processing device permutes the code bits of the GORS code so that the set code bits corresponding to the value 1, included in one arbitrary row of the parity check matrix, are not included in the same symbol.

The data processing device according to the second object of the present invention is a data processing device that accepts the GORS code (low density with parity control) transmitted to it in an interleaved form as a symbol or symbols formed by each of two or more code bits, and contains in itself a reverse permutation means to perform, for the GORS code obtained by performing the process of permuting the code bits of the GORS code so that a set of code bits of the GORS code corresponding to the value 1, included in one arbitrary line of the parity check matrix, are not included in one and the same symbol, a reverse permutation process that is a reverse permutation corresponding to a permutation process, and a GORS decoding means to perform GORS decoding of the GORS code for which the reverse permutation process is performed.

The method of data processing according to the second object of the present invention is a method of data processing for a data processing device that accepts a GORS (low density with parity control) code transmitted to it in an interleaved form as a symbol or symbols formed by each of two or more code bits , and includes a step performed by the data processing device to perform, for the AND ORS code, obtained by performing the process of permuting the code bits of the GORS code so that a set of code bits of the GORS code that correspond to the value 1 are included in one arbitrary row of the verification matrix per parity, not included in the same symbol, a reverse permutation process, which is a reverse permutation corresponding to the permutation process, and a step performed by the data processing device to decode the AND OPC of the AND OPC code for which the reverse permutation process is performed.

In such a second object, as described above, for the GORS code obtained by performing the permutation process, a reverse permutation process is performed, which is a reverse permutation corresponding to the permutation described above, and the GORS decoding of the GORS code for which the reverse permutation process is performed .

A data processing device according to a third object of the present invention is a data processing device that interleaves data and includes a permutation means to perform when a HORS (low density parity check) code in which the information matrix is that part of its verification matrix per parity corresponding to the information bits of the GORS code and has a cyclic structure is transmitted as a symbol or symbols formed by each of two or more code bits, while a symbol is formed from the code bits of the GORS code, which are written in a column direction in the storage means for storing the code bits bits of the GORS code in the row direction and in the direction of the column and are read in the direction of the row from the storage medium, interleaving the scrolling of the columns by changing the starting position of the write, when the code bits of the GORS code are to be written in the direction of the column in the storage medium, for each column in the storage medium as a process permutations for permuting the code bits of the I ORS code.

The data processing method according to the third object of the present invention is a data processing method for a data processing device that interleaves the data, including a step performed by the data processing device to perform when the HORS (low density parity check) code, in to which the information matrix, which is that part of its parity check matrix corresponding to the information bits of the GORS code, and which has a cyclic structure, is transmitted as a symbol or symbols formed by each of two or more code bits, while a symbol is formed from the code bits code

GORS, which are written column-wise in the storage medium for storing the code bits of the code

GORS in the row direction and in the column direction and are read in the row direction from the storage medium, interleaving the scrolling of the columns by changing the initial position of the record, when the code bits of the code

The GORS are written column-wise in the storage medium, for each column in the storage medium, as a permutation process to permute the code bits of the GORS code.

In such a third object, as described above, interleaving the scrolling of the columns by changing the start position of the write, when the code bits of the GORS code are to be written in the direction of the column in the storage means, for each column in the storage means, is performed as a permutation process to rearrange the code bits of the I code ORS.

The data processing device according to the fourth object of the present invention is a data processing device that accepts a GORS (low density with parity control) code transmitted to it in an interleaved form as a symbol or symbols formed by each of two or more code bits, and contains in itself a reverse permutation means to perform when the GORS code is a GORS code in which the information matrix, which is that part of its parity check matrix corresponding to the information bits of the GORS code in the parity check matrix of this GORS code, has a cyclic structure, and the symbol is formed from the code bits of the I ODS code, which are written in the column direction in the storage means for storing the code bits of the HORS code in the row direction and in the column direction and read out in the row direction from the storage means, for the HORS code obtained by interleaving the scrolling of the columns by change of the initial position of writing, when the code digits of the GORS code are to be written in the direction of the column in for storage itself, for each column in the storage medium, as a permutation process for permuting the code bits of the GORS code, a reverse permutation process, which is the reverse permutation corresponding to the permutation process, and a GORS decoding means to perform AND ORS decoding of the GORS code for which the process is carried out reverse permutation.

The data processing method according to the fourth object of the present invention is a data processing method for a data processing device that accepts a GORS code (density string with parity control) transmitted to it in an interleaved form as a symbol or symbols formed by each of two or more code bits , which includes a step performed by the data processing device to perform when the code

A GORS is a GORS code in which the information matrix, which is that part of its parity check matrix, corresponds to the information bits of the GORS code in the parity check matrix of this code

GORS, has a cyclic structure, and the symbol is formed from the code bits of the GORS code, which are written in the column direction in the storage medium for storing the code bits of the GORS code in the row direction and in the column direction, and read out in the row direction from the storage medium, for the GORS code received by interleaving the scrolling of the columns by changing the starting position of the recording, when the code bits of the GORS code are to be written in the direction of the column in the storage medium, for each column in the storage medium as a permutation process to rearrange the code bits of the GORS code, a reverse permutation process, which is a reverse permutation, corresponding to the permutation process, and a step performed by the data processing device to decode the AND ORS of the GORS code for which the reverse permutation process is performed.

In such a fourth object, as described above, a reverse permutation process, which is a reverse permutation corresponding to a permutation process, is performed on the GORS code obtained by performing column scroll interleaving as a permutation process, and the AND ORS decoding of the GORS code is performed for which the process of reverse permutation is carried out.

It should be noted that the data processing device can be an independent device, or it can be an internal unit that is a separate device.

Beneficial effects

With the first - fourth objects according to this invention, the resistance to errors of the code bits of the I ORS code can be improved.

Brief description of the drawings

Fig. 1 illustrates the matrix H of the GORS code parity check.

Fig. 2 is a block diagram of the algorithm illustrating the procedure for decoding the I ORS code,

Fig. C illustrates an example of a GORS code parity check matrix.

Fig. 4 shows the Tanner graph for the parity check matrix.

Fig. 5 shows the variable node.

Fig. 6 shows the inspection unit

Fig. 7 shows an example of an embodiment of a transmission system in which the present invention is applied.

Fig. 8 is a block diagram showing an exemplary embodiment of the transmission device 11.

Fig. 9 illustrates a parity check matrix.

Fig. 10 illustrates the parity matrix.

Fig. 11 illustrates the matrix for checking the parity of the GORS code and column weights proposed by the YuOMV-5.2 standard.

Fig. 12 illustrates placement of 160OAM signal points.

Fig. 13 illustrates placement of signal points 640AM.

Fig. 14 illustrates the placement of the 640OAM signal points.

Fig. 15 illustrates placement of signal points 640OAM.

Fig. 16 illustrates processing in demultiplexer 25.

Fig. 17 illustrates processing in demultiplexer 25.

Fig. 18 shows a Tanner graph related to the decoding of the GORS code.

Fig. 19 shows the Ht parity matrix having a step structure and the Tanner graph corresponding to this Ht parity matrix.

Fig. 20 shows the parity matrix Ht for the parity check matrix H corresponding to the GORS code after parity interleaving.

Fig. 21 illustrates the transformed parity check matrix.

Fig. 22 illustrates the processing in the interleaver 24 of scrolling columns.

Fig. 23 illustrates the number of columns in the memory 31 required to interleave the scrolling of the columns and the address of the recording of the starting positions.

Fig. 24 illustrates the number of columns in the memory 31 required to interleave the scrolling of the columns and the address of the recording of the starting positions.

Fig. 25 is a block diagram of an algorithm illustrating the transmission process.

Fig. 26 shows the model of the communication path adopted in the simulation.

Fig. 27 illustrates the relationship between the frequency of occurrence of errors obtained by simulation and the Doppler frequency of jitter.

Fig. 28 illustrates the relationship between the frequency of occurrence of errors obtained by simulation and the Doppler frequency of distortions.

Fig. 29 is a block diagram showing an exemplary embodiment of the receiving device 12.

Fig. 30 is a block diagram of an algorithm illustrating the receiving process.

Fig. 31 illustrates an example of a GORS code parity check matrix.

Fig. 32 illustrates a matrix (transformed parity check matrix) obtained by applying row swap and column swap to the parity check matrix.

Fig. 33 illustrates a transformed parity check matrix divided into blocks of 5 x 5 bits.

Fig. 34 is a block diagram showing an exemplary embodiment of a decoding device in which the mathematical operation of a node is performed jointly for P nodes.

Fig. 35 is a block diagram showing an example of the implementation of the I ORS decoding section 56.

Fig. 36 is a block diagram showing an exemplary embodiment of a computer to which the present invention is applied.

Fig. 37 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 2/3 and a code length of 16,200.

Fig. 38 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 2/3 and a code length of 64,800.

Fig. 39 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 2/3 and a code length of 64,800.

Fig. 40 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 2/3 and a code length of 64,800.

Fig. 41 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 3/4 and a code length of 16,200.

Fig. 42 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 3/4 and a code length of 64,800.

Fig. 43 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 3/4 and a code length of 64,800.

Fig. 44 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 3/4 and a code length of 64,800.

Fig. 45 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 3/4 and a code length of 64,800.

Fig. 46 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 4/5 and a code length of 16,200.

Fig. 47 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 4/5 and a code length of 64,800.

Fig. 48 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 4/5 and a code length of 64,800.

Fig. 49 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 4/5 and a code length of 64,800.

Fig. 50 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 4/5 and a code length of 64,800.

Fig. 51 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 5/6 and a code length of 16,200.

Fig. 52 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 5/6 and a code length of 64,800.

Fig. 53 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 5/6 and a code length of 64,800.

Fig. 54 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 5/6 and a code length of 64,800.

Fig. 55 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 5/6 and a code length of 64,800.

Fig. 56 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 8/9 and a code length of 16,200.

Fig. 57 illustrates an example of a table of initial values of the parity check matrix for an encoding rate of 8/9 and a code length of 64,800.

Fig. 58 illustrates an example of a table of initial values of the parity check matrix for an encoding rate of 8/9 and a code length of 64,800.

Fig. 59 illustrates an example of a table of initial values of the parity check matrix for an encoding rate of 8/9 and a code length of 64,800.

Fig. 60 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 8/9 and a code length of 64,800.

Fig. 61 illustrates an example table of initial parity check matrix values for a coding rate of 9/10 and a code length of 64,800.

Fig. 62 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 9/10 and a code length of 64,800.

Fig. 63 illustrates an example table of initial parity check matrix values for a coding rate of 9/10 and a code length of 64,800.

Fig. 64 illustrates an example table of initial parity check matrix values for a coding rate of 9/10 and a code length of 64,800.

Fig. 65 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 1/4 and a code length of 64,800.

Fig. 66 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 1/4 and a code length of 64,800.

Fig. 67 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 1/3 and a code length of 64,800.

Fig. 68 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 1/3 and a code length of 64,800.

Fig. 69 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 2/5 and a code length of 64,800.

Fig. 70 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 2/5 and a code length of 64,800.

Fig. 71 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 1/2 and a code length of 64,800.

Fig. 72 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 1/2 and a code length of 64,800.

Fig. 73 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 1/2 and a code length of 64,800.

Fig. 74 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 3/5 and a code length of 64,800.

Fig. 75 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 3/5 and a code length of 64,800.

Fig. 76 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 3/5 and a code length of 64,800.

Fig. 77 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 1/4 and a code length of 16,200.

Fig. 78 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 1/3 and a code length of 16,200.

Fig. 79 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 2/5 and a code length of 16,200.

Fig. 80 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 1/2 and a code length of 16,200.

Fig. 81 illustrates an example table of initial parity check matrix values for a coding rate of 3/5 and a code length of 16,200.

Fig. 82 illustrates an example of a table of initial values of the parity check matrix for a coding rate of 3/5 and a code length of 16,200.

Fig. 83 illustrates a method of finding the parity check matrix H from the initial parity check matrix table.

Fig. 84 illustrates an example of replacing code bits.

Fig. 85 illustrates another example of replacing code bits.

Fig. 86 illustrates an additional example of replacing code bits.

Fig. 87 illustrates another example of replacing code bits.

Fig. 88 illustrates the result of VEK modeling.

Fig. 89 illustrates another result of VEK simulation.

Fig. 90 illustrates an additional result of VEK simulation.

Fig. 91 illustrates another result of VEK modeling.

Fig. 92 illustrates an example of replacing code bits.

Fig. 93 illustrates another example of replacing code bits.

Fig. 94 illustrates an additional example of replacing code bits.

Fig. 95 illustrates another example of replacing code bits.

Fig. 96 illustrates another example of replacing code bits.

Fig. 97 illustrates another example of replacing code bits.

Fig. 98 illustrates another example of replacing code bits.

Fig. 99 illustrates another example of replacing code bits.

Fig. 100 illustrates another example of replacing code bits.

Fig. 101 illustrates another example of replacing code bits.

Fig. 102 illustrates another example of replacing code bits.

Fig. 103 illustrates another example of replacing code bits.

Fig. 104 illustrates processing in the multiplexer 54, which is the deinterleaver 53.

Fig. 105 illustrates the processing in the deinterleaver 55 of scrolling columns.

Fig. 106 is a block diagram showing another embodiment of the receiving device 12.

Fig. 107 is a block diagram showing a first embodiment of a receiving system that may be used in the receiving device 12.

Fig. 108 is a block diagram showing a second embodiment of a receiving system that may be used in the receiving device 12.

Fig. 109 is a block diagram showing a third embodiment of a receiving system that may be used in the receiving device 12.

Explanation of references 11 - Transmission device; 12 - Receiving device; 21 - GORS coding section; 22 - Bit interleaver; 23 - Parity interrupter; 24 - Column scrolling switch; 25 -

Demultiplexer; 26 - Display section; 27 - Orthogonal modulation section; 31 - Memory; 32 -

Replacement section; 51 - Orthogonal demodulation section; 52 - Reverse reflection section; 53 -

Deinterleaver; 54 - Multiplexer; 55 - Deinterrupter scrolling columns; 56 - GORS decoding section; 300 - Memory device for edge data; 301 - Selector; 302 - Section of the calculation of the verification node; 303 - Cyclic shift chain; 304 - Memory device for edge data; 305 - Selector; 306 - Memory of received data; 307 - Variable node calculation section; 308 -

Cyclic shift chain; 309 - Decoded word calculation section; 310 - Section of permutation of received data; 311 - Decoded data reorganization section; 401 - Tire; 402 - CPU; 403 - PZP; 404 -

RAM; 405 - Hard disk; 406 - Output section; 407 - Input section; 408 - Communication Section; 409 - Drive; 410 - Input - output interface; 411 - Removable recording medium; 1001 - Reverse replacement section; 1002 -

Memory; 1011 - Parity deinterleaver; 1021 - GORS decoding section; 1101 - Receiving section; 1102 - Transmission line decoding processing section; 1103 - Information source decoding processing section; 1111 - Output section; 1121 - Recording section.

The best option for implementing the invention

Fig. 7 shows an example of the configuration of an embodiment of the transmission system to which the present invention is applied (the term "system" means a logical assembly of a plurality of devices, regardless of whether the individual components of the device are included in a single body).

In Fig. 7, the transmission system includes a transmitting device 11 and a receiving device 12.

The transmission device 11 is, for example, a device that transmits a television broadcast program and transmits object data that is an object to be transmitted, such as image data, sound data, and so on, as a television broadcast program, for example, through satellite channel or surface waves.

The receiving device 12 is, for example, a tuner or a television receiver for receiving a television broadcasting program and receives the object data transferred to it from the transmitting device 11.

Fig. 8 shows an example of the transmission device 11 of FIG. 7.

In Fig. 8, the transmission device 11 includes a GORS coding section 21, a bit interleaver 22, a display section 26 and an orthogonal modulation section 27.

Object data is submitted to section 21 of the I ORS coding.

The HORS encoding section 21 carries out HORS encoding of the object data submitted to it according to the parity check matrix, in which the parity matrix with a part corresponding to the parity bits of the code

GORS has a step structure and issues the I ORS code, in which the object data are information bits.

In particular, section 21 of GORS coding carries out encoding of G(ORS) object data into the GORS code proposed, for example, in the ЮОМВ-5.2 standards, and issues the GORS code obtained as a result of this GORS encoding.

Here, the GORS code proposed in the OMV-5.2 standard is an irregular repetitive accumulating code (IKA) and the parity matrix in the parity check matrix of this GORS code has a step structure. The parity matrix and ladder structure are described here below. Further, the IKA code is described, for example, in the article "Igedshag Kereai-Assitiyae Sodev", N. ip, A. KnNapaekKag, apa VA.). MeBiPepse, ip

Rgoseyedipdz oi 2pa Ipiegpayopa! Zutrozisht op Tigro sodez apa Reiaiea Torisv, yr. 1-8, Zeri. 2000

The GORS code derived from the GORS coding section 21 is fed to the bit interleaver 22.

The bit interleaver 22 is a data processing device for interleaving data and includes a parity interleaver 23, a column scroll interleaver 24 and a demultiplexer (OEMIX) 25.

The parity interleaver 23 performs parity interleaving to interleave the parity bits of the GORS code from the GORS coding section 21 in the position of the other parity bits and supplies this GORS code after parity interleaving to the column scroll interleaver 24.

Column scroll interleaver 24 performs column scroll interleaving for GORS code from parity interleaver 23 and supplies GORS code after column scroll interleaving to demultiplexer 25.

In particular, the GORS code is transmitted after two or more of its bits are mapped into signal dots representing one orthogonal modulation symbol by the mapping section 26 described below.

The column scrolling interleaver 24 performs, for example, such column scrolling interleaving, which is described below as the process of permuting the code bits of the TORS code from the parity interleaver 23, so that a plurality of code bits of the GORS code corresponding to the value 1 are included in one arbitrary row of the check matrix on parity used in section 21 coding

GORS, are not displayed in one symbol.

The demultiplexer 25 carries out the process of replacing the positions of two or more code bits of the GORS code from the interleaver 24 of scrolling the columns that are displayed in the symbol to obtain the AND ORS code, which has enhanced resistance to AM/OM, and supplies two or more code bits of the received GORS code to the section 26 reflections.

The display section 26 maps two or more code bits of the GORS code from the demultiplexer 25 to the signal points determined by the orthogonal modulation (multi-valued modulation) modulation method implemented by the orthogonal modulation section 27.

In particular, the mapping section 26 maps the GORS code from the demultiplexer 25 into a symbol (symbol value) represented by a signal point determined by the modulation system on the IS plane) (constellation

IO), defined by axis I, which represents the in-phase component I, which is in phase with the carrier, and axis c), which represents the quadrature component 0, which is orthogonal to the carrier oscillation.

Here, as the orthogonal modulation modulation method implemented by the orthogonal modulation section 27, modulation methods including, for example, the modulation method defined by the standards are available

OMUV-T, that is, for example, ORZK (quadrature phase manipulation), 16O9AM (quadrature amplitude modulation), 640OAM, 256OAM, 10240OAM, 4096O0AM and so on. Which modulation method should be used for the orthogonal modulation to be performed by the orthogonal modulation section 27 is established in advance, for example, according to the operation of the transmission device 11 by the operator. It should be noted that the orthogonal modulation section 27 can perform some other orthogonal modulation, such as, for example, 4RAM (pulse amplitude modulation).

The symbol received by the display section 26 is fed to the orthogonal modulation section 27.

The orthogonal modulation section 27 carries out orthogonal modulation of the carrier according to the symbol from the display section 26 and transmits the modulated signal obtained by orthogonal modulation.

Now, Fig. 9 illustrates the matrix H of the parity check used in the encoding of the GORS by the section 21 of the encoding of the I ORS of FIG. 8.

The parity check matrix Н has the structure of a generating matrix of low density (МОСМ) and can be represented by the expression Н - (ИНА|ЙНт| from the information matrix Na, corresponding to the information digits, and the parity matrix Нt, corresponding to the parity digits, from the number code bits of the GORS code (a matrix in which the elements of the information matrix NA are the elements on the left side, and the elements of the parity matrix Нt are the elements on the right side).

Here, the number of bits of information bits and the number of bits of parity bits from the number of code bits of one GORS code (one code word) are called the information length K and the length M of parity, and the number of bits of code bits of one GORS code is called the code length M (- K i- M ).

The length K of the information and the length M of the parity associated with the GORS code of a certain length M of the code depend on the coding speed. At the same time, the parity check matrix H is a matrix in which the number of rows x columns is M x M. Then, the information matrix NaA is a matrix of size M x M, and the parity matrix Ht is a matrix of size M x M.

Fig. 10 illustrates the Нt parity matrix of the Н parity check matrix for the GORS code proposed in the ОМВ-5.2 standard.

The parity matrix Нt of the parity check matrix Н for the GORS code proposed in the ryuv-5.2 standard has a step structure, in which the elements with the value 1 are placed like a ladder, as seen in Fig. 10. The weight of a row of this Нt parity matrix is equal to 1 relative to the first row, but equal to 2 relative to all other rows. In this case, the weight of the column is equal to 1 relative to the last column, but equal to 2 relative to all other columns.

As described above, the GORS code of the parity check matrix H, in which the matrix Ht has a step structure, can be obtained immediately using the parity check matrix H.

In particular, the GORS code (one code word) is represented by the row vector c, and the column vector obtained by transposing the row vector is represented by c". Next, part of the information bits from the row vector c, which is the GORS code, is represented by the row vector A, and part of the parity bits is represented by the vector T line.

Here, in this case, the line vector c can be represented by the expression c - IA|T| from the string vector A as the information bits and the string vector T as the parity bits (a string vector in which the elements of the string vector A are the elements on the left side, and the elements of the string vector T are the elements on the right side).

For the matrix H check for parity and the vector c - |А|Т)| line as a GORS code must satisfy the expression Ne" - 0, where the matrix Нt of the parity of the matrix Н - ИНА|Нт| parity check has such a step structure as the one shown in Fig. 10, the vector T of the line in the role of parity bits, that forms the vector c - (AT of the row satisfying the expression Hc" - 0, can be found sequentially by setting to zero one by one the elements in the row, starting from the elements in the first row of the vector Ne" of the column in the expression Ne" - 0.

Fig. 11 illustrates the matrix H of checking the parity of the GORS code and the weight of the columns defined in the standard ruv-5.2.

In particular, part A of Fig. 11 illustrates the parity check matrix H for the GORS code defined in the OMV-5.2 standard.

In relation to KH columns from the first column of the parity check matrix H, the weight of the column is equal

X; in relation to the following short circuit columns, the weight of the column is equal to 3; in relation to the following M-1 rows, the weight of the column is equal to 2; and in relation to the last one column, the column weight is 1.

Here, KH i KZ i5- M - 1 1 is equal to the length of the M code.

In the YUMV-5.2 standard, the number of KH, KZ and M columns (parity length) as well as the weight of the columns are proposed as shown in part B of Fig. 11.

In particular, part B of Fig. 11 illustrates the numbers of KH, KZ and M columns, as well as the weight of X columns, associated with different encoding speeds of GORS codes proposed in the OMV-5.2 standard.

In the OMV-5.2 standard, GORS codes of M code length, equal to 64,800 bits and 16,200 bits, are proposed.

And, as can be seen in part B of Fig. 11, for the GORS code, the length M of which code is equal to 64,800 bits, 11 coding rates (nominal rates) 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/91 9/0, and for the GORS code, the length of M code of which is 16,200 bits, 10 coding rates are proposed 1/4, 1/3, 2/5, 1/2, 3/ 5, 2/3, 3/4, 4/5, 5/6 and 8/9.

Regarding GORS codes, it is known that the code bits corresponding to the column of the parity check matrix H, which has a higher column weight, exhibit a lower error rate.

The parity check matrix H proposed in the OMV-5.2 standard and illustrated in Fig. 11, there is a tendency for the column closer to the main side (left side) to have a higher column weight. Accordingly, the GORS code corresponding to this parity check matrix H tends to have a code bit closer to the beginning with higher error tolerance (has a higher error tolerance) and a code bit closer to the tail with a lower error tolerance. error tolerance.

Fig. 12 illustrates the placement of 16 symbols (signal points corresponding to 16 symbols) on the IC plane) when the orthogonal modulation section 27 of FIG. 8 is carried out by 160AM.

In particular, part A of Fig. 12 illustrates 16OAM symbols.

In 16O9OAM, one symbol represents 4 bits, and there are 16 (- 27) symbols. Then, these 16 symbols are arranged so that they form a square shape of 4 x 4 symbols in the direction I x direction O with the center at the origin of the coordinates of the plane I.

Now, if the 4 bits represented by one 16O0AM symbol are represented as uo, y, y" and uz in order, starting with the most significant bit, then if the modulation method is 16OAM, then the 4 code bits of the GORS code are mapped into a 4-bit symbol уо - уз, which coincide with 4 bits of section 26 of the display (Fig. 8).

Part B in Fig. 12 indicates the bit limits related to these 4 bits уоз - уз, represented by the symbol 16О0АМ.

Here, the bit boundary associated with bit y; (i-0, 1, 2, Z in Fig. 12) satisfies the boundaries between the symbol, bit y; which is equal to 0, and another symbol, bit y; which is equal to 1.

As can be seen from part B of Fig. 12, as regards the most significant bit уо from the number of 4 bits уо - уз, represented by the symbol in 160AM, only one location along the C axis) on the IC plane) constitutes a symbol boundary, and as regards the second bit у: (the second of the most significant bit ), only one location along the I axis on the IC plane) constitutes a symbolic boundary.

Next, with respect to the third bit ug, each of the two locations between the first and second columns and between the third and fourth columns to the left of the 4 x 4 symbols constitutes a boundary.

Next, with respect to the fourth bit, each of the two locations between the first and second rows and between the third and fourth rows of 4 x 4 symbols constitutes a boundary.

A bit represented by a symbol is less likely to become false as the number of symbols spaced from the boundary increases, but more likely to become false as the number of symbols closer to the bit boundary increases.

If the bit that is least likely to become false (insensitive to error) is called the "strong bit" and the bit that is most likely to become false (less insensitive to error) is called the "weak bit", then with respect to the 4 bits, the values represented symbols in 16OAM, the most significant bit uos and the second bit y: are strong bits, and the third bit y: and the fourth bit uz are weak bits.

Fig. 13 - 15 illustrate the placement of 64 symbols (signal points corresponding to 64 symbols) on the IC plane), when the orthogonal modulation section 27 of Fig. 8 is carried out by 640AM.

In 640OAM, one symbol represents 6 bits, and there are 64 (- 25) symbols. Next, these 64 symbols are placed so that they form a square of 8 x 8 symbols in the direction I x direction OO with the center at the origin of the coordinates of the plane I.

Now, assuming that the 6 bits represented by a single symbol in 640AM are represented as bits us, ui, ug, uz, uh, and uz in order, starting with the most significant bit, then when the modulation method is 640OAM, the 6 code bits of the code GORS are displayed in a symbol of 6 bits uoh - uh corresponding to 6 bits.

Here, Fig. 13 indicates the bit boundaries related to the most significant bit uobo and to the second bit y: from 6 bits us - uh, represented by symbols in 64OAM; Fig. 14 indicates the bit limits related to the third bit y" and the fourth bit uz; and Fig. 15 indicates the bit boundaries related to the fifth bit uh and to the sixth bit uh.

As can be seen in Fig. 13, the number of bit boundaries in relation to each of the most significant bit uob and the second bit y: is equal to one. At the same time, as can be seen from Fig. 14, the number of bit limits in relation to each of the third bit of y: and the fourth bit of uz is equal to two; and as can be seen from Fig. 15, the number of bit boundaries in relation to each of the fifth bit uh and the sixth bit uh is four.

Accordingly, among the bits уо - ух, represented by symbols in 64О0АМ, the most significant bit us and the second bit ui are the most significant bits, and the third bit у» and the fourth bit уз are the second most significant bits. Then, the fifth bit uh and the sixth bit uz are the weakest bits.

From Fig. 12 and further from Fig. 13 - 15 it can be seen that in relation to the bits of the orthogonal modulation symbols, there is a tendency that the high-order bit is the strong bit and the low-order bit is the weak bit.

Here, as described above with reference to Fig. 11, the GORS code derived from the GORS coding section 21 (Fig. 8) includes code bits that are error-tolerant and code bits that are less error-tolerant.

At the same time, as described above with reference to Fig. 12 - 15, the orthogonal modulation symbol bits performed by the orthogonal modulation section 27 include strong bits and weak bits.

Accordingly, if the weak bit of the orthogonal modulation symbol is assigned to the code bit of the GORS code, which has low error tolerance, then the error tolerance in general decreases.

Therefore, an interleaver is proposed that interleaves the code bits of the GORS code so that the assigned code bits of the GORS code, which have low error tolerance, are mapped to the strong bits of the orthogonal modulation symbol.

Demultiplexer 25 according to Fig. 8 performs interleaver processing.

Fig. 16 illustrates the processing of the demultiplexer 25 of FIG. 8.

In particular, part A of Fig. 16 shows an example of the functional implementation of the demultiplexer 25.

The demultiplexer 25 contains a memory 31 and a section 32 of replacement.

The I ORS code is given to memory 31.

The memory 31 has a storage capacity for storing t bits in the (horizontal) row direction and for storing M/(Itb) bits in the (vertical) column direction. Memory 31 records the code bits of the code

The GORS fed into it in the column direction and reads the code bits in the row direction, and then feeds the read code bits to the swap section 32.

Here, t represents the number of bits in the code digits of the GORS code per symbol, ar is a predetermined positive integer and is a multiplier to be used when multiplying t by this integer. At the same time, M (- length K of information - length M of parity) represents the length of the code for the GORS code, as described above.

Part A in Fig. 16 shows an example of implementation of demultiplexer 25 when the modulation system is 640OAM and, accordingly, the number of t bits in the code bits of the I ORS code per symbol is equal to 6 bits.

Next, in part A of Fig. 16, the multiplier t is equal to 1 and, accordingly, the memory 31 has a storage capacity of

M/(6 x 1) x (6 x 1) bits in column direction x row direction.

Here, the memory storage area 31 extending in the column direction and containing one bit in the row direction is hereinafter referred to as a column. In part A of Fig. 16 memory 31 contains six (- 6 x 1) columns.

The demultiplexer 25 records the code bits of the GORS code in a downward direction from the top of the column forming the memory 31 (in the column direction), starting from the left column to the column on the right side.

Then, if the writing of the code bits ends in the lowest bit of the rightmost column, the code bits are read and output to the swap section 32 in a block of 6 bits (tb bits) in the row direction, starting from the first row of all the columns that will form the memory 31 .

The replacement section 32 performs the replacement process by replacing the position of the code bits of 6 bits from the memory 31 and outputs the 6 bits obtained by replacement as 6 bits Uo uUo, u, ug, uz, Uz and uh, representing one 64OAM symbol.

In particular, if the 6 code digits read in the row direction from the memory 31 are represented as bo, Bi, p, rz, ba, and B5 in order, starting with the most significant digit, then from the column weight ratio described above with reference in Fig. 11, the code bit located in the direction of the bo bit is a code bit with high error tolerance, while the code bit in the direction of the bo bit is a code bit with low error tolerance.

The replacement section 32 performs a replacement process by replacing the position of the 6 code bits bo - b5 from the memory 31, so that the code bit having low error resistance among these 6 code bits bo - p5 from the memory 31 can be assigned to a bit , which has a high stability among bits uo - uh representing one 64OAM symbol.

Here, for the method of replacement by replacement of 6 code bits Bo - bo from memory 31 so that they are assigned 6 bits us - uh, representing one symbol of 640OAM, different systems are proposed.

Part B in fig. 16 illustrates a first replacement method; part C in Fig. 16 illustrates a second replacement method; and part 0 in Fig. 16 illustrates a third replacement method.

In parts from B to Fig. 16 to O according to Fig. 16 (similarly also in Fig. 17, described below), a linear segment connecting bits B; and y), means that the code bit is b; assigned to bit y; symbol (replaced in bit position y);).

As the first method of replacement, it is proposed to adopt one of the three types of replacement methods in Part B of

Fig. 16, and as the second method of replacement, it is proposed to adopt one of the two types of replacement methods in part C of Fig. 16.

As the third method of replacement, it is proposed to select and use six types of replacement methods in part O of Fig. 16.

Fig. 17 illustrates an example of the implementation of the demultiplexer 25 in the case when the modulation method is 640OAM (respectively, the number of t bits in the code bits of the I ORS code, displayed in one symbol, is equal to 6, similarly to what is the case in Fig. 16), and the multiplier B is 2 and also illustrates the fourth substitution method.

When the multiplier B is 2, the memory 31 has a storage capacity of M/(6 x 2) x (6 x 2) in the column direction x row direction and contains 12 (5 6 x 2) columns.

Part A in Fig. 17 illustrates the procedure for writing the GORS code into the memory 31.

The demultiplexer 25 records the code bits of the GORS code in a downward direction from the top of the column forming the memory 31 (in the column direction), starting from the left column to the column on the right side, as described hereinabove with reference to FIG. 16.

Then, if the writing of the code bits ends in the lowest bit of the rightmost column, the code bits are read and output to the swap section 32 in a block of 12 bits (tr bits) in the row direction, starting from the first row of all the columns that make up the memory 31 .

The replacement section 32 performs a replacement process by replacing the position of the code bits of 12 bits from the memory 31 according to the fourth replacement method, and outputs the 12 bits obtained by replacement as 12 bits representing two symbols (B symbols) of 6409AM, in particular, as b bits us, ui, ug, uz, ul and uB WHICH represent one 64OAM symbol, and 6 bits uo, ut, ug, uz, y« and uh representing the next one symbol.

Here, part B in Fig. 17 illustrates a fourth replacement method for the replacement process of the replacement section 32 in part A of FIG. 17.

It should be noted that which replacement method is optimal, that is, which replacement method provides an improved frequency of errors in the AMUSM communication path, varies depending on the encoding speed of the code

GORS, etc.

Now referring to FIG. 18 - 20 describes parity interleaving by the parity interleaver 23 of Fig. 8.

Fig. 18 shows the Tanner graph (part of the graph) for the GORS code parity check matrix.

If multiple variable nodes (code bits corresponding to them) connected to a check node, such as two variable nodes, suffer from an error such as erasure at the same time, as shown in

Fig. 18, then the validation node returns an equal probability message indicating that the probability that the value can be 0 and the probability that the value can be 1 are equal to each other for all variable nodes connected to that validation node. Therefore, if a plurality of variable nodes connected to the same validation node are put into an erasure state or the like at the same time, the decoding quality is degraded.

In this case, the GORS code derived from the GORS coding section 21 of FIG. 8 and proposed in the OUV-5.2 standard, is an irregular repeating accumulated (IKA) code, and the parity matrix Hn in the parity check matrix H has a step structure, as shown in Fig. 10.

Fig. 19 illustrates the Ht parity matrix with a step structure and the Tanner graph corresponding to this Ht parity matrix.

In particular, part A of Fig. 19 illustrates the Ht parity matrix with a step structure, and part B in Fig. 19 shows the Tanner graph corresponding to the Нt parity matrix from part A of FIG. 19.

When the Нt parity matrix has a step structure, in the Tanner graph of this Нt parity matrix, those nodes of the GORS code variable that correspond to the column of the element in the Нt parity matrix, which has the value 1 and whose message is transmitted using adjacent code bits (parity bits), with connected to the same verification node.

Accordingly, if the above-described contiguous parity bits are placed in a false state due to packet errors, erasures, or the like, then since the verification node is connected to a plurality of variable nodes corresponding to a plurality of parity bits that have become false (variable nodes whose messages to be found using the parity bits), returns an equal probability message indicating that the probability that the value can be 0 and the probability that the value can be 1 can be equal to each other, at variable nodes, with' connected to this validation node, the decoding quality is degraded. Then, if the packet length (the number of bits that became false due to a packet error) is large, the decoding quality degrades even more.

Therefore, in order to prevent the degradation of the decoding described above, the parity interleaver 23 (Fig. 8) performs interleaving to interleave the parity bits of the GORS code from the coding section 21

GORS in the position of other parity bits.

Fig. 20 illustrates the parity matrix Нt in the parity check matrix H corresponding to the GORS code after parity interleaving performed by the parity interleaver 23 of FIG. 8.

Here, the information matrix Na in the parity check matrix H, corresponding to the GORS code proposed in the OMV-5.2 standard and derived from section 21 of the I ODS coding, has a cyclic structure.

This cyclic structure means a structure in which some column coincides with another column in a cyclically shifted state and includes, for example, a structure in which for each P column positions the values of 1 in the rows of these P columns coincide with the positions in which the first of P of columns is cyclically shifted in the direction of the column by a value that increases in proportion to the value of d obtained by dividing the length M of parity. Hereinafter, the number P of columns in the cyclic structure is called the block number of columns of the cyclic structure.

As the GORS code proposed in the OMV-5.2 standard and derived from section 21 of the coding

ORS, two ORS codes are available, including codes with M code lengths of 64,800 and 16,200 bits, as described hereinabove with reference to FIG. 11.

Now, if from two different GORS codes, whose M code length is 64,800 and 16,200 bits, we pay attention to the GORS code, whose M code length is 64,800 bits, then eleven different encoding rates are available for this GORS code, whose M code length is 64,800 bits , as described above with reference to Fig. 11.

Regarding GORS codes, the length M of which code is equal to 64,800 bits and which have eleven different coding rates, in the OMV-5.2 standard it is proposed that the number P of columns of the cyclic structure should be 360, which is one of the divisors of the length M of the parity, except for 1 and M.

Next, for GORS codes whose code length M is 64,800 bits and which have eleven different coding rates, the length M of parity has a value other than prime numbers, and is represented by the expression M - d x r - d x 360, which uses the value 4, which varies depending on the encoding rate.

Accordingly, the value d is also one of the divisors of the length M of the parity, except for 1 and M, similarly to the number P of columns of the cyclic structure and is obtained by dividing the length M of the parity by the number P of the columns of the cyclic structure (the product of P and d, which are divisors of the length M of the parity, is is the length M of parity).

When the information length is represented by the number K, and the integer greater than 0, but less than P is represented by the number x, and the integer greater than 0, but less than d is represented by the number y, the parity interleaver 23 interleaves as the parity interleaving (К ж дх ж ю ж 1) -th code digit from the number of parity bits, which make up from (K «- 1) th to (K z M) th bits of the GORS code from section 21 of the I ORS coding, in the position (K i Ru izh x yah 1)- th code bit.

According to such parity interleaving, since variable nodes (the parity bits corresponding to these variable nodes) connected to the same check node are spaced by a distance corresponding to the number P of columns of the cyclic structure - here by 360 bits - then when the length of the packet error is less than 360 bits, it is possible to prevent the situation that multiple variable nodes connected to the same check node are received in error at the same time. As a result, packet error tolerance can be improved.

It should be noted that the GORS code after parity interleaving, in which the (К ж х х ю ю- 1)-th code digit is interleaved in the position of the (К «ж Ру «- х «- 1)-th code digit, coincides with the code I ORS of the parity check matrix (which is also called the transformed parity check matrix here), obtained by replacing the column when replacing the (Ko zh-x zh zh- zh- 1)-th column of the original parity check matrix Н with ("К я Ру иж х i 1)th column.

Next, in the parity matrix of the transformed parity check matrix, as can be seen from Fig. 20, a pseudo-cyclic structure appears, in which the block consists of P columns (in Fig. 20, it is 360 columns).

Here, a pseudo-cyclic structure means a structure having a section with a cyclic structure except for a part of it. In the column of the transformed parity check matrix, obtained by applying the replacement of the column corresponding to the parity interleaving in the parity check matrix of the GORS code proposed in the ЮОМВ-5.2 standard, a section of 360 rows x 360 columns (the shifted matrix described below) in the upper right section shorter by one element with a value of 1 (which has a value of 0). Therefore, the transformed parity check matrix does not have a (complete) cyclic structure, but has a pseudo-cyclic structure.

It should be noted that the transformed parity check matrix in Fig. 20 is a matrix in which also the row replacement for configuring the transformed parity check matrix from the above-described configured matrix is applied to the original parity check matrix H in addition to the column replacement corresponding to parity interleaving.

Now, with reference to Fig. 21 - 24, the interleaving of the scrolling of the columns by the interleaving of the scrolling of the columns of Fig. 24 is described. 8.

In the transmission device 11 according to Fig. 8, two or more code bits of the GORS code are transmitted as one symbol, as suggested above, to improve frequency efficiency.

In particular, for example, when 2 bits from the code bits are used to form one symbol, the modulation method used is, for example, FORTY, but when 4 bits from the code bits are used to form one symbol, the modulation method used is, for example, 16OAM.

In this case, when two or more code bits are transmitted as one symbol, if an erasure or the like occurs in some symbol, all of the code bits of that symbol become erroneous (erased).

Accordingly, in order to reduce the probability that multiple variable nodes (code bits corresponding to these variable nodes) connected to the same verification node may suffer from erasure at the same time, to improve decoding quality, it is necessary to avoid that the nodes of the variable corresponding to the code bits of the same symbol were connected to the same verification node.

At the same time, in the matrix H of the GORS code parity check proposed in the OMV-5.2 standard and derived from section 21 of the GORS coding, the information matrix NaA has a cyclic structure, and the matrix Ht has a step structure, as described above. Then, in the transformed parity check matrix, which is the parity check matrix of the GORS code after parity interleaving, a cyclic structure (more precisely, a pseudo-cyclic structure as described above) also appears in the parity matrix, as described in FIG. 20.

Fig. 21 shows the transformed parity check matrix.

In particular, part A of Fig. 21 illustrates a transformed parity check matrix of a parity check matrix H having a code length M of 64,800 bits and a coding rate (g) of 3/4.

In part A of Fig. The 21 position of the element with a value of 1 in the transformed parity check matrix is marked with a dot (.).

In part B of Fig. 21 shows the process carried out by the demultiplexer 25 (Fig. 8) for the GORS code of the transformed parity check matrix from part A of Fig. 21, i.e. GORS code after parity interleaving.

In part B of Fig. 21 code bits of the TORS code after parity interleaving are written in the direction of the column in four columns that form the memory 31 of the demultiplexer 25 when using 16OAM as a modulation method.

The code bits written in the direction of the column in the four columns that will form the memory 31 are read in the direction of the line in a block of 4 bits that make up one character.

In this case, the 4 code bits Vo, Vy, B" and Vz, which make up one symbol, sometimes make up the code bits corresponding to 1 and are included in an arbitrary row of the parity check matrix after the transformation according to part A of Fig. 21, and in this case the nodes of the variable corresponding to the code bits

Vo, Vy, B" and Vz are connected to the same verification node.

Accordingly, when these 4 code bits Vo, Vi, B" and Bz of one symbol become code bits corresponding to 1 and are included in an arbitrary string, if this symbol is erased, then the same verification node to which the variable nodes are attached, corresponding to the code categories Vo, Vy, B" and Vz, cannot find a corresponding message. As a result, the decoding quality deteriorates.

In addition, for coding rates other than the 3/4 coding rate, a plurality of code bits corresponding to a plurality of variable nodes connected to the same verification node sometimes compose one 16O0AM symbol similarly.

Therefore, the column scrolling interleaver 24 performs column scrolling interleaving, in which the code bits of the GORS code after parity interleaving from the parity interleaver 23 are interleaved so that a plurality of code bits corresponding to 1 and included in one arbitrary row of the transformed parity check matrix are not displayed in one symbol.

Fig. 22 illustrates interleaving column scrolling.

In particular, Fig. 22 illustrates the memory 31 (Figs. 16 and 17) of the demultiplexer 25.

The memory 31 has a storage capacity for storing tb bits in the (vertical) column direction and stores M(tb) bits in the (horizontal) row direction and contains tr columns as described in

Fig. 16. Next, the column scrolling interleaver 24 writes the code bits of the GORS code in the column direction into the memory 31 and controls the write start position when the code bits are read in the row direction to perform the column scrolling interleaving.

In particular, the column scroll interleaver 24 appropriately changes the write start position at which the writing of the code bits for each of the plurality of columns should begin, so that the plurality of code bits read in the row direction and used to obtain a single symbol may not become the code bits that correspond to 1 and included in one arbitrary line of the transformed parity check matrix (rearranges the code bits of the GORS code so that a set of code bits corresponding to 1 and included in one arbitrary line of the parity check matrix may not be included in the same symbol).

Here, Fig. 22 shows an example of a memory configuration 21 when the modulation method is 16OAM and, in addition, described above with reference to FIG. 16, the multiplier p is equal to 1. Accordingly, the number of t bits in the code digits of the I ORS code, which are to be mapped into one symbol, is 4 bits, and the memory 31 is formed from four (- tb) columns.

Interleaver 24 for scrolling the columns of Fig. 22 (instead of the demultiplexer 25 shown in Fig

Fig. 16) records the code bits of the GORS code in the downward direction (column direction) from above in the four columns that form the memory 31, starting from the left column to the column on the right side.

Then, when the writing of the code bits ends in the rightmost column, the column scrolling interleaver 24 reads the code bits in a block of 4 bits (th bits) in the row direction, starting from the first row of all the columns that make up the memory 31, and outputs these code bits bits as a GORS code after interleaving the scrolling of the columns into the replacement section 32 (Figs. 16 and 17) of the demultiplexer 25.

However, if the address of the main (uppermost) position of each column is represented by 0 and the addresses of the positions in the direction of the column are represented by integers in descending order, then the interleaver 24 of scrolling the columns of FIG. 22 sets the starting position of the entry for the leftmost column to the position whose address is equal to 0; sets for the second column (left) the initial position of the record to the position whose address is equal to 2; sets for the third column the initial position of the record to the position whose address is equal to 4; and sets the fourth column to the starting position of the entry at the position whose address is 7.

It should be noted that with respect to columns for which the starting position of the entry is any other position than the position whose address is equal to 0, after the code bits are written to the bottommost position, the entry position is returned to the top (to the position the address of which is equal to 0), and recording is carried out in the position immediately preceding the initial recording position. After that, an entry is made in the next (right) column.

By implementing such column scrolling interleaving as described above, it can be prevented that a plurality of code bits corresponding to a plurality of variable nodes connected to the same check node constitute a single 160AM symbol (included in the same symbol).

relative to GORS codes of all coding rates, the length of M code of which is 64,800, as proposed in the ОМВ-5.2 standard, and as a result, it is possible to improve the quality during decoding in the communication path that provides erasure.

Fig. 23 illustrates the number of memory columns 31 required for interleaving the scrolling of the columns and the address of the start position of the record for each modulation method with respect to GORS codes of eleven different coding rates with a code length M equal to 64,800 as proposed by the OMV-5.2 standard.

As a replacement method for the replacement process in the demultiplexer 25 (Fig. 8), one of the first to third replacement methods according to Fig. 16, and in addition, as the modulation method is adopted by ORBK, the number of t bits of one symbol is equal to 2 bits and the multiplier Yur is equal to 1.

In this case, according to Fig. 23, memory 31 has two columns to store 2 x 1 (- tb) bits in the row direction and stores 64,800/(2 x 1) bits in the column direction. Then, the write start position for the first of the two memory columns 31 is set to the position whose address is 0, and the write start position for the second column is set to the position whose address is 2.

Next, when the fourth replacement method of Fig. 8 is adopted as the replacement method for the replacement process in demultiplexer 25 (Fig. 17, and besides, as the modulation method is adopted by ORBZK, the number of t bits of one symbol is equal to 2 bits and the multiplier Yur is equal to 2.

In this case, according to Fig. 23, memory 31 has four columns to store 2 x 2 (5 trB) bits in the row direction and stores 64,800/(2 x 2) bits in the column direction. Then, the write start position for the first of the four memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 2, the write start position for the third column is set to the position whose address is 4, and the starting position of the record for the fourth column is set to the position whose address is 7.

Next, when one of the first to third replacement methods of Fig. 16, and in addition, as the modulation method is adopted by 16OAM, the number of t bits of one symbol is 4 bits and the multiplier B is 1.

In this case, according to Fig. 23, memory 31 has four columns to store 4 x 1 (5 trB) bits in the row direction and stores 64,800/(4 x 1) bits in the column direction. Then, the write start position for the first of the four memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 2, the write start position for the third column is set to the position whose address is 4, and the starting position of the record for the fourth column is set to the position whose address is 7.

Next, when the fourth replacement method of Fig. 8 is adopted as the replacement method for the replacement process in demultiplexer 25 (Fig. 17, and in addition, as the modulation method is adopted by 16OAM, the number of t bits of one symbol is 4 bits and the multiplier Br is 2.

In this case, according to Fig. 23, memory 31 has eight columns to store 4 x 2 (- tB) bits in the row direction and stores 64,800/(4 x 2) bits in the column direction. Then, the write start position for the first of the eight memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 0, the write start position for the third column is set to the position whose address is 2, the start position of the record for the fourth column is set to the position whose address is 4, the start position of the record for the fifth column is set to the position whose address is 4, the start position of the record for the sixth column is set to the position whose address is 5, the start position of the record for the seventh column is set to the position whose address is 7, and the start position of the record for the eighth column is set to the position whose address is 7.

Next, when one of the first to third replacement methods of Fig. 16, and in addition, as the modulation method is adopted by 64O0AM, the number of t bits of one symbol is equal to 6 bits and the multiplier B is equal to 1.

In this case, according to Fig. 23, memory 31 has six columns to store b x 1 (5 tB) bits in the row direction and stores 64,800/(6b x 1) bits in the column direction. Then, the write start position for the first of the six memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 2, the write start position for the third column is set to the position whose address is 5, the start position of the record for the fourth column is set to the position whose address is 9, the start position of the record for the fifth column is set to the position whose address is 10, and the start position of the record for the sixth column is set to the position whose address is 13 .

Next, when the fourth replacement method of Fig. 8 is adopted as the replacement method for the replacement process in demultiplexer 25 (Fig. 17, and in addition, as the modulation method is adopted by 640OAM, the number of t bits of one symbol is equal to 6 bits and the multiplier B is equal to 2.

In this case, according to Fig. 23, memory 31 has twelve columns to store 6 x 2 (- tb) bits in the row direction and stores 64,800/(6 x 2) bits in the column direction. Then, the write start position for the first of the twelve memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 0, the write start position for the third column is set to the position whose address is 2, the start position of the record for the fourth column is set to the position whose address is 2, the start position of the record for the fifth column is set to the position whose address is 3, the start position of the record for the sixth column is set to the position whose address is 4, the start position of the record for the seventh column is set to the position whose address is 4 the start position of the record for the eighth column is set to the position whose address is 5 the start position of the record for the ninth column is set to the position whose address is 5 the start position of the record for the tenth column is set to the position whose address is 7, initial the entry position for the eleventh column is set to the position whose address is 8, and the entry start position for the twelfth column is set to the position whose address is 9.

Next, when one of the first to third replacement methods of Fig. 16, and in addition, as the modulation method is adopted by 2560OAM, the number of t bits of one symbol is 8 bits and the multiplier B is 1.

In this case, according to Fig. 23, memory 31 has eight columns to store 8 x 1 (- tb) bits in the row direction and stores 64,800/(8 x 1) bits in the column direction. Then, the write start position for the first of the eight memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 0, the write start position for the third column is set to the position whose address is 2, the start position of the record for the fourth column is set to the position whose address is 4, the start position of the record for the fifth column is set to the position whose address is 4, the start position of the record for the sixth column is set to the position whose address is 5, the start position of the record for the seventh column is set to the position whose address is 7, and the start position of the record for the eighth column is set to the position whose address is 7.

Next, when the fourth replacement method of Fig. 8 is adopted as the replacement method for the replacement process in demultiplexer 25 (Fig. 17, and in addition, as the modulation method is 256O0AM, the number of t bits of one symbol is 8 bits and the multiplier B is 2.

In this case, according to Fig. 23, memory 31 has sixteen columns to store 8 x 2 (5 TB) bits in the row direction and stores 64,800/(8 x 2) bits in the column direction. Then, the write start position for the first of the sixteen memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 2, the write start position for the third column is set to the position whose address is 2, the start position of the record for the fourth column is set to the position whose address is 2, the start position of the record for the fifth column is set to the position whose address is 2, the start position of the record for the sixth column is set to the position whose address is 3, the start position of the record for the seventh column is set to the position whose address is 7 the start position of the record for the eighth column is set to the position whose address is 15 the start position of the record for the ninth column is set to the position whose address is 16 the start position of the record for the tenth column is set to the position whose address is 20, the beginning This record position for the eleventh column is set to the position whose address is 22 The start position of the record for the twelfth column is set to the position whose address is 22 The start position of the record for the thirteenth column is set to the position whose address is 27 The start position of the record for the fourteenth column is set to the position whose address is 27, the start position of the entry for the fifteenth column is set to the position whose address is 28, and the start position of the record for the sixteenth column is set to the position whose address is 32.

Next, when one of the first to third replacement methods of Fig. 16, and in addition, as the modulation method is adopted by 1024OAM, the number of t bits of one symbol is 10 bits and the multiplier B is 1.

In this case, according to Fig. 23, memory 31 has ten columns to store 10 x 1 (-tr) bits in the row direction and stores 64,800/(10 x 1) bits in the column direction. Then, the write start position for the first of the ten memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 3, the write start position for the third column is set to the position whose address is is 6, the start position of the record for the fourth column is set to the position whose address is 8, the start position of the record for the fifth column is set to the position whose address is 11, the start position of the record for the sixth column is set to the position whose address is 13, the start position of the record for the seventh column is set to the position whose address is equal to 15, the start position of the record for the eighth column is set to the position whose address is equal to 17, the start position of the record for the ninth column is set to the position whose address is equal to 18, and the start position entry for the tenth column is set to the position whose address is 20.

Next, when the fourth replacement method of Fig. 8 is adopted as the replacement method for the replacement process in demultiplexer 25 (Fig. 17, and in addition, as the modulation method is adopted by 1024OAM, the number of t bits of one symbol is 10 bits and the multiplier B is 2.

In this case, according to Fig. 23, the memory 31 has twenty columns to store 10 x 2 (5 TB) in the row direction and stores 64,800/10 x 2) bits in the column direction. Then, the write start position for the first of the twenty memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 1, the write start position for the third column is set to the position whose address is 3, the start position of the record for the fourth column is set to the position whose address is 4, the start position of the record for the fifth column is set to the position whose address is 5, the start position of the record for the sixth column is set to the position whose address is 6, the start position of the entry for the seventh column is set to the position whose address is b the start position of the record for the eighth column is set to the position whose address is 9 the start position of the record for the ninth column is set to the position whose address is 13 the start position of the record for the tenth column is set to the position whose address is 14, initial the record position for the eleventh column is set to the position whose address is 14, the start position of the record for the twelfth column is set to the position whose address is 16, the start position of the record for the thirteenth column is set to the position whose address is 21, the start position of the record for the fourteenth column is set to the position whose address is 21, the starting position of the entry for the fifteenth column is set to the position whose address is 23, the starting position of the record for the sixteenth column is set to the position whose address is 25, the starting position of the record for the seventeenth column is set to the position , whose address is 25, the starting position of the entry for the eighteenth column is set to the position whose address is 26, the starting position of the record for the nineteenth column is set to the position whose address is 28, and the starting position of the record for the twentieth column is set to the position, address what a dory takes 30.

Next, when one of the first to third replacement methods of Fig. 16, and in addition, as the modulation method is adopted by 4096OAM, the number of t bits of one symbol is equal to 12 bits and the multiplier B is equal to 1.

In this case, according to Fig. 23, memory 31 has twelve columns to store 12 x 1 (5 TB) bits in the row direction and stores 64,800/12 x 1) bits in the column direction. Then, the write start position for the first of the twelve memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 0, the write start position for the third column is set to the position whose address is 2, the start position of the record for the fourth column is set to the position whose address is 2, the start position of the record for the fifth column is set to the position whose address is 3, the start position of the record for the sixth column is set to the position whose address is 4, the start position of the record for the seventh column is set to the position whose address is 4 the start position of the record for the eighth column is set to the position whose address is 5 the start position of the record for the ninth column is set to the position whose address is 5 the start position of the record for the tenth column is set to the position whose address is 7, initial the entry position for the eleventh column is set to the position whose address is 8, and the entry start position for the twelfth column is set to the position whose address is 9.

Next, when the fourth replacement method of Fig. 8 is adopted as the replacement method for the replacement process in demultiplexer 25 (Fig. 17, and in addition, as the modulation method is adopted by 4096OAM, the number of t bits of one symbol is 12 bits and the multiplier B is 2.

In this case, according to Fig. 23, memory 31 has twenty-four columns to store 12 x 2 (- tb) bits in the row direction and stores 64,800/12 x 2) bits in the column direction. Then, the write start position for the first of the twenty-four memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 5, the write start position for the third column is set to the position, address which is equal to 8, the starting position of the record for the fourth column is set to the position whose address is equal to 8, the starting position of the record for the fifth column is set to the position whose address is equal to 8, the starting position of the record for the sixth column is set to the position whose address is equal to 8 , the start position of the record for the seventh column is set to the position whose address is 10, the start position of the record for the eighth column is set to the position whose address is 10, the start position of the record for the ninth column is set to the position whose address is 10, the start position entry for the tenth column is set to the position whose address is 12, the start position of the record for the eleventh column is set to the position whose address is 13, the start position of the record for the twelfth column is set to the position whose address is 16, the start position of the record for the thirteenth column is set to the position whose address is 17, the start position of the record for the fourteenth column is set to the position whose address is 19, the start position of the record for the fifteenth column is set to the position whose address is 21, the start position of the record for the sixteenth column is set to the position whose address is 22, the start position of the record for the seventeenth column is set to position whose address is 23 the starting position of the record for the eighteenth column is set to the position whose address is 26 the start position of the record for the nineteenth column is set to the position whose address is 37 the start position of the record for the twentieth column is set to the position addresswhich is 39, the starting position of the record for the twenty-first column is set to the position

whose address is 40, the start position of the record for the twenty-second column is set to the position whose address is 41, the start position of the record for the twenty-third column is set to the position whose address is 41, and the start position of the record for the twenty-fourth column is set to the position address which is equal to 41.

Fig. 24 illustrates the number of memory columns 31 required for interleaving the scrolling of the columns and the address of the starting position of the record for each modulation method relative to GORS codes of ten different coding rates with a code length M equal to 16,200 as proposed by the OMV-5.2 standard.

As a replacement method for the replacement process in the demultiplexer 25 (Fig. 8), one of the first to third replacement methods according to Fig. 16, in addition to the fact that the modulation method is adopted by ORBK, the number of t bits of one symbol is equal to 2 bits and the multiplier B is equal to 1.

In this case, according to Fig. 24, memory 31 has two columns to store 2 x 1 (- tb) bits in the row direction and stores 16,200/(2 x 1) bits in the column direction. Then, the write start position for the first of the two memory columns 31 is set to the position whose address is 0, and the write start position for the second column is set to the position whose address is 0.

Next, when the fourth replacement method of Fig. 8 is adopted as the replacement method for the replacement process in demultiplexer 25 (Fig. 17, and besides, as the modulation method is adopted by ORBZK, the number of t bits of one symbol is equal to 2 bits and the multiplier Yur is equal to 2.

In this case, according to Fig. 24, memory 31 has four columns to store 2 x 2 (5 trB) bits in the row direction and stores 16,200/(2 x 2) bits in the column direction. Then, the write start position for the first of the four memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 2, the write start position for the third column is set to the position whose address is 3, and the starting position of the entry for the fourth column is set to the position whose address is 3.

Next, when one of the first to third replacement methods of Fig. 16, and in addition, as the modulation method is adopted by 16O0AM, the number of t bits of one symbol is 4 bits and the multiplier B is 1.

In this case, according to Fig. 24, memory 31 has four columns to store 4 x 1 (5 trB) bits in the row direction and stores 16,200/(4 x 1) bits in the column direction. Then, the write start position for the first of the four memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 2, the write start position for the third column is set to the position whose address is 3, and the starting position of the entry for the fourth column is set to the position whose address is 3.

Next, when the fourth replacement method of Fig. 8 is adopted as the replacement method for the replacement process in demultiplexer 25 (Fig. 17, and in addition, as the modulation method is adopted by 16OAM, the number of t bits of one symbol is 4 bits and the multiplier Br is 2.

In this case, according to Fig. 24, memory 31 has eight columns to store 4 x 2 (- tB) bits in the row direction and stores 16,200/(4 x 2) bits in the column direction. Then, the write start position for the first of the eight memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 0, the write start position for the third column is set to the position whose address is 0, the start position of the record for the fourth column is set to the position whose address is 1, the start position of the record for the fifth column is set to the position whose address is 7, the start position of the record for the sixth column is set to the position whose address is 20, the entry start position for the seventh column is set to the position whose address is 20, and the entry start position for the eighth column is set to the position whose address is 21.

Next, when one of the first to third replacement methods of Fig. 16, and in addition, as the modulation method is adopted by 640AM, the number of t bits of one symbol is equal to 6 bits and the multiplier B is equal to 1.

In this case, according to Fig. 24, memory 31 has six columns to store b x 1 (5 TB) bits in the row direction and stores 16,200/(6 x 1) bits in the column direction. Then, the write start position for the first of the six memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 0, the write start position for the third column is set to the position whose address is 2, the start position of the entry for the fourth column is set to the position whose address is Z, the start position of the entry for the fifth column is set to the position whose address is 7, and the start position of the record for the sixth column is set to the position whose address is 7 .

Next, when the fourth replacement method of Fig. 8 is adopted as the replacement method for the replacement process in demultiplexer 25 (Fig. 17, and in addition, as the modulation method is adopted by 64O0AM, the number of t bits of one symbol is equal to 6 bits and the multiplier B is equal to 2.

In this case, according to Fig. 24, memory 31 has twelve columns to store 6 x 2 (- tb) bits in the row direction and stores 16,200/(6 x 2) bits in the column direction. Then, the write start position for the first of the twelve memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 0, the write start position for the third column is set to the position whose address is 0, the start position of the record for the fourth column is set to the position whose address is 2, the start position of the record for the fifth column is set to the position whose address is 2, the start position of the record for the sixth column is set to the position whose address is 2, the starting position of the record for the seventh column is set to the position whose address is equal to Z, the starting position of the record for the eighth column is set to the position whose address is equal to C, the starting position of the record for the ninth column is set to the position whose address is equal to the starting position of the record for the tenth column is set to the position whose address is b, initial the entry position for the eleventh column is set to the position whose address is 7, and the entry start position for the twelfth column is set to the position whose address is 7.

Next, when one of the first to third replacement methods of Fig. 16, and in addition, as the modulation method is adopted by 2560AM, the number of t bits of one symbol is 8 bits and the multiplier B is 1.

In this case, according to Fig. 24, memory 31 has eight columns to store 8 x 1 (- tb) bits in the row direction and stores 16,200/(8 x 1) bits in the column direction. Then, the write start position for the first of the eight memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 0, the write start position for the third column is set to the position whose address is 0, the start position of the record for the fourth column is set to the position whose address is 1, the start position of the record for the fifth column is set to the position whose address is 7, the start position of the record for the sixth column is set to the position whose address is 20, the entry start position for the seventh column is set to the position whose address is 20, and the entry start position for the eighth column is set to the position whose address is 21.

Next, when one of the first to third replacement methods of Fig. 16, and in addition, as the modulation method is adopted by 1024OAM, the number of t bits of one symbol is 10 bits and the multiplier B is 1.

In this case, according to Fig. 24, memory 31 has ten columns to store 10 x 1(-tr) bits in the row direction and stores 16,200/10 x 1) bits in the column direction. Then, the write start position for the first of the ten memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 1, the write start position for the third column is set to the position whose address is 2, the start position of the record for the fourth column is set to the position whose address is 2, the start position of the record for the fifth column is set to the position whose address is 3, the start position of the record for the sixth column is set to the position whose address is 3, the start position of the record for the seventh column is set to the position whose address is 4, the start position of the record for the eighth column is set to the position whose address is 4, the start position of the record for the ninth column is set to the position whose address is 5, and the start position entry for the tenth column is set to the position whose address is 7.

Next, when the fourth replacement method of Fig. 8 is adopted as the replacement method for the replacement process in demultiplexer 25 (Fig. 17, and in addition, as the modulation method is adopted by 1024OAM, the number of t bits of one symbol is 10 bits and the multiplier B is 2.

In this case, according to Fig. 24, memory 31 has twenty columns to store 10 x 2 (5 TB) bits in the row direction and stores 16,200/10 x 2) bits in the column direction. Then, the write start position for the first of the twenty memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 0, the write start position for the third column is set to the position whose address is 0, the start position of the record for the fourth column is set to the position whose address is 2, the start position of the record for the fifth column is set to the position whose address is 2, the start position of the record for the sixth column is set to the position whose address is 2, the start position of the record for the seventh column is set to the position whose address is 2 the start position of the record for the eighth column is set to the position whose address is 2 the start position of the record for the ninth column is set to the position whose address is 5 the start position of the record for the tenth column is set to the position whose address is 5, initial po the position of the record for the eleventh column is set to the position whose address is 5 the start position of the record for the twelfth column is set to the position whose address is 5 the start position of the record for the thirteenth column is set to the position whose address is 5 the start position of the record for the fourteenth column is set to the position whose address is 7 the starting position of the entry for the fifteenth column is set to the position whose address is 7 the starting position of the record for the sixteenth column is set to the position whose address is 7 the starting position of the record for the seventeenth column is set to the position , whose address is 7, the starting position of the entry for the eighteenth column is set to the position whose address is 8, the starting position of the record for the nineteenth column is set to the position whose address is 8, and the starting position of the record for the twentieth column is set to the position, address which is equal to 10.

Next, when one of the first to third replacement methods of Fig. 16, and in addition, as the modulation method is adopted by 4096OAM, the number of t bits of one symbol is equal to 12 bits and the multiplier B is equal to 1.

In this case, according to Fig. 24, memory 31 has twelve columns to store 12 x 1 (5 TB) bits in the row direction and stores 16,200/(12 x 1) bits in the column direction. Then, the write start position for the first of the twenty-four memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 0, the write start position for the third column is set to the position, address which is 0, the start position of the record for the fourth column is set to the position whose address is 2, the start position of the record for the fifth column is set to the position whose address is 2, the start position of the record for the sixth column is set to the position whose address is 2 , the start position of the record for the seventh column is set to the position whose address is 3, the start position of the record for the eighth column is set to the position whose address is 3, the start position of the record for the ninth column is set to the position whose address is 3, the start position entry for the tenth column is set to the position whose address is 6, beginning the starting position of the record for the eleventh column is set to the position whose address is 7, and the start position of the record for the twelfth column is set to the position whose address is 7.

Next, when the fourth replacement method of Fig. 8 is adopted as the replacement method for the replacement process in demultiplexer 25 (Fig. 17, and in addition, as the modulation method is adopted by 4096OAM, the number of t bits of one symbol is 12 bits and the multiplier B is 2.

In this case, according to Fig. 24, memory 31 has twenty-four columns to store 12 x 2 (5 TB) bits in the row direction and stores 16,200/12 x 2) bits in the column direction. Then, the write start position for the first of the twenty-four memory columns 31 is set to the position whose address is 0, the write start position for the second column is set to the position whose address is 0, the write start position for the third column is set to the position, address which is 0, the start position of the record for the fourth column is set to the position whose address is 0, the start position of the record for the fifth column is set to the position whose address is 0, the start position of the record for the sixth column is set to the position whose address is 0 , the start position of the record for the seventh column is set to the position whose address is 0, the start position of the record for the eighth column is set to the position whose address is 1, the start position of the record for the ninth column is set to the position whose address is 1, the start position entry for the tenth column is set to a position whose address is 1, beginning the starting position of the record for the eleventh column is set to the position whose address is 2 the start position of the record for the twelfth column is set to the position whose address is 2 the start position of the record for the thirteenth column is set to the position whose address is 2 the start position of the record for the fourteenth column is set to the position whose address is 3, the starting position of the entry for the fifteenth column is set to the position whose address is 7, the starting position of the record for the sixteenth column is set to the position whose address is 9, the starting position of the record for the seventeenth column is set to position, the address of which is 9, the starting position of the record for the eighteenth column is set to the position, the address of which is 9, the starting position of the record for the nineteenth column is set to the position, the address of which is 10, the starting position of the record for the twentieth column is set to the position, address which is equal to is 10, the start position of the record for the twenty-first column is set to the position whose address is 10, the start position of the record for the twenty-second column is set to the position whose address is 10, the start position of the record for the twenty-third column is set to the position whose address is 10 , and the starting position of the entry for the twenty-fourth column is set to the position whose address is 11.

Now, with reference to the block diagram of the algorithm in Fig. 25, the transmission process performed by the transmission device 11 of FIG. 8.

The IOR encoder section 21 waits for object data to be supplied to it, and at step 5101 encodes this object data into GORS codes and supplies these GORS codes to bit interleaver 22. Processing then proceeds to step 5102.

At step 5102, the bit interleaver 22 carries out bit interleaving for the AND ORS codes from the GORS coding section 21 and supplies the GORS codes after interleaving to the display section 26. Processing then proceeds to step 5103 .

Specifically, at step 5102, the parity interleaver 23 in the bit interleaver 22 performs parity interleaving for the GORS codes from the GORS coding section 21 and feeds these GORS codes after parity interleaving to the column scroll interleaver 24.

Column scroll interleaver 24 performs column scroll interleaving for GORS codes from parity interleaver 23, and then demultiplexer 25 performs the replacement process for the code

GORS after interleaving the scrolling of columns by interleaving 24 scrolling columns.

Then, GORS codes after the replacement process are fed from the demultiplexer 25 to the display section 26.

In step 5103, the display section 26 maps t code bits of the GORS codes from the demultiplexer 25 into symbols represented by signal dots determined by the modulation method for orthogonal modulation, carried out by the orthogonal modulation section 27, and supplies the displayed symbol to the orthogonal modulation section 27. Processing then proceeds to step 5104 .

At step 5104, the orthogonal modulation section 27 carries out orthogonal modulation of the carrier according to the signal points from the display section 26. Processing then proceeds to step 5105, in which the modulated signal obtained as a result of orthogonal modulation is transmitted, after which processing ends.

It should be noted that the transmission process in Fig. 25 is carried out on the highway repeatedly.

By implementing parity interleaving and column scrolling interleaving as described above, resistance to erasure or packet errors can be improved when multiple code bits in GORS codes are transmitted as a single symbol.

Here, although the parity interleaver 23, which is a parity interleaving block, and the column scroll interleaver 24, which is a column scroll interleaving block, in FIG. 8 are made separately from each other for ease of description, the parity interleaver 23 and the column scroll interleaver 24 may otherwise be implemented as a single unit.

In particular, both parity interleaving and column scrolling interleaving can be performed by writing and reading code bits to and from memory and can be represented by a matrix to convert the addresses (write addresses) to which the code bits are to be written to addresses (reading addresses) from which code bits should be read.

Accordingly, if the matrix obtained by multiplying the matrix representing the parity interleaving and the matrix representing the column scrolling interleaving is found in advance, then if this matrix is used to convert the code bits, then the result can be obtained in which the parity interleaving is performed, and then GORS codes after parity interleaving are interleaved with column scrolling.

Next, in addition to the parity interleaver 23 and the column scroll interleaver 24, a demultiplexer 25 can be combined.

In particular, the replacement process carried out by the demultiplexer 25 can be represented by a matrix for converting the write address in the memory 31 for storing the GORS code to the read address.

Accordingly, if the matrix obtained by multiplying a matrix representing the parity interleaving, another matrix representing the column scrolling interleaving, and another matrix representing the replacement process is found in advance, then the parity interleaving, the column scrolling interleaving, and the replacement process can be performed jointly by using the found matrix.

It should be noted that only one of parity interleaving and column scrolling interleaving can be performed.

Now, with reference to FIG. 26 - 28, the simulation performed with respect to the transmission device 11 of FIG. 8 to measure the frequency of occurrence of errors (the frequency of occurrence of erroneous bits).

This simulation was carried out using a jittered communication path with a useful to unwanted signal ratio of 0 dB.

Fig. 26 shows the model of the communication path adopted in the simulation.

In particular, part A of Fig. 26 shows the jitter pattern adopted in the simulation.

However, part B of Fig. 26 shows a model of a link path having jitter represented by the model of part A of FIG. 26.

It should be noted that in part B of Fig. 26 H represents the vibration model in part A of Fig. 26. Next, in part B of Fig. 26 M represents the interference between the carriers (ICI), and during modeling, the expected value of EGM-| of power was approximated by additive white Gaussian noise (AUMOM).

Fig. 27 and 28 illustrate the relationship between the frequency of occurrence of errors obtained during simulation and the Doppler frequency of jitter.

It should be noted that Fig. 27 illustrates the relationship between the error rate and their Doppler frequency when the modulation method is 16OAM and the coding rate (r) is (3/4) and, in addition, the replacement method is the first replacement method. At the same time, Fig. 28 illustrates the relationship between the error rate and the Doppler frequency when the modulation method is 640OAM and the coding rate (g) is (5/6) and, furthermore, the replacement method is the first replacement method.

Next, in Fig. 27 and 28, the curve drawn by the bold line represents the relationship between the error rate and the Doppler frequency y4 when all of the parity interleaving, the scrolling interleaving and the replacement process were performed, and the curve drawn by the thin line represents the relationship between the error rate and the Doppler frequency iz when only the replacement process was performed from among parity interleaving, column scrolling interleaving, and replacement process.

In both Figs. 27 and 28, it can be seen that the error rate is improved (decreased) when all of the parity interleaving, column scrolling interleaving, and the replacement process are performed, rather than when only the replacement process is performed.

Fig. 29 is a block diagram showing an example configuration of the receiving device 12 of FIG. 7.

In Fig. 29, the receiving device 12 is a data processing device for receiving a modulated signal from the transmitting device 11 (Fig. 7) and contains an orthogonal demodulation section 51, a reverse reflection section 52; deinterleaver 53 and decoding section 56 GG ORS.

The orthogonal demodulation section 51 receives the modulated signal from the transmission device 11 and carries out orthogonal demodulation, and then supplies the symbols obtained as a result of the orthogonal demodulation (values on the and and Y axes) to the reverse display section 52.

The reverse mapping section 52 performs reverse mapping by converting the symbols from the orthogonal demodulation section 51 into code bits of the GORS code and feeds these code bits to the deinterleaver 53.

The deinterleaver 53 contains a multiplexer (MOX) 54 and a column scrolling deinterleaver 55 and deinterleaves the symbols from the bits from the reverse mapping section 52.

In particular, the multiplexer 54 performs a reverse replacement process (the reverse process of the replacement process), which corresponds to the replacement process performed by the demultiplexer 25 of FIG. 8, for GORS codes from the reverse mapping section 52, that is, the process of reverse replacement by returning the positions of the code digits (bits) of the GORS codes replaced by the replacement process to the original positions. The multiplexer 54 then feeds the GORS code obtained as a result of the reverse replacement process to the deinterleaver 55 of scrolling columns.

Column scrolling deinterleaver 55 performs column scrolling deinterleaving (a process inverse to column scrolling interleaving) corresponding to column scrolling interleaving as a permutation process performed by column scrolling interleaver 24 of FIG. 8, i.e., for example, column scrolling deinterleaving as a reverse permutation process by returning the placement of code bits of a GORS code having a placement changed by column scrolling interleaving as a process of permutation to the original placement, for the code

GORS from multiplexer 54.

In particular, the column scrolling deinterleaver 55 deinterleaves the column scrolling by writing the code bits of the GORS code into the memory and reading the recorded code bits from the memory for deinterleaving, while the memory is made similarly to the memory 31 shown in

Fig. 22, etc.

It should be noted that in the column scrolling deinterleaver 55, the recording of code bits is carried out in the direction of the memory line for deinterleaving using read addresses when reading codes from memory 31 as write addresses. At the same time, the reading of the code bits is carried out in the direction of the memory column for deinterleaving using write addresses when writing the code bits into the memory 31 as read addresses.

GORS codes obtained as a result of column scrolling deinterleaving are fed from the column scrolling deinterleaver 55 to the section 56 of decoding I ORS.

Here, although the GORS code supplied from the reverse mapping section 52 to the deinterleaver 53 is obtained by parity interleaving, column scroll interleaving, and the replacement process performed in this order, the deinterleaver 53 only performs the reverse replacement process corresponding to the replacement process and the column scroll deinterlace, which corresponds to interleaving the scrolling of the columns. Accordingly, parity deinterleaving, which corresponds to parity interleaving (a process inverse to parity interleaving), that is, parity deinterleaving, which returns the placement of the code bits of GORS codes, the placement of which has been changed by parity interleaving, to the original placement, is not carried out.

Accordingly, the GORS code, for which the process of deinterlacing and deinterleaving the column scrolling is performed, but the parity deinterleaving is not performed, is fed from the (column scrolling deinterleaver 55) of the deinterleaver 53 to the GORS decoding section 56.

The GORS decoding section 56 decodes the H(ORS of the TORS code from the deinterleaver 53 using a transformed parity check matrix obtained by performing at least a column swap corresponding to the parity interleaving for the parity check matrix H used for GORS encoding by the GORS encoding section 21 Fig. 8, and displays the data obtained as a result of decoding AND ORS as a result of decoding object data.

Fig. 30 is a block diagram of an algorithm illustrating the receiving process performed by the receiving device 12 of FIG. 29.

The orthogonal demodulation section 51 receives the modulated signal from the transmission device 11 in step 5111. Then, processing proceeds to step 5112, in which the orthogonal modulation section 51 performs orthogonal demodulation of the modulated signal. The orthogonal demodulation section 51 supplies the signal dots obtained as a result of the orthogonal demodulation to the reverse mapping section 52, after which the processing proceeds from step 5112 to step 5113.

At step 5113, the demapping section 52 performs demapping by converting the symbols from the orthogonal demodulation section 51 into symbols and feeds the code bits to the deinterleaver 53, after which processing proceeds to step 5114.

At step 5114, the deinterleaver 53 deinterleaves the code bits of the GORS code from the reverse mapping section 52, after which processing proceeds to step 5115.

In particular, at step 5114, the multiplexer 54 in the deinterleaver 53 performs a deinterlacing process for the GORS code from the reverse mapping section 52 and supplies the GORS code obtained as a result of the deinterlacing process to the scrolling deinterleaver 55.

Column scrolling deinterleaver 55 performs column scrolling deinterleaving for the GORS code from the multiplexer 54 and feeds the GORS code obtained as a result of column scrolling deinterleaving to the section 56 of decoding AND ORS.

At step 5115, the GORS decoding section 56 performs GORS decoding of the GORS code from the column scrolling deinterleaver 55 using a transformed parity check matrix obtained by performing at least a column swap corresponding to the parity interleaving for the parity check matrix H used for GORS encoding by the encoding section 21 GORS by

Fig. 8, and outputs the data obtained by HORS decoding as a result of object data decoding. After that, the processing ends.

It should be noted that the reception process according to Fig. 30 is carried out repeatedly.

In addition, in Fig. 29, the multiplexer 54 for performing the reverse replacement process and the column scrolling deinterleaver for performing column scrolling deinterleaving are made separately from each other for ease of description, similarly to the case of Fig.8. However, the multiplexer 54 and the column scrolling deinterleaver 55 can be implemented together with each other.

Further, when the transmitting device 11 of Fig.8 does not interleave the scrolling columns, there is no need to provide the deinterleaving column scrolling 55 in the receiving device 12 of Fig. 29.

Now the GORS decoding performed by section 56 of the GG ORS decoding in Fig. 29 is described below.

Section 56 decoding of the I ORS according to Fig. 29 performs GORS decoding of a GORS code that has been reverse swapped and column scroll deinterleaved, but not parity deinterleaved, from column scroll deinterleaver 55 as described above using the transformed parity check matrix obtained by performing at least column swapping corresponding to parity interleaving for the parity check matrix H used for coding the I ODS by section 21 of the HH ODS coding in Fig. 8.

Here, GORS decoding, which can suppress the operating frequency in a sufficiently feasible range while reducing circuit sizes by performing GORS decoding using a transformed parity check matrix, has been proposed previously (see, for example, the patent application

of Japan Mo 2004 - 343170).

Thus, the previously proposed GORS decoding using a transformed parity check matrix is described first with reference to FIG. 31 - 34.

Fig. 31 shows an example of a GORS code parity check matrix H, the length M of which code is 90, and the coding speed is 2/3.

It should be noted that in Fig. 31 zero is represented by a dot (.) (this is analogously applicable to Fig. 32 and 33, which are described later).

In the matrix H of parity checks in Fig. 31 parity matrix has a step structure.

Fig. 32 illustrates the parity check matrix H' obtained by applying row replacement by expression (9) and column replacement by expression (9) to the parity check matrix H of FIG. 31.

Replacement of rows: (65 1 - 1) th row - (5145 4.1) th row (8)

Replacement of columns: (bh x y y - 61)-th column -" (5y x x -- 61)-th column (9)

However, in expressions (8) and (9), 5, y, х, and y are integers in the range х5«5, 0хи1«6 О0«х«BbBibsk ev, respectively.

According to the replacement of lines by expression (8), the replacement is carried out in such a way that the 1st, 7th, 13th, 19th and 25th lines, each of the numbers of which indicates the remainder of the division of 1 by 6, are replaced on the 1st, 2nd, 3rd, 4th and 5th lines, and the 2nd, 8th, 14th, 20th and 26th lines, each of which numbers indicates the remainder from dividing 2 by 6 is replaced by the 6th, 7th, 8th, 9th and 10th lines.

On the other hand, according to the replacement of columns by expression (9), the replacement is carried out for the 61st and subsequent columns (parity matrix), so that the 61st, 67th, 73rd, 79th, and 85th columns , each of whose numbers indicates the remainder from dividing 1 by 6, are replaced by the 61st, 62nd, 63rd, 64th and 65th columns, and the 62nd, 68th, 74th, 80 The -th and 86th columns, each of whose numbers indicates the remainder from the division of 2 by 6, are replaced by the 66th, 67th, 68th, 69th, and 70th columns.

The matrix obtained by permuting the rows and columns for the parity check matrix H in Fig. 31, there is a parity check matrix H' in Fig. 32.

Here, even if the rows of the parity check matrix H are replaced, this does not affect the placement of the code bits of the GORS code.

At the same time, the replacement of columns according to expression (12) corresponds to parity interleaving, when the length K of the information, the block number P of the columns of the cyclic structure, and the divisor 4 (- M/Р) of the length M of the parity (here, 30) in the parity interleaving with interleaving (К « from дх «ж у иж 1)-th code digit to the position (К ж Ру ж x)-th code digit are set, respectively, to 60, 5 and 6.

If the parity check matrix H' (hereinafter referred to as the substituted parity check matrix) according to Fig. 32 is multiplied by the result of its substitution according to expression (9) for the GORS code of the parity check matrix H (hereinafter referred to, respectively, as the original parity check matrix) of Fig. 31, then the zero vector is output. In particular, when the row vector obtained by applying column substitution according to expression (9) for the row vector c as the GORS code (codeword) of the original parity check matrix H is represented by c, since Ne" becomes a zero vector based on the characteristic of the parity check matrix , naturally, and H'c" becomes a zero vector.

It follows from the above that the transformed matrix H' of the parity check in Fig. 32 becomes the parity check matrix of the code with GORS, obtained by replacing the columns according to expression (9) for the code with GORS of the original parity check matrix H.

Accordingly, by replacing the columns according to expression (9) for the GORS code of the original parity check matrix H, decoding (and ORS decoding) of the GORS code after replacing the columns using the parity check matrix H' in Fig. 32, and then performing a reverse substitution to replace the columns by expression (9) for the decoding result, a decoding result similar to that obtained when the GORS code of the original parity check matrix H is decoded by the parity check matrix H can be obtained.

Fig. 33 shows the transformed matrix H' of the parity check of FIG. 32, in which the space between blocks of 5 x 5 matrices is provided.

In Fig. 33, the transformed matrix H' of the parity check is represented by a combination of block matrices of 5 x 5 elements, another matrix (hereafter referred to as a quasi-block matrix) corresponding to a block matrix in which the element or elements with the value 1 are replaced by the element or elements with the value 0, another matrix (hereafter referred to as the shifted matrix respectively) corresponding to the block matrix or quasi-block matrix after it is cyclically shifted (cyclic shift), another matrix (hereafter referred to respectively as the sum matrix) of two or more block matrices, quasi-block matrices and a shifted matrix, and a null matrix of 5 x 5 elements.

It can be assumed that the transformed matrix H' of the parity check in Fig. 33 is composed of a block matrix, a quasi-block matrix, a shifted matrix, a total matrix and a zero matrix with 5 x 5 elements.

For this purpose, the matrices of 5 x 5 elements, which make up the transformed matrix H' of the parity check, are referred to hereafter as component matrices.

To decode the GORS code represented by a parity check matrix, represented by a matrix of P x P components, it is possible to use an architecture that performs a mathematical operation of the verification node and a mathematical operation of the variable node simultaneously for P verification nodes and P variable nodes.

Fig. 34 is a block diagram showing an example configuration of a decoding device performing such decoding as just described.

In particular, Fig. 34 shows an example of the configuration of a coding device that decodes codes

GORS of the output matrix H of the parity check in Fig. 31 using the transformed matrix H' of the parity check in Fig. 33, obtained by performing at least the replacement of columns according to expression (9).

The decoding device of Fig. 34 contains a memory device 300 of data edges, containing six registers 300: - Z006 РИО, selector 301 for selecting registers 3001 - 3006 РИРО, section 302 calculation of the verification node, two circuits 303 and 308 cyclic shift, storage device 304 data edges containing eighteen registers 3041 - 3048 RIRO, selector 305 for selecting registers 304: -

Z04v RIBO, memory 306 of the received data, section 307 calculation of the variable node, circuit 308 cyclic shift, section 309 calculation of the decoded word, section 310 permutation of the received data and section 311 reorganization of the decoded data.

First, the method of saving data in memory devices 300 and 304 of data edges is described.

The storage device 300 of data edges contains six registers 3001 - 3006 RIBO, the number of which is equal to the fraction of dividing the number of 30 rows of the transformed matrix H' of the parity check in Fig. 33 by the number of 5 lines of the component matrix. Each of the registers З00у RIBO (in :- 1, 2,..., 6) has a plurality of levels of storage areas, so that messages corresponding to five edges, the number of which is equal to the number of rows and the number of columns of the component matrices, can be read from these storage areas of each level or write to them at the same time. Next, the number of levels of storage areas of each register

Z00y RIRO is nine, which is the maximum number of units (Hamming weight) in the row direction of the transformed parity check matrix of Fig. 33.

In the register 300; RIRO data (message m; from the nodes of the variable) corresponding to the positions with the value 1 in the first to fifth rows of the transformed matrix H' of the parity check in Fig. 33, are stored in a closed form in the horizontal direction in separate lines (in the form where 0 is ignored). In particular, if the element in the |-th row of the i-th column is represented as (|, i), then in the storage areas in the first step of the register 300: РИРО the data corresponding to the positions with the value 1 of the block matrix with x 5 elements from (1 , 1) to (5, 5) transformed matrix H' of the parity check. In the storage areas of the second stage, the data corresponding to the positions with the value 1 of the shifted matrix from (1, 21) to

(5, 25) of the transformed matrix H' of the parity check (the shifted matrix is obtained by cyclic shift of the block matrix with 5 x 5 elements by three to the right). In addition, in storage areas from the third to the eighth level, the data is stored in a bound relationship with the transformed matrix H' of the parity check. Next, in the storage areas in the ninth step, the data corresponding to the positions of the values of the shifted matrix from (1, 86) to (5, 90) of the transformed matrix H' of the parity check (of the shifted matrix obtained by replacing the value 1 in the first row of the block a matrix of 5 x 5 elements with a value of 0 and then a cyclic shift of this block matrix after replacing it by one to the left).

The data corresponding to the positions of the value 1 from the sixth to tenth rows of the transformed matrix H' of the parity check in Fig. 33. In particular, in the storage area in the first step of the RIBO register 3002, the data corresponding to the positions of the value 1 of the first shifted matrix, which forms the total matrix from (6, 1) to (10, 5) of the transformed matrix H' of the parity check (total matrix, which is the sum of the first shifted matrix, obtained by cyclically shifting the block matrix of 5x5 elements by one to the right, and the second shifted matrix, obtained by cyclically shifting the block matrix of 5x5 elements by two to the right). Next, in the storage area in the second step, the data corresponding to the positions of the value 1 of the second shifted matrix is stored, which forms the total matrix from (6, 1) to (10, 5) of the transformed matrix H' of the parity check.

In particular, with respect to the component matrix, the weight of which is 2 or more, when this component matrix is represented as the sum of the set of the number of the block matrix with Р x Р elements with weight 1, the quasi-block matrix corresponding to the block matrix, one or more elements of which with the value 1 are replaced by 0, and of the shifted matrix obtained by cyclic shifting of the block matrix or quasi-block matrix, the data corresponding to the positions of the value 1 of the block matrix, quasi-block matrix, or shifted matrix whose weight is 1 (messages corresponding to the edges belonging to the block matrix, quasi-block matrix or shifted matrix), are stored in the same address (the same register RIBO from the number of registers 300: - ЗО0в РИО).

In addition, in the storage areas in the third - ninth steps, the data is stored in a bound ratio with the transformed matrix H' of the parity check.

In addition, registers 3005 - З006 РИРО store data in a related relationship with the transformed matrix H' of the parity check.

The memory device 304 of data edges contains eighteen registers 304: - Z041v RIBO, the number of which is equal to the fraction of dividing the number of 90 columns of the transformed matrix H' of the parity check by the number of 5 columns of the component matrix. Each of the storage devices Z04x (x - 1, 2,..., 18) contains a set of steps of storage areas and messages corresponding to five edges, the number of which is equal to the number of rows and the number of columns of the transformed matrix H' parity checks can be read from or written to these storage areas of each tier at the same time.

In the RIBO register 3041, the data corresponding to the positions with the value 1 in the first to fifth columns of the transformed matrix H' of the parity check in Fig. 33, (messages ц; from verification nodes) are stored in a closed form in the vertical direction in separate columns (in the form where 0 is ignored). In particular, in the storage areas in the first step of the register 304; RIBO stores data corresponding to positions with a value of 1 of the block matrix with 5 x 5 elements from (1, 1) to (5, 5) of the transformed matrix H' of the parity check. In the storage areas of the second stage, the data corresponding to the value positions of the first shifted matrix are stored, which form the total matrix from (6, 1) to (10, 5) of the vertical matrix H' of the parity check (the total matrix, which is the sum of the first shifted matrix, obtained by cyclic shift of a block matrix with 5 x 5 elements by one to the right, and another shifted matrix obtained by cyclic shift of a block matrix with 5 x 5 elements by two to the right). Next, in the storage areas in the third step, the data corresponding to the positions with values of 1 of the second shifted matrix is stored, which forms the total matrix from (6, 1) to (10, 5) of the vertical matrix H' of the parity check.

In particular, with respect to the component matrix, the weight of which is 2 or more, when this component matrix is represented as the sum of the set of the number of the block matrix with Р x Р elements with weight 1, the quasi-block matrix corresponding to the block matrix, one or more elements of which with the value 1 are replaced by 0, and of the shifted matrix obtained by cyclic shifting of the block matrix or quasi-block matrix, the data corresponding to the positions of the value 1 of the block matrix, quasi-block matrix, or shifted matrix whose weight is 1 (messages corresponding to the edges belonging to the block matrix, quasi-block matrix or shifted matrix), are stored in the same address (the same RIBO register from the number of registers 304: - З04в RIEO).

In addition, with respect to the storage areas in the fourth and fifth steps, the data is stored in a bound relationship with the transformed parity check matrix H'. The number of steps of the storage areas of the register 304: RIEO is 5, which is the maximum number for the number of units (Hamming weight) in the row direction in the first - fifth columns of the transformed matrix H' of the parity check.

In addition, RIBO registers 3042 and 3043 store data in a bound relationship with the transformed matrix H!' parity check similarly, and each length (number of steps) of registers 3042 and 3043 is equal to 5. In addition, registers 3044 - 30412 PIRO store data in a related relationship with the transformed parity check matrix H' similarly, and each length of registers 3044 - 30442 RIBO is 3. In addition, RIBO registers 30413 - 30418 store data in a bound relationship with the transformed parity check matrix H' similarly, and each length of RIBO registers 3044 - 30442 is 2.

Now the operation of the decoding device according to Fig. 34.

The memory device 300 of the edge data contains six registers 3001 - ZOOve RIRO, and the RIRO registers in which the data should be stored are selected from the number of registers 300: - Z00e RIBO according to the information (matrix data) 0312, which represents which row of the transformed matrix H' of the parity check belong to five messages 0311, submitted from the circuit 308 of the cyclic shift at the previous stage. Then these five 0311 messages are stored together and one by one in selected RIO registers. Next, when the data is to be read, the memory device 300 of the data edges reads five messages 03001 one by one from the register 3001 RIRO and submits these five messages YZ300 to the selector 301 at the next step. After reading the messages from the register 3001 RIRO, the storage device 3001 reads the messages one by one also from the registers 300" - ZO0e RIRO and submits the read messages to the selector 301.

Selector 301 selects five messages from that register RIRO from the number of registers 300: - ZOOv, from which data is currently being read in accordance with signal 0301 and submits five messages as messages rzog2 to section 302 of the calculations of the verification node.

Section 302 of the calculations of the verification node contains five calculators 3021 - 3025 of the verification node and performs the mathematical operation of the verification node according to the expression (7) using the message p' 302 (03021 - 3025) (message y; according to the expression (7)) , obtained as a result of a mathematical operation, into the chain 303 cyclic shift.

The cyclic shift chain 303 cyclically shifts five messages 0303: - 03035, found by the section 302 of the calculation of the verification node based on the information (matrix data) U30O5 regarding the number of output block matrices by which the corresponding edges in the transformed parity check matrix H' are cyclically shifted , and submits the result of this cyclic shift as a message 0304 to the edge data storage device 304.

The memory device 304 of these edges contains 18 registers 3041 - ЗО041в RIBO.

The storage device 304 selects the RIEO register in which the data must be stored from among the registers 3041 to 30418 according to the information 0305 regarding which row of the converted parity check matrix H' belong to the five messages 0304 provided from the chain 303 cyclic shift in the previous stage, and jointly stores these five messages in turn in the selected RIBO register. On the other hand, when the data is to be read, the memory device 304 data edges reads five messages 03061 one by one from the register 304: RIBO and submits the message 0306; in selector 305 at the next step. After reading data from register 304; The RIRO memory device 304 reads the messages one by one also from the registers 3042 - Z304-:v and submits these messages to the selector 305.

Selector 305 selects five messages from the RIPO register, from which data is currently being read, from the number of RIBO registers 3041 - 3048 according to the selected signal Y307 and feeds the selected messages as message 0308 to the variable node calculation section 307 and the decoded word calculation section 309 .

On the other hand, the section 310 permutation of the received data carries out the replacement of columns according to the expression (9) for the permutation of the code 0313 GORS received through the communication path, and provides the rearranged code 0313 AND ORS as the received data 0314 in the memory 306 of the received data. The memory 306 of the received data calculates and stores the logarithmic ratio of the likelihood (II K) of the reception from the received data 0314, submitted to it from the section 310 of the permutation of the received data, and collects and submits every five of the GCs of the reception as the value of O 309 of the reception to the section 307 computing the variable node and section 309 computing the decoded word.

The variable node calculation section 307 contains the variable node calculators 3071 - 3075 and performs the mathematical operation of the variable node according to expression (1) with the help of messages YZ308 (308: - 3085) (messages and; according to expression (1)) submitted to it through the selector 305, and five reception values 0309 (values of the reception neck according to expression (1)), applied to it from the received data memory 306. Then, section 307 of calculating the variable node submits message Y310 (03105 - YZ105) (message mi according to the expression (1)), obtained as a result of the mathematical operation, to the circuit 308 of the cyclic shift.

The cyclic shift chain 308 cyclically shifts the messages 03101 to 03105 calculated by the variable node calculation section 307 based on the information about which number of output block matrices the corresponding edge is cyclically shifted in the transformed parity check matrix H', and outputs the result of the cyclic shift as message 0311 300 data edges in the memory device.

Due to the implementation of the sequence of operations described above, decoding can be carried out in one cycle of the GORS code. In the decoding device of Fig. 34, after the GORS code is decoded a predetermined number of times, the final decoding result is determined by the decoded word calculation section 309 and the decoded data permutation section 311, and then output.

Specifically, the decoded word calculation section 309 includes five calculators 309: - 3095 and acts as the final step in a plurality of decoding cycles to calculate the decoding result (decoded word) according to expression (5) using five messages 2308 (03081 - OZO85) (messages and; according to expression (5)), deduced from the selector 305, and five values 0309 of reception (values of points of reception according to expression (5)), deduced from memory 305 of received data. Then, the decoded word calculation section 309 supplies the decoded data 0315 obtained as a result of the decoded data permutation calculation section 311.

Section 311 of permuting the decoded data performs a reverse substitution before replacing the columns according to the expression (12) for the decoded data 0315 supplied to it from the section 309 of calculating the decoded word, to rearrange the order of the decoded data 0315 as a result of Y316 decoding.

As described above, by applying one or both of row swap and column swap to a parity check matrix (the original parity check matrix) to transform this parity check matrix into a parity check matrix (the transformed parity check matrix) that can be represented by a combination of a block matrix of 3 Р x Р elements, a quasi-block matrix corresponding to a block matrix whose elements with the value 1 are replaced by an element or elements with a value 0, a shifted matrix corresponding to a block matrix or a quasi-block matrix after it is cyclically shifted, the sum matrix of two or more of a block matrix, a quasi-block matrix, and a shifted matrix, and a zero matrix of Р x Р elements, as described above, it becomes possible to adapt to the decoding of the GORS code an architecture that performs the mathematical operation of the verification node and the mathematical operation of the variable node at the same time for P nodes of the check and P nodes of the variable. Therefore, due to the implementation of the mathematical operation of the node simultaneously for P nodes, it is possible to suppress the operating frequency in the feasible range for the decoding of the I ORS code.

Section 56 decoding GORS, consisting of the receiving device 12 in Fig. 29, performs the mathematical operation of the verification node and the mathematical operation of the variable node at the same time for P verification nodes and P variable nodes to perform GORS decoding similarly to the decoding device by

Fig. 34.

In particular, let us now assume, to simplify the description, that the parity check matrix of the GORS code, which is derived from the section 21 of the IOR coding, consisting of the transmission device 11 of Fig. 8 is, for example, a parity check matrix H, in which the parity matrix has the step structure shown in FIG. 31. In this case, the parity interleaver 23 of the transmission device performs parity interleaving to interleave the (K x x x x x x 1)-th code bit into the position of the (K - Ru x x x 1)-th code bit with the information length set to 60, with the block number P of the columns of the cyclic structure set to 5, and with the divisor 4 (- M/P) of the parity length M equal to 6.

Since this parity interleaving corresponds to the replacement of columns according to expression (9), the decoding section 56 of AND ORS does not perform the replacement of columns according to expression (9).

Therefore, in the receiving device 12 of Fig. 29, the GORS code for which parity deinterleaving has not been performed, that is, the GORS code in the state in which the columns are replaced by expression (9), is fed from the column scrolling deinterleaver 55 to the GORS decoding section 56, as described above. The GORS decoding section 56 carries out processing similar to the processing of the decoding device in Fig. 34, except that the columns are not replaced by expression (9).

In particular, Fig. 35 shows an example of the configuration of the decoding section 56 of the I ORS of FIG. 29.

In Fig. 35 section 56 of decoding AND ORS is performed similarly to that in the decoding device according to

Fig. 34, except that the received data rearrangement section 310 of FIG. 34 is not provided, and performs processing similar to that in the decoding device of FIG. 34, except that the columns are not replaced by expression (9). Therefore, the description of GORS decoding section 56 is omitted here.

Since the GORS decoding section 56 can be performed without including the received data permutation section 310 as described above, it can be reduced in size compared to the decoding device of FIG. 34.

It should be noted that, although in Fig. 31 - 35 it is assumed that the length M of the code in the GORS code is equal to 90, the length K of information is equal to 60, the block number P of columns (the number of rows and the number of columns of the component matrix) of the cyclic structure is equal to 5, and the divisor is 4 (- M/R) of the length M parity is equal to b - for a simplified description, the length M of the code, the length K of the information, the block number P of the columns of the cyclic structure, and the divisor d (- M/P) are not individually limited by the specific values given above.

In particular, although the GORS coding section 21 in the transmission device 11 of Fig. 8 displays the code I ORS, in which, for example, the length M of the code is 64,800, the information length K is equal to М - Ра (- М - М), the block number Р of the cyclic structure is 360, and the divisor d is equal to М/Р, section 56 of decoding

GORS according to Fig. 76 can also be applied when the decoding of IGORS is carried out by performing a mathematical operation of the verification node and a mathematical operation of the variable node at the same time for P verification nodes and P variable nodes in relation to such an IORS code as just described.

Although the sequence of procedures described above can be performed in hardware, it can otherwise be performed in software. When a number of processes are performed in software, a program that creates the software is installed on a general purpose computer or the like.

Fig. 36 shows an example of an embodiment of a computer on which a program is installed to perform the sequence of procedures described above.

This program can be recorded in advance on the hard disk 405 or in the ROM 403 as a data carrier built into the computer.

Alternatively, this program may be stored (recorded) temporarily or permanently on or in a removable recording medium 411 such as a floppy disk, CD-ROM, magneto-optical (MO) disk, digital universal disk (MD ), magnetic disk or semiconductor memory. Such a removable recording medium 411 may be provided as a so-called software package.

It should be noted that the program can not only be installed in the computer from such a removable recording medium 411 as described above, but also can be installed in the hard disk 405 built into the computer when it is transferred to it and received by the section 408 connection In this case, the program may be transferred to the computer wirelessly from the download site via an artificial satellite for digital satellite broadcasting, or transferred to the computer via a wired connection over a network such as a local area network (LAN). or the Internet.

The computer has a central processing unit (CPU) (CPU) 402 built into it. An I/O interface 410 is connected to the CPU 402 by a bus 401, and if a command is input to the CPU 402 through the I/O interface 410, when the input section 407 performed from a keyboard, mouse, microphone, etc., is controlled by an operator, or in such a case, the CPU 402 executes a program stored in a non-volatile memory (ROM) device (ROM) 403. Alternatively, the CPU 402 loads a program stored on the hard disk 403, the program transmitted from the satellite or from the network, received by the communication section 408 and installed on the hard disk 405, or the program read from the removable recording medium 411 loaded in the drive 409 and installed on the hard disk 405, in random access memory (RAM) (RAM) 404, and executes this program. Therefore, the CPU 402 performs processing according to the algorithm flowchart described above, or processing performed by the configuration of the flowchart described above. Then, the CPU 402 outputs the processing result from the output section 706 made from the liquid crystal display (LCD) (LCD), speaker, and so on, and transmits the processing result from the communication section 408 through the I/O interface 410 or writes the processing result to hard drive 405 as required.

Here, in this description, the processing steps that describe a program that causes the computer to perform various processes do not necessarily have to occur in time sequence according to the order described as an algorithm flow chart, but include those processes that are subject to execution in parallel or separately (for example, parallel processes or processes with the help of an object).

Further, the program can be processed by a single computer or can be processed through distributed processing by a large number of computers. Next, the program can be transferred to a computer and executed on a computer at a remote location.

It should be noted that the embodiment of this invention is not limited to the specific embodiment described above, but can be varied in various ways without departing from the subject matter of this invention.

In particular, although in this embodiment, parity interleaving and column scrolling interleaving as a permutation process are performed for the GORS code proposed in UMV-5.2, parity interleaving can also be applied to the GORS code of a parity check matrix, in which the information matrix does not have a cyclic structure, if the parity matrix has a step structure.

At the same time, the interleaving of column scrolling as a permutation process can also be applied to the GORS code, whose parity check matrix can change to have a cyclic structure at least when the columns are replaced, the OS-IGORS code (a quasi-cyclic GORS code), and so on, when the entire check matrix on parity has a cyclic structure.

In particular, the parity check matrix of GORS codes made by the parity interleaving object only needs its parity matrix to have a step structure, while it is not necessary for the information matrix to have a cyclic structure.

Next, the GORS code parity check matrix made by the column scrolling interleaving object as a permutation process is not specifically limited to structure.

It should be noted that the permutation process only needs to be able to permute the code bits of the GORS code so that the set of code bits corresponding to the value 1 included in an arbitrary row of the parity check matrix are not included in the same symbol, and that it could be done in a way other than interleaving column scrolling. In particular, the permutation process can be carried out by using not the memory 31 to store data in the direction of the column and in the direction of the row, but, for example, the memory to store data in only one direction and by controlling the write address and the read address of this memory .

Now describes the process for encoding the 1st ODS by the ODS encoding section 21 of the transmission device 11.

For example, in the OMV-5.2 standard, GORS coding is proposed with two different M code lengths equal to 64,800 and 16,200.

For the GORS code, in which the M code length is 64,800, 11 coding rates are proposed, equal to 1/4, 1/3, 2/5, 1.2, 3/5, 2/3, 3/4, A/5, 5/6, 8/9119/10, and for the GORS code, in which the M code length is 16,200, 10 coding rates are proposed, which are 1/4, 1/3, 2/5, 1.2, 3/5, 2 /3, 3/4, 4/5, 5/6 and 8/9.

The HORS coding section 21 encodes (error-correcting coding) into HORS codes with different coding rates, the M code length of which is 64,800 bits or 16,200 bits, according to the parity check matrix H prepared for the M code length and each coding rate.

In particular, the GORS coding section 56 stores the above-described table of initial values of the parity check matrix to obtain the parity check matrix H for each code length M and for each coding rate.

Here, in the UMV-5.2 standard, GORS codes of two different M code lengths of 64,800 and 16,200 are proposed as described above, and 11 different coding rates are proposed for a GORS code whose M code length is 64,800 bits, and 10 different coding rates proposed for the code

GORS, the length of M code of which is 16,200 bits.

Accordingly, when the transmitting device 11 is a device that performs processing in accordance with the YMV-5.2 standard, the GORS coding section 21 stores tables of initial values of parity check matrices that separately correspond to 11 different coding rates for a GORS code whose code length is M is 64,800 bits, and tables of initial values of the parity check matrix separately corresponding to different coding rates for the GORS code whose code length M is 16,200 bits.

The GORS coding section 21 sets the length M of the code and the coding rate r for the GORS codes, for example, in response to the operation of the operator. The M code length and g coding rate set by section 21 of the I ORS coding are referred to below, respectively, as the set M code length and the g coding rate set, respectively.

Section 21 of GORS coding, based on the tables of initial values of the parity check matrix corresponding to the set length M of the code and the set speed g of coding, places elements with the value 1 of the information matrix Na corresponding to the length K (- Mg - length M of the code - length M parity) of information corresponding to the set length M of the code and the set speed r of coding in a period of 360 columns (block number P of columns of the cyclic structure) in the direction of the column to obtain the parity check matrix H.

Then, the HORS coding section 21 extracts information bits for the length K of information from the object data that is the object of transmission, such as image data or sound data supplied from the transmission device 11. Next, the HORS coding section 21 calculates the parity bits that correspond to information bits, based on the parity check matrix H, to obtain a code word (GORS code) for one code length.

In other words, the GORS coding section 21 sequentially performs a mathematical operation on the parity bit of the code word c, which satisfies the following expression:

No" -0.

Here, in the above expression, c denotes the string vector as a code word (GORS code), and c!" denotes the inversion of the string vector c.

When the part of the line vector c as the GORS code (code word) corresponding to the information bits is represented by the line vector A, and the part corresponding to the parity bits is represented by the line vector T, the line vector c can be represented by the expression c - ИА|Т) from vector A line as information bits and vector T line as parity bits.

At the same time, the parity check matrix H is based on the information matrix Ni of those code bits of the GORS code that correspond to the information bits, and the matrix Нt of those code bits of the code

GORS, which correspond to parity bits, can be represented by the expression Н - ИНА|Нт| (a matrix in which the elements of the information matrix NaA are the elements on the left, and the elements of the parity matrix Нt are the elements on the right).

Further, for example, in the OMV-5.2 standard, the parity matrix Нt in the matrix Н - |НА|Нт) of the parity check has a step structure.

For the matrix H check for parity and the vector c - Я|Г| line as a GORS code must satisfy the expression Nese" - 0, and when the matrix Нt in the matrix Н - ИНА|Нт| of the parity check has a step structure, the vector T of the line as parity bits, which configures the vector с - ИА|Т| of the line , which satisfies the expression Not! - 0, can be found by successively setting the elements of each row to zero one by one, starting from the elements in the first row of the vector Hs" of the column in the expression Not" - 0.

If the GORS encoding section 21 finds the T parity bit for the information bit A, it outputs the codeword c - TSIA|T| represented by the A information bit and the T parity bit as a result of the GORS encoding for the A information bit.

As described above, the GORS coding section 21 stores in advance the tables of the initial values of the parity check matrix corresponding to the lengths M of the code and the coding rates g and carries out the GORS encoding of the set length M of the code and the set rate g of the coding using the matrix H of the parity check, obtained from the tables of the initial values of the parity check matrix corresponding to the set length M of the code and the set speed r of coding.

Each table of initial values of the parity check matrix is a table representing the position of elements with a value of 1 of the information matrix Na, which corresponds to the length K of the information, which corresponds to the length M of the code and the encoding speed r of the GORS code of the parity check matrix H (code

GORS determined by the parity check matrix H) for each 360 rows (block number P of columns of the periodic structure), and is obtained in advance for the parity check matrix H and for each code length M and each coding rate r.

Fig. 37 - 82 illustrate the tables of initial values of the parity check matrix, including the tables of initial values of the parity check matrix proposed in the OMV-5.2 standard.

In particular, Fig. 37 shows a table of initial values of the matrix H of the parity check proposed in the ОМВ-5.2 standard and which has a code length M of 16,200 and a coding rate g of 2/3.

Fig. 38 - 40 show a table of initial values of the matrix H of the parity check proposed in the OMV-5.2 standard and which has a code length M of 64,800 and a coding rate g of 2/3.

It should be noted that Fig. 39 is a view continuing from FIG. 38, and Fig. 40 is a view continued from FIG. 39.

Fig. 41 shows a table of initial values of the parity check matrix H proposed in the ОМВ-5.2 standard and which has a code length M of 16,200 and a coding rate g of 3/4.

Fig. 42 - 45 show a table of initial values of the matrix H of the parity check proposed in the ОМВ-5.2 standard and which has a code length M of 64,800 and a coding rate g of 3/4.

It should be noted that Fig. 43 is a view continuing from FIG. 42, and fig. 44 is a view continuing from FIG. 43. Next, Fig. 45 is a view continuing from FIG. 44.

Fig. 46 shows a table of initial values of the parity check matrix H proposed in the ОМВ-5.2 standard and which has a code length M of 16,200 and a coding rate g of 4/5.

Fig. 47 - 50 show a table of initial values of the matrix H of the parity check proposed in the OMV-5.2 standard and which has a code length M of 64,800 and a coding speed g of 4/5.

It should be noted that Fig. 48 is a view continued from FIG. 47, and Fig. 49 is a view continuing from FIG. 48. Next, Fig. 50 is a view continued from FIG. 49.

Fig. 51 shows a table of initial values of the parity check matrix H proposed in the ОМВ-5.2 standard and which has a code length M of 16,200 and a coding rate g of 5/6.

Fig. 52 - 55 show a table of initial values of the matrix H of the parity check proposed in the OMV-5.2 standard and which has a code length M of 64,800 and a coding speed of 5/6.

It should be noted that Fig. 53 is a view continuing from FIG. 52, and fig. 54 is a view continuing from FIG. 53. Next, Fig. 55 is a view continuing from FIG. 54.

Fig. 56 shows a table of initial values of the parity check matrix H proposed in the ОМВ-5.2 standard and which has a code length M of 16,200 and a coding rate g of 8/9.

Fig. 57 - 60 show a table of initial values of the matrix H of the parity check proposed in the ОМВ-5.2 standard and which has a code length M of 64,800 and a coding speed g of 8/9.

It should be noted that Fig. 58 is a view continuing from FIG. 57, and Fig. 59 is a view continuing from FIG. 58. Next, Fig. 60 is a view continuing from FIG. 59.

Fig. 61 - 64 show a table of initial values of the parity check matrix H proposed in the ОМВ-5.2 standard and which has a code length M of 64,800 and a coding speed g of 9/10.

It should be noted that Fig. 62 is a view continuing from FIG. 61, and fig. 63 is a view continuing from FIG. 62. Next, Fig. 64 is a view continuing from FIG. 63.

Fig. 65 and 6b show a table of initial values of the parity check matrix H proposed in the OMV-5.2 standard and which has a code length M of 64,800 and a coding speed of 1/4.

It should be noted that Fig. 66 is a view continuing from FIG. 65.

Fig. 67 and 68 show a table of initial values of the parity check matrix H proposed in the ОМВ-5.2 standard and which has a code length M of 64,800 and a coding rate g of 1/3.

It should be noted that Fig. 68 is a view continued from FIG. 67.

Fig. 69 and 70 show a table of initial values of the parity check matrix H proposed in the ОМВ-5.2 standard and which has a code length M of 64,800 and a coding rate g of 2/5.

It should be noted that Fig. 70 is a view continued from FIG. 69.

Fig. 71 - 73 show a table of initial values of the matrix H of the parity check proposed in the OMV-5.2 standard and which has a code length M of 64,800 and a coding speed of 1/2.

It should be noted that Fig. 72 is a view continuing from FIG. 71, and Fig. 73 is a view continuing from FIG. 72.

Fig. 74 - 76 show a table of initial values of the matrix H of the parity check proposed in the OMV-5.2 standard and which has a code length M of 64,800 and a coding speed of 3/5.

It should be noted that Fig. 75 is a view continued from FIG. 74, and Fig. 76 is a view continuing from FIG. 75.

Fig. 77 shows a table of initial values of the matrix H of the parity check proposed in the OMV-5.2 standard and which has a code length M of 16,200 and a coding rate g of 1/4.

Fig. 78 shows a table of initial values of the matrix H of the parity check proposed in the ОМВ-5.2 standard and which has a code length M of 16,200 and a coding rate g of 1/3.

Fig. 79 shows a table of initial values of the parity check matrix H proposed in the ОМВ-5.2 standard and which has a code length M of 16,200 and a coding speed g of 2/5.

Fig. 80 shows a table of initial values of the matrix H of the parity check proposed in the ОМВ-5.2 standard and which has a code length M of 16,200 and a coding rate g of 1/2.

Fig. 81 shows a table of initial values of the matrix H of the parity check proposed in the ОМВ-5.2 standard and which has a code length M of 16,200 and a coding rate g of 3/5.

Fig. 82 shows a table of initial values of the parity check matrix H proposed in the OMV-5.2 standard and having a code length M of 16,200 and a coding rate g of 3/5, which can be used instead of the table of initial values of the parity check matrix of FIG. 81.

Section 21 of the GORS coding defines the parity check matrices H in the following manner using tables of initial values of the parity check matrix.

In particular, Fig. 83 illustrates a method of determining the parity check matrix H from a table of initial values of the parity check matrix.

It should be noted that the table of initial values of the parity check matrix in Fig. 83 shows a table of initial values of the parity check matrix for the parity check matrix H proposed in the OMV-5.2 standard and having a code length M of 16,200 and a coding rate g of 2/3 shown in FIG. 37.

As described above, the table of initial values of the parity check matrix is a table representing the position of the elements with a value of 1 of the information matrix Na corresponding to the length K of the information corresponding to the length M of the code and the encoding speed g of the GORS code for each 360 columns (for each block the number of P columns in the cyclic structure), and in the first row of this table of initial values of the parity check matrix, the number of row numbers of elements with the value 1 in the (1 "x 360 x (i - 1)) th column of the parity check matrix H (numbers rows, where the row number of the first row of the parity check matrix H is equal to 0) is equal to the number of column weights that the (1 x 360 x (i - 1)|)th column has.

Here, it is assumed that the parity matrix Нt in the parity check matrix H corresponding to the parity length M has a step structure and is determined in advance. According to the table of initial values of the parity check matrix, the information matrix NaA is determined, which corresponds to the length K of information from the parity check matrix H.

Number K -. 1 row of the table of initial values of the parity check matrix differs depending on the length K of the information.

The length K of the information and the number K -- 1 line of the table of initial values of the parity check matrix satisfy the ratio given by the following expression:

K - (K i 1) x 360.

Here, 360 in the above expression is the block number of P columns of the cyclic structure.

In the table of initial values of the parity check matrix in Fig. 83, 13 numerical values are listed in the first-third lines and three numerical values are listed in the fourth - (K -- 1)th (on

Fig. 83 - thirtieth) lines.

Accordingly, the number of column weights in the parity check matrix H found from the table of initial values of the parity check matrix in Fig. 83, is equal to 13 in the first - (1 - 360 x (Z - 1)|th rows, but is equal to Z in (1 - 360 x (Z - 1)) - Kth rows.

The first line of the table of initial values of the parity check matrix in Fig. 83 contains 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622, and this means that in the first column of the parity check matrix H, the elements in rows with row numbers 0 , 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622 are 1 (and other elements are 0).

At the same time, the second line of the table of initial values of the parity check matrix in Fig. 83 indicates 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358 and 3108, and this means that in the 361st (- 1 x 360 x (2 - 1) )| the columns of the parity check matrix H elements in the rows with row numbers 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358 and 3108 have the value 1.

As given above, the table of initial values of the parity check matrix represents the position of the elements with a value of 1 of the information matrix NA in the parity check matrix H for every 360 columns.

Each of the columns of the matrix H of the parity check is different from the (1 - 360 x (i - 1))|th column, i.e. each of the columns from the (2 x 360 x (i - 1)|Yth by (360 x i) -th column contains elements with a value of 1, obtained by cyclic shifting of elements with a value of 1 from (1 j- 360 x (i - 1))|th column, which depends on the table of initial values of the parity check matrix periodically in the downward direction ( in the direction down the column) according to the length M of parity.

In particular, for example, (2 x 360 x (i - 1)|th column is a column obtained by cyclic shift |1 x 360 x (i - 17th column in the downward direction by M/360 (- d), and the next |Z same 360 x (i - 1)|th column is a column obtained by cyclic shift |1 same 360 x (i - 1)|Yth column in the downward direction by 2 x M/Z360 (- 2 (4 ), and then cyclically shift the cyclically shifted (2 - 360 x (i - 1)|)th column in the downward direction by M/360 (- 4).

Now, if it is assumed that the numerical value in the i-th column (I-th left) in the i-th row (i-th from the top) of the table of initial values of the parity check matrix is represented by the value b, ; and the row number of the i-th element with the value 1 in the mth column of the parity check matrix H is represented by the value Nu-, then the number Nu. row of the element with the value 1 in the m/th column other than (1 - 360 x (i - 1)|-th column of the parity check matrix H corresponds to the following expression:

Nuy- - topi, - tod((m - 1),P) x 4, M).

Here, tofu, x) means the remainder of dividing x by y.

At the same time, P is the block number of the columns of the cyclic structure described above and is equal to, for example, 360 in the OMV-5 standard. 2. Next, d is the value of M/360 obtained by dividing the length M of the parity by the block number P (- 360) of the columns of the cyclic structure.

Section 21 of the GORS coding specifies the row number of the elements with the value 1 in the (1 -- 360 x (ii - 1))th column of the parity check matrix H from the table of initial values of the parity check matrix.

Next, section 21 of GORS coding finds the number of the row of the element with the value 1 in the m/th column, which is a column different from (1 z 360 x (ii - 1)|th column of the parity check matrix H, and receives matrix H of the parity check, in which the elements with the row numbers obtained by the above method have the value 1.

Now the variants of the method of replacing the code bits of the GORS code are described in the process of replacing the demultiplexer 25 in the transmission device 11 by the section 32, i.e. the assignment combination (hereinafter referred to as the bit assignment combination) of the code bits of the GORS code and the bits representing the symbol.

In the demultiplexer 26, the code bits of the GORS code are written in the direction of the column in the memory 31, which stores (M/tb)) x (tr) bits in the direction of the column x the direction of the line. After that, the code bits are read in a block of tb bits in the line direction. Next, in the demultiplexer 25, the replacement section 32 replaces the tr code bits read in the direction of the memory line 31 and defines the code bits after this replacement as bits (following each other) of t symbols.

In particular, the replacement section 32 finds the (and the 1st) bit from the most significant bit in the code bits read in the direction of the memory line 31 as the code bit b and finds the (and the 1st) bit from the most significant bit in tr bits with p (following one after the other) symbols as bit y, and then replaces t code bits bo - Yut-y in accordance with the predetermined combination of destination.

Fig. 84 shows an example of a bit assignment combination that can be accepted when the GORS code is a code

GORS, whose M code length is 64,800 and whose coding rate is 5/6 or 9/10, and in addition, the modulation method is 4096OAM and the B factor is 1.

When the GORS code is a GORS code whose code length M is 64,800 and whose coding rate is 5/6 or 9/10, and in addition, the modulation method is 4096OAM and the multiplier B is 1, the demultiplexer has 25 code bits written in memory slots 31 for storing (64,800/12 x 1)) x (12 x 1) bits in the column direction x row direction are read in a block of (12 x 1) (5-5 TB) bits in the row direction and fed to section 32 replacement

The replacement section 32 replaces 12 x 1 (5 tr) code bits Bo - bBii so that 12 x 1 (-5 tb) code bits bo - By, to be read from memory 31, can be assigned 12 x 1 (5 -5 tb) to bits uo - ut of one (- 5) symbol, as can be seen in Fig. 84.

In particular, according to Fig. 84, the replacement section 32 performs replacement for both the GORS code with a coding rate of 5/6 and the GORS code with a coding rate of 9/10 from the number of GORS codes with a code length M equal to 64,800 bits for the purpose of: code bit b bit uv, code digit b: bit uo, code digit b» bit uv, code digit bBz bit ut, code digit ba bit y, code digit b5 bit uz, code digit Be bit ug, code digit b; bit uz, code digit BVv bit y?, code digit bo bit Uto, code digit bo bit ut and code digit b: bit uv.

Fig. 85 shows an example of a bit assignment combination that can be accepted when the GORS code is a code

GORS, whose M code length is 64,800 and whose coding rate is 5/6 or 9/10, and in addition, the modulation method is 4096OAM and the B factor is 2.

When the GORS code is a GORS code whose code length M is 64,800 and whose coding rate is 5/6 or 9/10, and in addition, the modulation method is 4096OAM and the multiplier B is 2, the demultiplexer has 25 code bits written in memory memory slots 31 for storing (64,800/12 x 2)) x (12 x 2) bits in the column direction x row direction are read in a block of (12 x 2) (- tb) bits in the row direction and fed to the swap section 32.

The replacement section 32 replaces 12 x 2 (their tr) code bits Bo - Yugoz so that 12 x 2 (- tb) code bits bo - rgz, to be read from memory 31, can be assigned 12 x 2 (5 tb ) to bits uo - ugz of two (- BV), symbols that follow each other, as can be seen in Fig. 85.

In particular, according to Fig. 85, section 32 of the substitution performs, with respect to both the GORS code with a coding rate of 5/6 and the GORS code with a coding rate of 9/10 from the number of GORS codes with a code length M equal to 64,800 bits, a replacement for the assignment of: code bit b bit uv, code bit b" bit uo, code bit ba bit uv, code bit Be bit ut, code bit Bv bit uh, code bit bo bit uv,

code bit b:2 bit ug, code bit ba bit uz, code bit b'in bit y?, code bit b'in bit Uio, code bit bho bit y, code bit bg2 bit uz. code digit b: ugo bit, code digit Bz bit Ui2, code digit b5 bit Uyiv, code digit b» bit Uiz, code digit bo bit Uyiv, code digit Bi: bit uch, code digit biz bit ucha, code digit b'5 bit uz", code digit Bi7 bit uz", code digit bo bit ugg, code digit b" bit ugz and code digit bgz bit ug.

Here, the combination of assigning the discharges of Fig. 85 uses a combination of assignment of digits by

Fig. 84, in which the factor B is equal to 1 without modification. In particular, the assignment of code bits bo, B»2,..., to 22 bits in; and assignment of code bits Bi, Bz,..., bgz to bits y; similar to the assignment of code bits Bo - Bi: to bits y; according to Fig. 84.

Fig. 86 shows an example of a bit assignment combination that can be adopted when the modulation method is 1024OAM and the GORS code is a GORS code whose M code length is 16,200 and whose coding rate is 3/4, 5/6 or 8/9, and in addition , the factor B is 2, and also when the modulation method is 1024OAM, and the GORS code is a GORS code, the code length M of which is 64,800 and the coding rate of which is 3/4, 5/6 or 9/10, and in addition, the factor B is equal to 2.

When the GORS code is a GORS code, the code length M of which is 16,200 and the coding rate of which is 3/4, 5/6 or 8/9, and in addition, the modulation method is 10240AM and the multiplier B is 2, the demultiplexer has 25 code bits, written in memory 31 to store (16,200/(10 x 2)) x (10 x 2) bits in the column direction x row direction, read in a block of (10 x 2) (- tb) bits in the row direction and fed in section 32 replacements.

On the other hand, when the GORS code is a GORS code whose M code length is 64,800 and whose coding rate is 3/4, 5/6 or 9/10, and in addition, the modulation method is 1024O0AM and the multiplier B is 2, in the demultiplexer 25 code bits written in memory 31 to store (64,800/10 x 2)) x (10 x 2) bits in the column direction x row direction are read in a block of (10 x 2) (- tb) bits in the direction line and are submitted to section 32 substitutions.

The replacement section 32 replaces the 10 x 2 (5 tr) Bo - Bio code bits so that the 10 x 2 (- tb) bo - Bio code bits to be read from the memory 31 can be assigned 10 x 2 (5 tb ) to bits uo - uto of two (- B) symbols that follow each other, as can be seen in Fig. 86.

In particular, according to Fig. 86, the section 32 replaces with respect to all of the GORS codes with a coding rate of 3/4, GORS codes with a coding rate of 5/6, and GORS codes with a coding rate of 8/9 from the number of GORS codes with a code length M equal to 16,200 bits, and codes (ORC with a coding rate of 3/4, GORS codes with a coding rate of 5/6 and GORS codes with a coding rate of 9/10 from the number of GORS codes with M code length equal to 64,800 bits from the number of GORS codes with M code length equal to 64,800 bits, replacement for the assignment of: code bit b to bit uv, code bit b: bit uz, code bit b» bit y?, code bit Bz to bit Uto, code bit ba to bit uio, code bit b5 to bit uh, code bit be to bit uz , code digit b; bit uv, code digit Bv bit y, code digit b bit uv, code digit bo bit uch, code digit Bi: bit uch, code digit b'2 bit ug, code digit biz bit Uiv, code digit Ba bit Uyiv, code digit b'5 bit uz", code digit b'v bit uo,

code digit b'7 bit uch, code digit b'v bit uz and code digit bo bit ut".

Fig. 87 shows an example of a bit assignment combination that can be adopted when the modulation method is 4096OAM and the GORS code is a GORS code whose code length M is 16,200 and whose coding rate is 5/6 or 8/9, and in addition, the factor B is 2, and also when the modulation method is 4096OAM, and the GORS code is a GORS code, the code length M of which is equal to 64,800 and the coding rate of which is 5/6 or 9/10, and in addition, the multiplier B is equal to 2.

When the GORS code is a GORS code, the length M of the code is 16,200 and the coding rate is 5/6 or 8/9, and in addition, the modulation method is 4096OAM and the multiplier p is 2, the demultiplexer has 25 code bits written in memory memory slots 31 for storing (16,200/12 x 2)) x (12 x 2) bits in the column direction x row direction are read in a block of (12 x 2) (- tb) bits in the row direction and fed to the swap section 32.

On the other hand, when the GORS code is a TORS code, the length M of the code is 64,800 and the coding rate is 5/6 or 9/10, and in addition, the modulation method is 40960AM and the multiplier 5 is 2, the demultiplexer has 25 code bits, written in memory 31 to store (64,800/12 x 2)) x (12 x 2) bits in the column direction x row direction, read in a block of (12 x 2) (5 TB) bits in the row direction and fed into section 32 replacement.

The replacement section 32 replaces 12 x 2 (their tr) code bits Bo - Yugoz so that 12 x 2 (- tb) code bits bo - rgz, to be read from memory 31, can be assigned 12 x 2 (5 tb ) to bits uo - ugz of two (- B) symbols that follow each other, as can be seen in Fig. 87.

In particular, according to Fig. 87, the section 32 replaces with respect to all of the GORS codes with a coding rate of 5/6 and GORS codes with a coding rate of 8/9 from the number of IORS codes with a code length M equal to 16,200 bits, as well as GORS codes with a coding rate of 5/6 and GORS codes with a coding speed of 9/10 of the number of codes

GORS with M code length equal to 64,800 bits from the number of GORS codes with M code length equal to 64,800 bits, replacement for the assignment of: code bit Uto bit, code bit b: bit uv, code bit b» bit y, code bit Bz bit uUto, code bit ba bit ugi, code bit b5 bit Uiv, code bit Be bit ugg, code bit b» bit Uyiv, code bit BVv bit Uch, code bit bo bit Ua, code bit bo bit ugg, code bit b: bit uv, code digit b'2 bit uv, code digit biz bit ut, code digit Ba bit Uiz, code digit b: ugo bit, code digit b'in bit uch, code digit b'7 bit uz, code digit b'v bit uz, code digit bo bit ug, code digit bgo bit y?, code digit b»: bit uv, code digit bg2 bit uig and code digit bgz bit uo.

According to the combinations of discharge assignments shown in Fig. 84 - 87, the same bit assignment combination can be adopted for multiple types of GORS codes, and furthermore, the error tolerance can be set to a desired characteristic with respect to all multiple types of codes

MOUNTAIN

In particular, Fig. 88 - 91 illustrate the results of the simulation of the frequency of occurrence of erroneous bits (BEC) when the replacement process is carried out in accordance with the combinations of assignment of the digits of FIG. 84 - 87.

It should be noted that in fig. 88 - 91 the abscissa represents E5/Mo (the ratio of signal power to noise power per symbol), and the ordinate represents VEC.

Next, the bold curved line represents the VEC when the replacement process is carried out, and the dash-dotted line represents the VEC when the replacement process is not carried out.

Fig. 88 illustrates the VEC when the replacement process according to the combination of the discharge assignments of FIG. 84 is carried out for GORS codes, the code length M of which is 64,800, and the coding rate of which is 5/6 and 9/10, taking 4096OAM as the modulation method and setting the multiplier B to 1.

Fig. 89 illustrates the VEC when the replacement process according to the combination of the discharge assignments of FIG. 85 is carried out for GORS codes, whose M code length is 64,800, and whose coding rate is 5/6 and 9/10, taking 4096OAM as the modulation method and setting the multiplier b to 2.

It should be noted that in Fig. 88 and 89, the graph with the triangular labels on it represents the VEC relative to the GORS code at the coding rate 5/6, and the graph with the star-shaped labels on it represents the VEC with respect to the GORS code at the coding rate 9/10.

Fig. 90 illustrates the VEC when the replacement process according to the combination of the discharge assignment of FIG. 86 is performed for HORS codes whose M code length is 16,200 and whose coding rate is 3/4, 5/6 and 8/9, and HORS codes whose M code length is 64,800 and whose coding rate is 3/4, 5/6 and 9/10, taking 1024OAM as the modulation method and setting the multiplier B to 2.

It should be noted that in fig. 90, the graph with the star-shaped labels on it represents the VEC relative to the GORS code with M code length 64,800 and the coding rate 9/10, and the graph with the upward triangular labels on it represents the VEC with respect to the GORS code with M code length 64.800 and the coding rate 5/ 6. Next, the graph with the square labels on it represents the VEC relative to the GORS code with a code length M of 64,800 and a coding rate of 3/4.

Next, in Fig. 90, the plot with the circular labels on it represents the VEC relative to the GORS code with M code length 16,200 and the coding rate 8/9, and the graph with the downward triangular labels on it represents the VEC with respect to the GORS code with M code length 16,200 and the coding rate 5/ 6. Next, the graph with the cross-shaped marks on it represents the WEE. relative to the GORS code with M code length 16,200 and coding speed 3/4.

Fig. 91 illustrates the VEC when the replacement process according to the combination of the assignment of the discharges of FIG. 87 is carried out for GORS codes whose M code length is 16,200 and whose coding rate is 5/6 and 8/9, and GORS codes whose M code length is 64,800 and whose coding rate is 5/6 and 9/10, taking 4096OAM as the modulation method and setting the multiplier B to 2.

It should be noted that in fig. 91, the graph with the star-shaped labels on it represents the VEC relative to the GORS code with M code length 64.800 and the coding rate 9/10, and the graph with the upward triangular labels on it represents the VEC with respect to the GORS code with M code length 64.800 and the coding rate 5/ 6.

Next, in Fig. 91 graph with circular labels on it represents the VEC relative to GORS code with M code length 16,200 and coding rate 8/9, and the graph with downward triangular labels on it represents VEC with respect to GORS code with M code length 16,200 and coding rate 5/ 6.

According to Fig. 88 - 91, the same combination of digit assignment can be accepted for multiple types of GORS codes. In addition, the error tolerance can be set to the desired characteristic with respect to all the numerous types of GORS codes.

In particular, when the bit assignment combination for exclusive use is adopted for each of a plurality of types of GORS codes having different code lengths and different coding rates, the error tolerance can be raised to a very high value, but it is necessary to change the bit assignment combination for each of the plurality of types GORS codes.

On the other hand, according to the combinations of assignment of discharges in Fig. 84 - 87, the same combination of bit assignment can be adopted for a plurality of types of GORS codes having different code lengths and different coding rates, and the need to change the combination of bit assignments for each of the plurality of types of GORS codes is eliminated, as in the case where the combination the designation of digits for exclusive use is accepted for each of the plurality of types of codes and ORS.

Next, in accordance with the combinations of assignment of the discharges in Fig. 84 - 87 error tolerance can be raised to a very high value, although it is somewhat lower than when a combination of exclusive use bit assignments is adopted for each of a plurality of GORS code types.

In particular, for example, when the modulation method is 4096OAM, the same combination of bit assignments in Fig. 84 or 85 can be used for all GORS codes that have an M code length of 64,800 and a coding rate of 5/6 or 9/10. Even when the combination of assigning bits for exclusive use to each of the plurality of types of IOR codes is adopted in such a manner, the error tolerance can be raised to a high value.

Further, for example, when the modulation method is 1024OAM, the same combination of destination bits for

Fig. 86 can be accepted for all GORS codes that have an M code length of 16,200 and a coding rate of 3/4, 5/6 and 8/9, and GORS codes that have an M code length of 64,800 and a coding rate of 3/4, 5/6 and 9/10. Then, even if the combination of assigning bits for exclusive use for each of the plurality of types of GORS codes is adopted in this way, the error tolerance can be raised to a high value.

At the same time, for example, when the modulation method is 4096OAM, the same combination of assignment of digits in Fig. 87 can be accepted for all IGORS codes that have an M code length of 16,200 and a coding rate of 5/6 and 8/9, and GORS codes that have an M code length of 64,800 and a coding rate of 5/6 and 9/10. Then, even if the combination of assigning bits for exclusive use for each of the plurality of types of GORS codes is adopted in this way, the error tolerance can be raised to a high value.

Next, the options for the combination of the assignment of discharges are described.

Fig. 92 illustrates an example of a bit assignment combination that can be adopted when the I ODS code is any ODS code having a code length M of 16,200 or 64,800 bits and one of the coding rates for the ODS code defined by the parity check matrix H obtained, e.g. , from each of the tables of initial values of the parity check matrix shown in Fig. 37 - 82, different from the coding rate of 3/5, and in addition, the modulation method is ORBZK and the multiplier B is equal to 1.

When the GORS code is a GORS code having a code length M of 16,200 or 64,800 bits and a coding rate other than 3/5, and in addition, the modulation method is ORBZK and the multiplier B is equal to 1, the demultiplexer 25 reads the code bits written in the memory block 31 for storing (M/2 x 1)) x (2 x 1) bits in the column direction x row direction in a block of 2 x 1 (- tb) bits in the row direction and supplies the read code bits to the swap section 32.

Substitution section 32 replaces 2 x 1 (- tr) code bits bo and ri read from memory 31, so that 2 x 1 (5 tb) code bits bo and Bi are assigned to 2 x 1 (- tb) bits uo and ui of one (- B) symbol, as can be seen from Fig. 92.

In particular, according to Fig. 92, section 32 of the replacement makes a replacement for assigning the code bit to the u0 bit, and the code bit to the b: bit uch.

It should be noted that in this case, it can also be assumed that the replacement is not carried out, and the code bits bo and b: are found as if they were bits ub and u:i, respectively.

Fig. 93 shows an example of the bit assignment combination accepted when the GORS code is a code

GORS, which has a code length M of 16,200 or 64,800 bits and has a coding rate other than 3/5, and in addition, the modulation method is 16O0AM and the multiplier B is 2.

When the GORS code is a GORS code having a code length M of 16,200 or 64,800 bits and a coding rate other than 3/5, and in addition, the modulation method is 16O0OAM and the multiplier B is 2, the demultiplexer 25 reads the code bits stored in the memory block 31 for storing (MA x 2)) x (4 x 2) bits in the column direction x row direction in a block of 4 x 2 (5 TB) bits in the row direction and feeds the read code bits to the section 32 of the swap.

Substitution section 32 replaces 4 x 2 (x tb) code bits bo - p7 read from memory 31, so that 4 x 2 (x tb) code bits are assigned to 4 x 2 (5 tb) bits uo - y7 of two (- B) symbols that follow each other, as can be seen from Fig. 93.

In particular, according to Fig. 93, section 32 of the substitution performs a substitution for the assignment of the code digit b to the bit y?, the code digit b: the bit uch, the code digit b» to the bit y, the code digit Bz to the bit ug, the code digit ba to the bit uv, the code digit b5 to the bit uz, the code digit Be bit uv, and code digit b; bitu uo

Fig. 94 shows an example of a receiving bit assignment combination when the modulation method is 64OAM and the GORS code is a GORS code having a code length M of 16,200 or 64,800 bits and a coding rate other than 3/5, and in addition, the multiplier p is 2.

When the GORS code is a GORS code having a code length M of 16,200 or 64,800 bits and a coding rate other than 3/5, and in addition, the modulation method is 640OAM and the multiplier B is 2, the demultiplexer 25 reads the code bits written in the memory block 31 for storing (M/6 x 2)) x (6 x 2) bits in the column direction x row direction in a block of 6 x 2 (- tb) bits in the row direction and supplies the read code bits to the swap section 32.

Substitution section 32 replaces 6 x 2 (xx tb) code bits bo - Bi read from memory 31, so that 6 x 2 (- tb) code bits bo - ii are assigned to 6 x 2 (- tb) bits uo - two (- B) symbols that follow each other, as can be seen from Fig. 94.

In particular, according to Fig. 94, section 32 of the substitution performs a substitution for assigning the code bit Uch bit, the code bit b: bit y?, the code bit b» the bit uz, the code bit Bz the bit Uto, the code bit ba the bit uv, the code bit b5 the bit ug, the code bit be bit uz, code bit b; bit uv, code digit BVv bit ut, code digit bo bit uv, code digit bo bit uz, and code digit b: bit uo.

Fig. 95 shows an example of the bit assignment combination that is accepted when the modulation method is

2560OAM and the GORS code is a GORS code that has a code length M of 64,800 bits and in which the coding rate is different from 3/5, and in addition, the multiplier p is equal to 2.

When the GORS code is a GORS code having a code length M of 64,800 bits and in which the coding rate is different from 3/5, and in addition, the modulation method is 2560AM and the multiplier 5 is equal to 2, the demultiplexer 25 reads the code bits written in the memory 31 to store (64,800/(8 x 2)) x (8 x 2) bits in the column direction x row direction in a block of 8 x 2 (- tb) bits in the row direction and feeds the read code bits to the swap section 32.

Substitution section 32 replaces 8 x 2 (xx tb) code bits bo - Bi5 read from memory 31, so that 8 x 2 (- tbr) code bits Bo - bi5 are assigned to 8 x 2 (- tb) bits uo - ui5 of two (- B) symbols following each other, as can be seen from Fig. 95.

In particular, according to Fig. 95, section 32 of the substitution makes a substitution for the assignment of the code bit uUi5, the code bit b: bit uch, the code bit Uiz bit, the code bit bBz bit uz, the code bit ba bit uv, the code bit b5 bit Ut, the code bit be bit uz, code digit b; bit uv, code bit Bv bit Uto, code bit bw bit uv, code bit y, code bit b: bit uo, code bit Bi» bit uig, code bit biz bit ug, code bit Ba bit ucha, and code bit b: bitu uo.

Fig. 96 shows an example of the bit assignment combination adopted when the modulation method is 2560OAM and the GORS code is a GORS code having a code length M of 16,200 bits and in which the coding rate is different from 3/5, and in addition, the multiplier p is equal to 1.

When the GORS code is a GORS code having a code length M of 16,200 bits and in which the coding rate is different from 3/5, and in addition, the modulation method is 2560AM and the multiplier 5 is equal to 1, the demultiplexer 25 reads the code bits written in the memory 31 to store (16,200/(8 x 1)) x (8 x 1) bits in the column direction x row direction in a block of 8 x 1 (- tb) bits in the row direction and feeds the read code bits to the swap section 32.

Substitution section 32 replaces 8 x 1 (x tb) code bits bo - p7 read from memory 31, so that 8 x 1 (- t) code bits bo - b7 are assigned to 8 x 1 (- tb) bits uo - in; one (- B) symbol, as can be seen from Fig. 96.

In particular, according to Fig. 96, section 32 of the substitution performs a substitution for the assignment of the code digit bo to the bit y?, the code digit b: the bit uz, the code digit b» to the bit uch, the code digit bBz to the bit uz, the code digit ba to the bit u?g, the code digit Bb5 to the bit uv, code digit Be bit uh, and code digit b; bitu uo

Fig. 97 shows an example of the bit assignment combination accepted when the GORS code is a code

GORS, which has a code length M of 16,200 or 64,800 bits and has a coding rate other than 3/5, and in addition, the modulation method is ORB5K and the multiplier 5 is equal to 1.

When the GORS code is a GORS code having a code length M of 16,200 or 64,800 bits and a coding rate other than 3/5, and in addition, the modulation method is ORBZK and the multiplier B is equal to 1, the demultiplexer 25 reads the code bits written in the memory block 31 for storing (M/2 x 1)) x (2 x 1) bits in the column direction x row direction in a block of 2 x 1 (- tb) bits in the row direction and supplies the read code bits to the swap section 32.

The replacement section 32 replaces 2 x 1 (- tb) code bits bo and ri read from memory 31, so that 2 x 1 (5 tb) code bits bo and Bi are assigned to 2 x 1 (- tb) bits uo and ui of one (- B) symbol, as can be seen from Fig. 97.

In particular, according to Fig. 97, section 32 of the replacement makes a replacement for assigning the code bit to the u0 bit, and the code bit to the b: bit uch.

It should be noted that in this case it can also be considered that the replacement is not carried out, and the code bits bo and bi are found, assuming that they are bits uo and uch, respectively.

Fig. 98 shows an example of a combination of assigning receiving bits when the GORS code is a code

GORS, which has a code length M of 64,800 bits and the coding rate of which is 3/5, and in addition, the modulation method is 16OAM and the multiplier B is 2.

When the GORS code is a GORS code having a code length M of 64,800 bits and a coding rate of 3/5, and in addition, the modulation method is 16OAM and the multiplier p is 2, the demultiplexer 25 reads the code bits written in the memory 31 to store (64,800/(4 x 2)) x (4 x 2) bits in the column direction x row direction in a block of 4 x 2 ("5 TB) bits in the row direction and feeds the read code bits to the swap section 32.

Substitution section 32 replaces 4 x 2 (x tb) code bits bo - p7 read from memory 31, so that 4 x 2 (- tbB) code bits bo - b7 are assigned to 4 x 2 (- tb) bits uo - in; two (- B) sequentially located symbols, as can be seen from Fig. 98.

In particular, according to Fig. 98, section 32 of the substitution performs a substitution for the assignment of the code digit b to bit uo, the code digit b: bit uv, the code digit b» to bit uch, the code digit bBz to bit ug, the code digit ba to bit y, the code digit b5 to bit y?, the code digit Be bit uz, and code digit b; bitu uv.

Fig. 99 shows an example of the bit assignment combination accepted when the GORS code is a code

GORS, which has a code length M of 16,200 bits and in which the coding rate is 3/5, and in addition, the modulation method is 16OAM and the multiplier B is 2.

When the GORS code is a GORS code having a code length M of 16,200 bits and in which the coding rate is 3/5, and in addition, the modulation method is 16OAM and the multiplier p is 2, the demultiplexer 25 reads the code bits written in the memory 31 to store (16,200/(4 x 2)) x (4 x 2) bits in the column direction x row direction in a block of 4 x 2 ("5 TB) bits in the row direction and feeds the read code bits to the swap section 32.

Substitution section 32 replaces 4 x 2 (x tb) code bits bo - p7 read from memory 31, so that 4 x 2 (- tb) code bits Bo - b7 are assigned to 4 x 2 (- tb) bits uo - in; two (- B) sequentially located symbols, as can be seen from Fig. 99.

In particular, according to Fig. 99, section 32 of the substitution performs a substitution for the assignment of the code digit b to the bit y?, the code digit b: the bit uch, the code digit b» to the bit y, the code digit bBz to the bit ug, the code digit ba to the bit uv, the code digit b5 to the bit uz, the code digit Be bit uv, and code digit b; bitu uo

Fig. 100 shows an example of a bit assignment combination adopted when the modulation method is 640OAM and the GORS code is a GORS code having a code length M of 64,800 bits and in which the coding rate is 3/5 and in addition the multiplier p is 2.

When the GORS code is a GORS code having a code length M of 64,800 bits and in which the coding rate is 3/5, and in addition, the modulation method is 640OAM and the multiplier 6 is 2, the demultiplexer 25 reads the code bits written in the memory 31 to store (64,800/(6 x 2)) x (6 x 2) bits in the column direction x row direction in a block of 6 x 2 (- tb) bits in the row direction and feeds the read code bits into the swap section 32.

Substitution section 32 replaces 6 x 2 (xx tb) code bits bo - Bi read from memory 31, so that 6 x 2 (5 t) code bits bo - bii are assigned to b x 2 (- tb) bits uo - in two (- B) sequentially located symbols, as can be seen from Fig. 100.

In particular, according to Fig. 100, section 32 of the substitution performs a substitution for the assignment of the code bit b to the bit ug, the code bit b: the bit y?, the code bit b» to the bit uv, the code bit bBz to the bit uz, the code bit ba to the bit uo, the code bit b5 to the bit uz, the code bit Be bitu ut, code bit b; bit uv, code bit Bv bit uh, code bit Uch, code bit Uch, code bit ub, and code bit Bi: bit Uo.

Fig. 101 shows an example of the bit assignment combination adopted when the modulation method is 640OAM and the GORS code is a GORS code having a code length M of 16,200 bits and in which the coding rate is 3/5 and in addition the multiplier p is 2.

When the GORS code is a GORS code having a code length M of 16,200 bits and in which the coding rate is 3/5, and in addition, the modulation method is 640OAM and the multiplier p is 2, the demultiplexer 25 reads the code bits written in the memory 31 to store (16,200/(6 x 2)) x (6 x 2) bits in the column direction x row direction in a block of 6 x 2 ("5 Tb) bits in the row direction and feeds the read code bits to the swap section 32.

Substitution section 32 replaces 6 x 2 (xx tb) code bits bo - Bi read from memory 31, so that 6 x 2 (5 t) code bits bo - bii are assigned to b x 2 (- tb) bits uo - in two (- B) sequentially located symbols, as can be seen from Fig. 101.

In particular, according to Fig. 101, section 32 of the substitution performs a substitution for the assignment of the code digit b to the Uch bit, the code digit b: the bit y?, the code digit b» to the bit uz, the code digit Bz to the bit Uto, the code digit ba to the bit uv, the code digit b5 to the bit ug, the code digit be bit uz, code bit b; bit uv, code digit BVv bit ut, code digit bo bit uv, code digit bo bit uz, and code digit b: bit uo.

Fig. 102 shows an example of the bit assignment combination adopted when the modulation method is 2560OAM and the GORS code is a GORS code having a code length M of 64,800 bits and in which the coding rate is 3/5 and in addition the multiplier p is 2.

When the GORS code is a GORS code having a code length M of 64,800 bits and in which the coding rate is 3/5, and in addition, the modulation method is 2560AM and the multiplier p is 2, the demultiplexer 25 reads the code bits written in the memory 31 to store (64,800/(8 x 2)) x (8 x 2) bits in the column direction x row direction in a block of 8 x 2 ("5 TB) bits in the row direction and feeds the read code bits to the swap section 32.

The replacement section 32 replaces 8 x 2 (xx tb) code bits bo - Bi5 read from memory 31, so that 8 x 2 (5-5 tb) code bits bo - bi5 are assigned to 8 x 2 (5 tb) bits uo - ui5 of two (- B) sequentially arranged symbols, as can be seen from Fig. 102.

In particular, according to Fig. 102, the section 32 of the substitution performs a substitution for the assignment of the code digit bo to the bit ug, the code digit b: the bit uch, the code digit b» to the bit uz, the code digit bBz to the bit uh, the code digit ba to the bit uo, the code digit b5 to the bit uz, the code digit Be bit ut, code bit b; bit uv, code bit Bv bit Uto, code bit Uiz bit, code bit y?, code bit Bi: bit ucha, code bit b'2 bit uv, code bit biz bit uv, code bit Ba bit y, and code bit b: bit ut".

Fig. 103 shows an example of the bit assignment combination adopted when the modulation method is 2560OAM and the GORS code is a GORS code having a code length M of 16,200 bits and in which the coding rate is 3/5 and in addition the multiplier p is 1.

When the GORS code is a GORS code having a code length M of 16,200 bits and in which the coding rate is 3/5, and in addition, the modulation method is 2560AM and the multiplier p is 1, the demultiplexer 25 reads the code bits written in the memory 31 to store (16,200/(8 x 1)) x (8 x 1) bits in the column direction x row direction in a block of 8 x 1 (- tb) bits in the row direction and feeds the read code bits to the swap section 32.

Substitution section 32 replaces 8 x 1 (x tb) code bits bo - p7 read from memory 31, so that 8 x 1 (- t) code bits bo - b7 are assigned to 8 x 1 (- tb) bits uo - in; one (- B) symbol, as can be seen from Fig. 103.

In particular, according to Fig. 103, section 32 of the substitution performs a substitution for the assignment of the code digit bo to the bit y?, the code digit b: bit uz, the code digit b» to the bit uch, the code digit bBz to the bit uz, the code digit ba to the bit u?g, the code digit Bb5 to the bit uv, code digit Be bit uh, and code digit b; bitu uo

The deinterleaver 53 that forms the receiving device 12 is now described.

Fig. 104 illustrates the processing of the multiplexer 54 that constitutes the deinterleaver 53.

In particular, part A of Fig. 104 shows an example of the functional configuration of multiplexer 54.

The multiplexer 54 consists of a reverse swap section 1001 and a memory 1002.

The multiplexer 54 finds the bits provided from the reverse mapping section 52 in the previous stage as the object of its processing, and performs a reverse replacement process corresponding to the replacement process performed by the demultiplexer 25 of the transmission device 11 (a process inverse of the replacement process), that is, a reverse replacement process replacement by returning the positions of code bits (bits) of the GORS code replaced in the process of replacement. Then, the multiplexer 54 feeds the GORS code obtained as a result of the reverse replacement process to the deinterleaver 55 scrolling the columns to the next step.

In particular, in the multiplexer, 54 tr bits уо, уй,..., Ут-- of Ю symbols are supplied in a block of B (following one after the other) symbols to the section 1001 of reverse replacement.

The reverse replacement section 1001 carries out a reverse replacement by returning the placement of the symbol bits уо, уй,..., Утя to the original placement of the code bits бо, Би,..., Ют-- (placement of the code bits бо, Би,... , Yut- before the replacement in the replacement section 32, which is the demultiplexer 25 on the side of the transmission device 11). The reverse substitution section 1001 outputs the code bits bo, bi,..., Yut-i, obtained as a result of the reverse substitution.

The memory 1002 has a storage capacity for storing tb bits in the (horizontal) row direction and storing M/tb) bits in the (vertical) column direction similarly to the memory 31, which constitutes the demultiplexer 25 on the side of the transmission device 11. In other words, the section 1001 reverse substitution is made of tr columns, each of which stores Mt) bits.

However, in the memory 1002, the recording of the code bits output from the reverse replacement section 1001 is carried out in the direction in which the reading of the code bits from the memory 31 of the demultiplexer 25 of the transmission device 11 is carried out, and the reading of the code bits recorded in the memory 1002, is carried out in the direction in which code bits are recorded in memory 31.

In particular, the multiplexer 54 of the receiving device 12 sequentially records the code bits of the GORS code, which is output from the reverse replacement section 1001 in a block of tb bits in the row direction, starting from the first memory row 1002 to the bottom row, as seen in part A of Fig. . 104.

Then, when the recording of the code bits for one code length ends, the multiplexer 54 reads the code bits in the direction of the column from the memory 1002 and feeds the code bits to the deinterleaver 55 of scrolling the columns in the next stage.

Here, part B of Fig. 104 illustrates reading code bits from memory 1002.

The multiplexer 54 reads the code bits in a downward direction (column direction) from the top of the column constituting the memory 1002, starting from the leftmost column to the column on the right side.

Now with reference to fig. 105 describes the processing of the column scrolling deinterleaver 55, which is the deinterleaver 53 of the receiving device 12.

Fig. 105 shows an example of the memory configuration 1002 of the multiplexer 54.

Memory 1002 has a storage capacity to store tr bits in the (vertical) column direction and stores Mt) bits in the (horizontal) row direction and consists of tr columns.

The column scrolling deinterleaver 55 writes the code bits of the GORS code in the row direction into the memory 1002 and controls the position at which reading starts when the code bits are read in the column direction to perform column scrolling deinterlacing.

In particular, the column scrolling deinterleaver 53 performs a process of reversing the corresponding change of the initial reading position, in which the reading of the code bits with respect to each of the plurality of columns should begin to return the placement of the code bits rearranged by the column scrolling interleaver to the original placement.

Here, Fig. 105 shows an example of the configuration of the memory 1002, when the modulation method is 16OAM, and the multiplier p is equal to 1. Accordingly, the number of t bits of one symbol is 4, and the memory 1002 contains four (- tb) columns.

Column scrolling deinterleaver 55 performs (instead of multiplexer 54) writing the code bits of the GORS code, derived from the reverse replacement section 1001, in the direction of the line sequentially into the memory 1002, starting from the first line to the lowest line.

Then, if the writing of code bits for one code length ends, the column scrolling deinterleaver 55 reads the code bits in a downward direction (column direction) from the top of the memory 1002, starting from the leftmost column to the column on the right side.

However, the column scrolling deinterleaver 55 reads the code bits from the memory 1002 by finding the start position of writing when the code bits are written by the column scrolling interleaver 24 on the side of the transmission device 11, to read the starting position of the code bits.

Specifically, if the address of the top position of each column is defined as 0, and the address of each position in the direction of the column is represented by an integer specified in ascending order, then when the modulation method is 160AM and the multiplier p is 1, the column scroll deinterleaver 55 sets the starting read position for the leftmost column to the position whose address is 0, sets the starting read position for the second column (left) to the position whose address is 2, sets the starting read position of the third column to the position whose address is 4, and sets the starting read position for the fourth column to the position whose address is 7.

It should be noted that in relation to each of those columns, the initial reading position of which has an address other than 0, the reading of the code bits is carried out in such a way that after the reading is carried out down to the lowest position, the reading of the position returns to the top (to the position, address which is equal to 0) of the column and the reading is carried out down to the position immediately preceding the initial reading position. Then, after that, reading is done from the next (right) column.

By performing such column scroll interleaving as described above, the placement of the code bits rearranged by the column scroll interleaving returns to its original position.

Fig. 106 is a block diagram showing another example configuration of the receiving device 12 .

In Fig. 106 receiving device 12 is a data processing device that receives the modulated signal from the transmitting device 11 and contains section 51 orthogonal demodulation, section 52 reverse mapping, deinterleaver 53 and section 1021 decoding AND ORS.

The orthogonal demodulation section 51 receives the modulated signal from the transmission device 11, carries out orthogonal demodulation and supplies the symbols (values in the direction of the I and 0 axes) obtained as a result of the orthogonal demodulation to the reverse display section 52.

The reverse mapping section 52 carries out reverse mapping by converting the symbols from the orthogonal demodulation section 51 into code bits of the GORS code and feeds the code bits into the deinterleaver 53.

The deinterleaver 53 includes a multiplexer (MOX) 54, a column scrolling deinterleaver 55 and a parity deinterleaver 1011 and deinterleaves the code bits of the GORS code from the reverse mapping section 52.

In particular, the multiplexer 54 determines the GORS code from the reverse mapping section 52 as the object of its processing and performs a reverse replacement process that corresponds to the replacement process performed by the demultiplexer 25 of the transmission device 11 (a process that is the reverse of the replacement process), that is, a reverse replacement process by returning positions of the code bits replaced by the replacement process into the original positions.

The multiplexer 54 then feeds the GORS code obtained as a result of the reverse replacement process to the deinterleaver 55 of scrolling columns.

The column scrolling deinterleaver 55 determines the GORS code from the multiplexer 54 as the object of its processing and performs column scrolling deinterleaving, which corresponds to the column scrolling interleaving in the role of the permutation process performed by the column scrolling interleaver 24 of the transmission device 11.

The GORS code obtained as a result of column scrolling deinterleaver is fed from the column scrolling deinterleaver 55 to the parity deinterleaver 1011.

The parity deinterleaver 1011 determines the code bits after deinterleaving the column scrolling by the column scrolling deinterleaver 55 as the object of its processing and performs parity deinterleaving, which corresponds to the parity interleaving performed by the parity interleaver 23 of the transmission device 11 (the reverse process of parity interleaving), that is, parity deinterleaving by returning the placement of code bits of the GORS code, the placement of which was changed by parity interleaving, to the original placement.

The GORS code obtained as a result of deinterleaving the parity is fed from the deinterleaver 1011 of the parity to the section 1021 of the decoding of the I ODS.

Accordingly, in the receiving device 12 of Fig. 106 GORS code, for which the process of reverse replacement, column scrolling deinterleaving and parity deinterleaving have been carried out, i.e. the I ODS code obtained by HORS encoding according to the parity check matrix H is fed to the I ODS decoding section 1021.

The HORS decoding section 1021 carries out the HORS decoding of the HORS code from the deinterleaver 53 using the same parity check matrix H used to encode the HORS by the HORS coding section 21 of the transmitting device 11, or the transformed parity check matrix obtained by performing at least a column transformation corresponding to interleaving parity, for the parity check matrix H. Then, the GORS decoding section 1021 outputs the data obtained by decoding AND ORS as the result of object data decoding.

Here, in the receiving device 12 of FIG. 106, because the TOR code obtained by the TOR encoding according to the parity check matrix H is fed from the (parity 3 deinterleaver 1011) of the deinterleaver 53 to the TOR decoding section 1021, when the TOR decoding of the TOR code is performed using the same parity check H matrix used for HORS encoding of HORS sections 21 HORS encoding of transmission device 11, HORS decoding section 1021 can be performed, for example, from a decoding device performing HORS decoding in accordance with the method of full sequential decoding, in which the mathematical operation of messages (verification node messages and variable node messages) is carried out for one node after another, or another decoding device, in which IGORS decoding is carried out in accordance with the method of full parallel decoding, in which the mathematical operation of messages is carried out simultaneously (in parallel) for all nodes.

Next, when the HORS decoding of the HORS code is performed using a transformed parity check matrix obtained by performing at least column swapping corresponding to parity interleaving for parity interleaving for the parity check matrix H used in HORS encoding by the HORS encoding section 21 of the transmission device 11, the section 1021 HORS decoding can be performed from a decoding device with an architecture that performs a check node math operation and a variable node math operation simultaneously for P (or a divisor of P other than 1) check nodes and P variable nodes and which has a received data permutation section 310 to perform replacement of columns, which is similar to the replacement of columns to obtain the transformed parity check matrix for the GORS code for permuting the code bits of the codes

MOUNTAIN

It should be noted that although Fig. 106 multiplexer 54 for performing the reverse replacement process, column scrolling deinterleaver 55 for performing column scrolling deinterleaving, and parity deinterleaver 1011 for performing parity deinterleaving are made separate from each other for ease of description, two or more of multiplexer 54, column scrolling deinterleaver 55, and parity deinterleaver 1011 can be performed together similarly to the parity interleaver 23, the column scrolling interleaver 24 and the demultiplexer 25 of the transmission device 11.

Fig. 107 is a block diagram showing a first embodiment of a receiving system that may be implemented in the receiving device 12.

In Fig.107, the receiving system includes a reception section 1101, a transmission line decoding processing section 1102, and an information source decoding processing section 1103.

The receiving section 1101 receives a signal including a GORS code obtained by GORS encoding at least object data such as image data and program music data through a transmission line such as, for example, digital terrestrial broadcasting, digital satellite broadcasting, cable network television (SATUM), the Internet or some other network. Then, the receiving section 1101 feeds the received signal to the transmission line decoding processing section 1102.

Here, when the signal received by the receiving section 1101 is broadcast, for example, from a broadcasting station using surface waves, satellite waves, cable television (SATU) or the like, the receiving section 1101 is made of a tuner, a set-top box (TV set-top box) or the like . On the other hand, when the signal received by the receiving section 1101 is transmitted in a multicast state, as in Internet Television (ITV), for example, from a web server, the receiving section 1101 is implemented from a network interface, such as, for example, a network interface card ( MISS).

The transmission line decoding processing section 1102 performs a transmission line decoding process, which includes at least a process of correcting errors occurred in the transmission line for the signal received through the transmission line by the receiving section 1101, and supplies the signal obtained as a result of the transmission line decoding process to section 1103 processing of decoding the information source.

Specifically, the signal received through the transmission line by the receiving section 1101 is a signal obtained by performing at least error-correction coding to correct errors occurring in the transmission line, and for such a signal as just described, the transmission line decoding processing section 1102 performs a transmission line decoding process, such as an error correction process.

Here, as error-correcting encodings are available, for example, GORS encoding, Reed encoding-

Solomon and so on. Here, as error-correcting coding is done at least coding

MOUNTAIN

Further, the process of decoding the transmission line sometimes involves demodulation of the modulated signal, and so on.

The information source decoding processing section 1103 performs the information source decoding process, which includes at least the process of expanding the compressed information into the output information for the signal for which the transmission line decoding process is performed.

In particular, the signal received through the transmission line by the receiving section 1101 is sometimes processed by compression coding for compressed information to reduce the amount of data such as image, sound and so on as information. In this case, the information source decoding processing section 1103 performs the information source decoding process, such as a process (decompression process) for decompressing the compressed information into the output information for the signal for which the transmission line decoding process is performed.

It should be noted that when the signal received through the transmission line by the receiving section 1101 has not been encoded with compression, the information source decoding processing section 1103 does not perform the process of expanding the compressed information into the original information.

Here, as a deployment process is possible, for example, decoding MPEC and so on. Further, the transmission line decoding process sometimes includes descrambling in addition to the decompression process.

In the receiving system implemented as described above, the receiving section 1101 receives a signal obtained by performing compression coding such as MPEC coding for data in the form of, for example, images, audio, and so on, and further performs correction coding errors, such as GORS coding, for compression-encoded data over the transmission line. This signal is fed to the transmission line decoding processing section 1102.

In the transmission line decoding processing section 1102, processes similar to those performed by, for example, the orthogonal demodulation section 51, the reverse mapping section 52, the deinterleaver 53, and the HORS decoding section 56 (or the HORS decoding section 1021) are performed as a transmission line decoding process for the signal from the section 1101 obtaining. Then, the signal obtained as a result of the transmission line decoding process is fed to the information source decoding processing section 1103.

In the information source decoding processing section 1103, an information source decoding process such as MPEC decoding is performed for the signal from the transmission line decoding processing section 1102, and the image or sound obtained as a result of the information decoding process is output.

Such a reception system according to Fig. 107, as described above, can be used, for example, in a television tuner to receive television broadcasts as digital broadcasts, and so on.

It should be noted that it is possible to perform section 1101 of reception, section 1102 of processing decoding of the transmission line and section 1103 of processing decoding of information source each as an independent device (in hardware (in the form of an integrated circuit - IC) or the like) or in the form of a software module.

Next, with respect to receiving section 1101, transmission line decoding processing section 1102, and information source decoding processing section 1103, a set of receiving section 1101 and transmission line decoding processing section 1102, another set of transmission line decoding processing section 1102 and decoding processing section 1103 information source, or another set of receiving section 1101, transmission line decoding processing section 1102, and information source decoding processing section 1103 can be made as a single independent device.

Fig. 108 is a block diagram showing a second embodiment of a receiving system that may be used in the receiving device 12.

It should be noted that in Fig. 108 elements corresponding to the elements in Fig. 107, are designated by the same references, and their description below is omitted where appropriate.

The receiving system according to fig. 108 has that in common with the system in Fig. 107 that it contains a receiving section 1101, a transmission line decoding processing section 1102, and an information source decoding processing section 1103, but different from the system of FIG. 107 in that it reincorporates section 1111 derivation.

The output section 1111 is, for example, a display device for displaying an image or a loudspeaker for outputting sound, and outputs an image, sound or the like as a signal output from the information source decoding processing section 1103. In other words, the output section 1111 displays an image or outputs a sound.

Such a reception system according to Fig. 108, as described above, can be applied, for example, to a television receiver (TM) for receiving television broadcasts as digital broadcasts, to a radio receiver for receiving radio broadcasts, and so on.

It should be noted that when the signal received by the receiving section 1101 is not in a form in which compression coding is not applied, the signal output from the transmission line decoding processing section 1102 is supplied to the output section 1111.

Fig. 109 is a block diagram showing a third embodiment of a receiving system that may be used in the receiving device 12.

It should be noted that in Fig. 109 elements corresponding to the elements in Fig. 148, are marked with the same reference points, and their description below is omitted where appropriate.

The receiving system according to fig. 109 has that in common with the system in Fig. 107 that it contains a receiving section 1101 and a transmission line decoding processing section 1102.

However, the receiving system of Fig. 109 is different from the system in Fig. 107 in that it does not include information source decoding processing section 1103, but again includes recording section 1121.

Recording section 1121 records (stores) a signal (eg, a transport stream packet (TP) or TP

MPEC) output from the transmission line decoding processing section 1102 on or in a recording (storage) medium such as an optical disk, hard disk (magnetic disk) or flash memory.

Such a receiving system according to Fig. 109, as described above, may be applied to a tape recorder for recording television broadcasts or the like.

It should be noted that in Fig. 109 receiving system may contain information source decoding processing section 1103 such that the signal is then processed as an information source decoding processing section by information source decoding processing section 1103, that is, the image or sound obtained by decoding is recorded by recording section 1121.

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Fig. 27 mon in nn mon mon fr fr nn,

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NN nn p NN NN NN NN No NN NN We M p p p p p o o p p

PY py M M OO o i VIC PN NN p p p po r p p i NN NN p p p p p p p ia p PI PN NN S s E p s o p v y -- - nn nn p yn nn na i m chn p sp a p p p p . - Na i NN NN NN p M p p o p p o o A p NN PN M NE s m nn nn p p p p p p p p p p p o o V po PN PN NN S pav - nm nn nn o NN NN NN A pa p PP pa - . Mon nn nn nn p o p M M W p o V NO, o PP NN p - . nn nn nn nn nn NM o p p , NM . yah yuyu yuyu yuyu pv- - . I MK pi NI NN NI NE Re PI pa IN U Esh i I . I-- . RI R Ya Yaz , M SHO SHI NI SHK sons of NZI NNNYA AND WHAT - . . pn nn a n IN M p o A m p NN PN PN PP M YA oo ' pr I NN p p p Y o M A e zo i mo NE NN PP NN PN NE KSO, we nn p p p p p p p pa NA on MON NN KI ZI S pi s KI NO

R - y R - N . I eat as they are not lions as shk n pk I i a p la . pn p nn p NN Ye mi CHIN PI M p r p p p p M A o pov Y y they nin nn p nn sk i a NI AN NK IN I y . Mon nn nn nn nn p p IN po NN R oo po NO NO NO S o NI NK s

I nn p p An NS, m v po I po NE WE WE ARE, th NN S NS: okr z drosh ee m I NN WE NN NOT Z V NE S y

PO NN M NN NN MES; syn i NN KE CE i S s SHIK NI Z I KK NI M NN p NN A NE, ii y I ny NN NN NN NN NN NN NN PI NN, py shyy ZHK Ki i i p I nn nn na a i i p p p kN TEA with NN MM NO. nin nn nn NN, NM p M M A o NN NS, and V NN PN NS nan Ne M a a a M NN p o Ya p NYA. mo NN p nin nn nn NI NNYA, ep NN p p p p S, s E pi Shk YN Ya . nina NA NA NN NN PP PN , os PN M NN NN NN NN PS VS, and KU and

And. Stump Yuyu Yuina I . i nn NN NN n MN A PP PP s p ЧНО tak yuyu yuyu ha yun

Hn PI PP NN NN Ya, piy piy NN NN KN A PP PO V NE na NN E NI PC M PI NT ey

AND

Fig. 32

Yii. her

i - « DECIDED min ny y che R y I yuyu IN NN nan , I - oh GY yayu i ka R NN YN CHI yayu zhk RO aa yich p i yuyu p ne ny i p p o r y SHE huya. -t. - и G Е " B я ke z t - е z е k z z . k g - k y, - ' ch nn nyk i ne R NI shk she NI Sl NE NK ai GI st Yeyuoontn, m ny NNYA p ee koka ya voi "oku oh voi. o. pn i NYA Kokozh i i i i yayu is NIK I NK o ni oyu. p i i R i i PI NN NI an voyzhk RN nn yav shk ny She SHE NE we and Shk NN l. HE NE. yuyu m RY ayu PI i kozh u syuyu" ni i eni ny En i i imi m ly NNYA ni ny p mym nn yuyu sh nik i is NI I U yah shi ny i kyu yuyu g i PISHE ME NI oi GU I MY it shi ny she yayu pi i m nn Kat, PE Re ni ly NE ny chn ya ki shi ny NYA a NI NN pon Ya i a I py cha i el NI yaya- kozh kan SHY sy SHE U she she ny gly ny p nny ly ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny ny j i - ozh SHO "a ch ' g Kl ku lk ia nyk she . shk shih shi gi U yuyu ni NN yayu kish ne gny CY I yuyu i and yuya zhk trick ny chn Ya a i NN z - z Гn - z і- -і- к - є ж . in. - with 4 - t. with a I t I . Nya, osh gnn ki shk she m write nn R

N m ly U HY l SY CHE voy vk oka i h kto kish shk I YAN

Gani t is k - -e is i - I: . - I I - I - I t iv v. y zhoszh z « zh tk is - iz ey z - zh k. , there is also Kk same . with - h I am. t S h a i z - . --e - I m -I- z z ТЯ , - z z . - « i Kk S x GI z KI S m lin - - m ke i-- k Kk is zh - e - k S z zh i zho - Kk i i x. S y " yuka SHE nia pi i i p chn vo i Ko ! and. Oyaetta koi zha fights zho ni chn i how

Pon SHY GO on SHK ryn i p i YN koy vn SHY SHY i Y z ke - mn IN I i i i I we or NI NNYA i NI za shi chn -. . smell RAN rn MN m i NU - and with pi pn i R or poses yuyu yah - - - ah RAN NYA R y bom, pi i sh- An ne yuyu s po shYA yuyu

NI kyu ya she i a NE an i IN lo - Kn boju I WRITE WITH NN U U ni so i i U Ge they SHE i i shik ni i as Genni pi SHIA g she ne y i I NU ne An ne p chn IN kovo v NI R i PISHE NN sny aa p i NO YE YN Ann p syshe y ni i o p i NO NO i ozh. shk shk kyu hmm no no SHY a R y voi p y I yayu ah yuyu

N i nn NE coma M y y y pi i ANYA yayu

N S NE NI go NI we RN ayu oz v s zhi EE

I: nin i PI NE nn R NI p nn NI Kashi pn i NYA kou pi R ni i iv YN NI lan z PK ny nn i g shi i i o NN U RE In: i Pany NI RE A I yuyu R NE WE as what in Fr. . ROSHEN im YN Kot yuyu R I yuyu kyu kyu go sa ne yavu Rosh i U yayu . - tya nn for NK san sanya ROSHEN ki nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie nie

H -- 0. mon nn U YN I they coke. RE NI SY U shin ny ny

And I'm not the only one. g EE R NS NN ny - - z -- Ah z I S ia S is Kk a zh in h GU i ta la ichch t « zh z vyt k oyu in NN EN nn u p nn y Han SHY Sh em oh nn voyzha we ne ni ni ni ne A pi ni -o - chn pe chi pni yuyu im IN CHI -- p nn i RA snuyu Ko zh yuyu y - I kyu GY aa She pn NN NE U SNY lan she SHE - Cat ni chn aa SHY i ni ne ne ozh pe i i . Tue kyu «zh B NNI NI I RN CHYN Gen IN NI yuyu pn NI i R R NN A m PNR MRINNU pi ni i nn i nin ni i tk EE m shi i U SYN ie p i U i "ok NE Plani sh na pen ny or Ya pa SHK NO I. kozh v oyu, and I yuyu tkozh j and kyu ni ny Yezhen Ks SHY shi ni zo zhu - g che BI zhk ye h is t v Gak B. t" zh - Kk g. ' Ye k Go t - t h i is shk nn ny nn U R NE NE MY za SHY and other M NI an g ny NI GE ny SHO Ii. those 5. ha, in Py re M I voy Ge en NN shin ny I'm afraid because I don't know how to do it. sn NI NN SCHI yuyu oyu a nn p ne I vh Mlyn pe I NI nen m ni z i I y m ly yuyu i so NE b PI i g y kzhoozhzhh g NO I

I A NN i i NN A i NN NN p p o i A i z, M a SHY w o v o p p aly she

N PO and our tok pn nn y I lo KU m y U and NN

That's a fight, oh yeah

I - yuyu at zhen oka yuyu gnn NE I pev: K t 1

Fig. 33

IS.

ZitsArlok wattozia sch mya Azov! EVIL TRANSFERERS OO KoMmpochOovi KO PRIYO.

PAT KY LLANIKH g MU i vases zo

TO THE SUBSTITUTE. IF o peo BECOME EMPTY!. pass DYKO 304 ОВ309 goth (RESULT

And | | ! shu, pdok sons | PECODU. dit g nis : hop iz Her DZEKOD

UNTIL THE NEXT, IF 304, rzob Oh, and BATHROOM accessories

RO BECOME EMPTY zo4; A Y shchi K go I GT idekopana" 7 z y ha TYAYE Na | | AH nihdatsikh | X! 3045-. er Ya - day ) days EE VI GO zda, M 0315 0315 m 300 veni 1309,

MATRICES 0301 vv: I pet 302. el ! 309. 300, 2300; 230305 No 307; 0312 SE Azoli i and IDE 3071 i «NV Ncherya dme 3073 3005 3024 605; and from the POWER of BZHEK already 2 YehEMH I live not S u eiKl / in t Geya SHY zucikl and preteyurut nogo vn" as

MNN o vsvu ZM in -e8О 1 shift of the liver ) bddy OZ08 p in VEK zobyttesttya 10. 03033 Zoya vo zoli ob she B3bg 303. M rt» z; 308 302 Zoie and 300; 030050 eddnAs 307 in "7 302 304 7 years 305

Zoya 304 aunt and uncle

Fig. BY

And that, still ZU LERELYANE throne and 12312 And took away ASTUZKO KL! IN; and what is Zoya's ode; od 3, ZY 302 and 05094 5-5 RESULT ийЙ-Т--е | WHAT t Ps pyati DECODE-

LO NEXT. IF 304. nickname. 3077 pi Y "Kozponovty VANCHYA

PES STA Ota GUSTYMI 3042 and -- 2 AXES r olatana TO shi She and on Shk. in went : and ". pet rizi 0316

MATRYN from B-rzo: Kenik VATA «rr et ra . en - C | zp. ev New Balls! 309; 300. ozoo, o moats in 307 0317 in and 30211 Iz fl! 307.

Y - zl: zp. zro VRENNNNIER» Oh melon | Food: 300; rt T da EE 3005 SET and I - Y SUEM 04; we fi | I see the SCHEME

ET EE | | - pickle stte EV | then cycle dawn 2-0 sv se dz ya ZSUVU, 300: PANE t» tr x zha : 0305 Ch ! And : zo I 1 pz EL zi 7, 310. i

OWEN Rovo 10303. 030304 ik 3075 (03 -b8 same M zo; pi 3075)

Passes 30 Eoleee 307 and "le 302 "zl" "tya Go5 7 o306 What is

Fig. 35

702 793 704 705 in and .

ROM RAM HARD DISK

Y 1 ; in h Ann vnch titi;

INPUT/OUTPUT INTERFACE 710 - EN and ZIOMNY p ZHI (the

OUTPUT and RECORD 706 707 708 709

COMPUTER fig. 36 t- VU TOK i tt tt tn

Ї 2094 1813 1548 1295 1460 31985 4207 2481 3369 3451 4620 2622 ї129 1918 2440 2850 1407 1947 37993599 373 971 4358 3108 (5 259 5598 929 2050 864 39968 3835 107 5287 164 3125 2350 1242 3529 іх а199 2147 : 1880) 4896 іх 5854 4910 7 243 147 ' 8 M 1435 7 ORIB7 2517 (b 45065 1002 11 2835 705 52 3425 2285 3 3045 2474 ! 14.1360 1743 00183 2556

ET: 2583 1180 11842 509

G 4813 1005

B 5117 3155 2922 soda obob 19265 42 re 108yu "in

Ssobchav ma! 149 295278 1172384 5 units and: 2 635 688 and 13 231 1684 14 1129 ZVO

TABLETS of the output VALUES of the CHECK MATRIX 2

ON EVENING DE G: 3, M-16200 fig. 37

TABLE OF OUTPUT VALUE OF CHECK MATRIX Z. and . | NA PARNIST DE TZ U, Me 5450

PC sn nn

ИО0 so 6043 506 19826 8065 8296 2767 940 19673 9279 10579 20998

С 17819 8313 0433 0924 5120 5824 12812 17187 9920 13447 13825 18483 2 17507 8074 088: 18529 12754 5915 14576 10970 12054 20437 4455 7151 бо 12777 6193 3079 14538 8189 17749 11343 5556 4373 17434 15477 18537 4 а001 19029 1905 059 16707 2335 6143 3058 14818 17804 20684 5305

O5Oe775 2052 12090 12355 15198 16890 4851 3109 1700 18795 1907 15982

Obavo bit 13745 11537 5591 7433 15297 14145 1483 3887 17431 19430 7 и0бЯ? 14911 11754 4180 8110 5525 12141 157651 18861 15441 10569 8192)

3701 14750 15264 19014 10132 9082 10010 12786 10675 9582 19246 AB 919525 9455

II t4079 4033 19059 12808 831 19494 14160 8949 10223 21504 12395 4329. it 12808 And 13 UZ bba?

Sta 14032 10097 15 0806 1108 : 1 1145 9020 base aa 181048 2100 10 otlota 2iobO o 205 19007

YAR DIVO lu svo IZb40 10048 25 Zb 1omia a m ZavOo be tn Tb784 78 5913 8495 7 RA 10 zi tati vovi z bat 15809 ! frequency 12953 in omio 14boE:

Ho oi7pliV Bob

VZ B7o5 140 sa vno; ' 25 7290 5700 ma arr Ver

UT micron 1905 opening OD ZOV

So? 17040 fig. 38

40 20233 12352 81 19355 19546 42 6249 19030 43 11037 19193 44 19750 11772 45 19844 7425 46 16076 3521 47 11775 21067 іи8 15062 9682 а) вза 5917 5) 11057 3319 о 5118502 4356 02 7994 3999 53 5952 4380 54 7346 11726 п 5182 5609 55 2412 17995 57 9845 20494

I5a 668? 1864 in 20564 5216 (018296 17207 1 9350 5266

С» 7013 ХН5 16255 13437

ID number 15642

Ba o 61505 9078 7 5309 9415 80024 0015 9 1206 16954 14994 1105 (the same v02U 13 14789; 6452

And 14 8002 1859) 14749 14089 (15 253 3045 171274 19956 14775 20 19 15020. 0800

O20 455 7574

Fig. 39

21 18206 9921 22 0131 514 23 10077 9726 24 12045 5479 25 4322 7990 25 156516 5550 27 15561 10681 255681 25 20719 7387 29 2518 18908

IZ 16000 11692:

From 147 10303 117 16550 191 «8 15577 19685 29 17167 20917 40 4955 3391 41 20092 17219 47 9218 5056 45 18429 847? 44 12083 20753 45 16225 12748 16 15025 11095 47 9048 17595 49 19995 4817 ap 164833 3536 50 1439 10145 51 3661 3039 158 18016 g195 G195 G195 G185

Ba KM? 18003 58 5203. 3083 58 10068 51

Be 5695. 7960 and 3559 14630. fig. 40

-y38 10K- set - -- 3 3195 475 4207 1481 1009 2616 1924 3437 554 883 1801

It is 2581 2125 of 3107 4027

OA2837 3373 (7 330 5849 p 125 2050 with 4184 2747 10 p9av 1070 11 2239 984

From 1458 3031 (113009 1375 21137170 5132 3725 4 1817 625 po1t774 47 3839 1257 7 549 3004 3 1015 1945

From 198 412 995 2938 1 4141 1907 3 2430 5079 for? phone 713 1379 5 uv ZO 4 2393 2501

Zno Vb 258 1542

Y 5 t69o 2405 3 1298 188 from VIV M

IV 1848 5112 11 1415 2903 | SH ShY

TABLE OF OUTPUT VALUE OF THE CHECK MATRIX WITH SHLU 0 NAPARNISTDET 4" Me15200

Fig. 41

Table of Outgoing Matrix of Exceeding and Vikh PD Parcel DK GE 2, Mebabio - CC -: - and 63985 7901 14611 13369 11200 3252 5243 92504 9792 6321 13619 12197 14449 15137 13880 1708. 6395 13444 1560 11504 0975 12292 О846 3812 8772 7306 5795 14327 7866 і 7096 11407 14599 9685 1598 2113 10809 9283 1230 15241 4870 2,210 5609 15976 9446 19515 1400 8303 БТІ 14181 13925 7358 с асу во 0:05 7853 7999 15336 5970 10368 10278 9675 4681 7 ай41 5963 9153 2109 19685 7459 12030 12991 629 15917 406 5 6007 8411 5771 3497 БиЗ 14902 875 9188 5235 Т3908 3565 4 32392 0025 4705 548 9781 9071 7312 3399 7250 4939 12655 2820 10058 11090 7069 8585 13134 10158 7183 488 7455 9998 "11905 10918 119 215 7558 13046 10615 11545 4784 7961 15619 ов 3855 9736 4917 15574 5123 2134 15944 14768 7150 2509 1459 3 8310 5820 505 8923 6757 806 7957 49216 15589 13944 2622 14 14463 4852 15733 ЗО41 11195 12860 136073 8152 bbBI 151508 8758

LUNCH 11951 "b 13416 5906 ot 13095 13358 : ! 8 2009 14400 19 7207 4314 ib 3312 3945

Sp kar ba

SS 2599 15975 pi t371 9023 za 1472 2987 bla tati lu 26 6155 13670 27 7430 14559 28 8037 2455 a 595 T2534 ! 5470 3152 31 13317 4305 72 8024 13730 , "3 10975 14182

For 2484 13157 5281 15049 365 1103 1849 57 ?058 1059 8 pob4 5095 ro 14311 7857 fig. 42

40 15617 3146 41 4588 11218 12 13660 5243 43 3578 7874 44 11741 2656

E 1022 1264

SI 12604 9965 2827 2707 (22155 11793 ra osha 114

SloEbT 120 lo7329 pYut 715087 12135

E 5053 470

From 12687 14932 (10 1mB5 1765 11 81211721 12 1245 549 4192 7091 of them 1425 Sh415

I5 9763 7604 16 6.95 11329

G17 1405 12061 18 8055 9057 19 215 8436 201295 14115

AK with 3051 4000 (23 55 1765

KE 2055 14957 5955 6332 and 26 4303 12651 27 11653 12236 (28 19025 7632

Iza 4555 14125 9584 13123

IZ 13997 9597 32 15409 12119 33 0754 15490

E 1416 15395 (26 2509 15549

Fig, 43

О36 2095 2257 (ext. 4791

Zv 1111 4954 29 2912 8571 40 8476 1477 ry 7820 15360

O42 1179 7999 43 2357 3679 44 7703 8216: o 3477 7087 1 Z991 155845 2 7075 12509

And 5 1754 8187

E T5 1400 59213 5891 b 244 703

And 7576 750 8 4921 15092

In 10426 11955 0 1919 904 111332 9264 1211312 3570 13 14916 26550

Y 14 7670 7042 "and 6039 15054

GI6 3939 2751 17 8509 4549 18 12204 8017

C19 5745 12443 120 12013 443 21 1344 Я014

And babb 13850: -23 7730; 14596. 24 14942 7126 18993 965 26 6576 9564 ?0 297 19505 23 13978 5507 130 11857 11185 31 14395 11493 fig. 44

38 10145 12251

From 13467 7425 4 14596 13119

Y zh 2555 11243 30 0465 12690 17 8872 9334 39 15371 14023 39 8101 10187 40 11963 4043 415125 6119 42 93001 14465 15 11135 5107

Name: 14591

Fig, 45 475 1vKA- and t 806 1565 2 2493 184 7 212 3210 8727 1309 is 3498 612 g 2663 1947 230 2695 x 2025 7794 y 059 283 - 862 2859 1071 g 226 285 2

Vb; 2008 t ZOV z542 p 307 1491

ANGLE;

Ro 1800 3280 7 331 2308 th 405 2652

Ia lozv 2479 sch 1583 343 g ba 235

TOOV15 t 1457 2774 and 2118 1555 0722 18534 1 9167 1051 shya chnu | ! t 2253 Зо 4 705 1099 - 2074 243 - 8А0О 945. t 2089 1746 5656 1427 e 3545 1168

TABLE OF OUTPUT VALUE OF CHECK MATRIX a I

NA PARNIST DE Gl, M-16200

Fig. 46

TABLE OF OUTPUT VALUE OF THE CHECK MATRIX sa. 00 muzzles, ME 654800 t.5 Baku Inn Enn Pttatni (019 11219 5575 5360 12559 8108 8505 408 408 10026 T9828 1 5257

From 2659 4304 8350 712 OJSC 3250. 4791 10105. 517 7516 4 12067 1351 11992 197191 112657 5161 537 8165 «048. 29353 5028 7107 2127 3724 5743 11040 10756 4073 1011 59499 5 11259 1215 9526 1466 818 940 3744 2816 11506 11573

Her 7 bass 1507 1118 1274 13751 5207 7854 12803 4047 5484

З вищо а115 0440 413 4455 2989 7915 12402 8579 7052 о 3Б85 0126 5665 4505 9343 963 4707 3742 4186 1556 19 1704 3056 6775 8539 8179 7954 8234 7850 88955 813 1111710 4344 0087 11264 9974 8632 9147 11930 6054 5455 1 7325 3970 10329 2170 8989 3854 2087 12899 9497 11700 13 8218 1467 2490 5841 817 11453 533 11217 11962 5051 (14 1541 4525 79576 3457 9536 7725 3788 2982 6307 5957 11494 2739 4023 12107 8516551 2572 6628 9150. 9952 16 5070 1261 4627 5594 7013 8730 11866 1813 12306 8249 17 12441 5489 8743 7837 7660 2109 11341 2995 6719 11977

I 18 10155 4210 19 10109 10483 (20 8900 10750 21 10245 12978 22 7070 4397 bo tro7i 887 sa 11980 6836 25 09514 4356 7127 10981

G37 11581 2596 (28 1969 11477 29 3044 LLC" 2236 8724

From 9105 6349 and 32 7342 8582

And 35 11675 10405

For VAV 32176

Zb z186 1298 sa 9621 1845 r 486 5611 5 4019 4879 3 2195 For "horn. 47 a 1527 5050 10693 2440

Her bt55 2706

And 7 vii 5909 in 11s43 SCHO35 o adab 4435 4157 9228 11 12970 5562 12 11954 7592

E 1420 9509 14 8210 9536 and 15 609 5430 ate 920 1204 17 1253 119954 5965 015 1 ZT» 7589 4439 4157 21 4002 9555

E 12232 7719

C 1454 8782 24 10749 3969 4252 3479 25 By 5542

C27 2a55 3593 25 12157 7405 29 6508 11495 11805 4455 i 9625 2000 22 4731 27 53 3575 2508

Y 34 9504 1849 4027 1151 ro 5ba? 4955

I aa B) 2 t0965. BEANS 6970 5447 4 3217 bya5b -5 8972 659 5 5818 19472 714657 1280 "in edev 3903

Fig, 48

9 8865 1224. 95371 5979 11 286 4405 125700 7944 13 8059 5934 14 7200 53283 1502 11282 18 19318 2202 17 4523 25 6680 12925 (27 2139 8757

And 28 12004 5948 and 29 8704 3191 8171 10933 31 65297 p.b.

Ia bibe (not t VO. 2096 ! 6 786 3021 7 70 2085 о 8120 4595 1020985 MO 11 6759 10034 12 424 ЦИ in 137 7597

Fig. 49

14 1450112 7955 SHR478 B 0615 7397 17 6590 9316 19 6174 190 255 255 113 21 58197 5835 22 19902 Naya (23 8377 3506 24 5478 8072 455

Ia a 7515 25 2636 28 025 1031

OBOV 5553

"VOV 15 - I- - Piece x 2400 499 1481 908 BBB 716 3270 333 2508 2264 1702 9805 A ZP47 1926 A 414 1224 8 2114 842 7212 575 0 2383 2112 964 166 on 11414 7413 72243 out 0 T245 151 1 775 1655 7 9228 503

I ate. Y g 11574585 7 2 88 1050 5 1231 1950 4 1738 58 5 2399 Z p 163. 545 7 Rbayae 1708 Sho Sho

THE TABLE OF OUTPUT VALUE OF THE PEVEVIRKA MATRIX is

GRAY OF THE OUTPUT VALUE OF THE PEVEVIRKA MATRIX DE g- V, Me«:16200

Fig. 81

Table of expelled value of the Matrix of the Powievka and the smooth detail t. M -64800 -i5.6 VAC Pnunes now with AZB2 415 5900 4155 3218 318 3112 2580 2919 6405 85599 3091 4995 7257 4052 8874 5671 2777 9189 8716 3 8052 4795 3924 3370 10058 1128. 9996 10165 9360 4297 434 5198 4 2379 7834 аб35 2327 9043 804 329 8953 7167 3070. 1528 1 3435 7871 345 53653 1876. 6585 19340 7144 5870 2084 8059 9780 . я 3917 3111 3475 1304 10331 58539 5199: 1611 1991 8959 8316 9950 ії 7 6585 3237 1717 0752 7891 9784 «745: ЗВО 0009 4176 4614 1557 210587 2102 1059 2968 5429 2580 2883 8496 111 8093 1094 44495 с 3780 9555 2074 3321 5057 1450 3840 5444 6572. 3004 9892 1512 8543 1848 10372 4585 7313 65536 6379 1756 9462 2458: 5605 9975

Y 1 8202 10593 7036 3636 3882 For 5969 8561 2395 7289 9267 9979 12 7795 74 1035 9542 6807 73592 6417 7565 10693 795 2581 5115

IZ 7151 2482 4260 5003 0105 7419 9205 6691 8798 2099 8253 3755 14 3800 570 4527 200 9718 6771 1995 800? 5446 768 1103 8520 6304 7691 126 6458 9200 Tast 7295 67956 18 5950 17085 8521 1703 5174 7854 21 9773 1100 22 9517 10768 , !

That's 9290

I VBA6 2041 2 2714 7452 2: 5331 2031

OM min and 1859 2398

I 10450 9774 7 1592 9275 5 10027 "055 o ЗОб4 238

Fig. 52

(10 2640 5087 11 553 5473 12 5002 5682 with oo5 1

Sta 4107 1559 and t15 aBOB 349

B ZIR 8? 17 10192 657 15 5665 3205

C19 3445 1540 20 4706 2097 2 5059 5675 82117 6 and 25 5619 3095 m shAbO shcha

I 25 8255 Z94 (70 vI3B 045 270174 ZNO z) spots 1989 rev VT I A

C 14654 2559

ОВ яли1е зв 3 10595 55 4 122 bi 5300 or? 6 1429 9745 tat and 5 4435 10954

In BI o? on both BY at VA 0558

И 15 во з 13 Fi56 5630

And 14 7067 8878 115 9027 3415 16 1690 2860 17 25054 5469 to 8206 630 32 363 babu 4125 7008 fig. 53

21 1612 6702 22 90659 9298 23 5767 40650 24 3743 9737 25 7018 5572 26 88592 4536 -27 953 60684 23 8069 5993 29

And 7 10576 3240 9 5572 9489 9 3170 57 7869 5731 11 8121 19732 12 4243 9132 13 580 5501 14 5967 9990 3009 2268 16 195 2419 6 1 5571

IV 1010 9195 19 8062 9064 20, 2095 5965 21 753 7326 fe bo8i 3935. !

She is yours. 249303 640

RO 1 264687 302 21 8684 9940 28. 29830 2065 29 7035 1363 0 1769 7837 1 3801 1539

Fig; 54 and lake

But blow ze "PERSON O kom z zdat po a 00 Io te Z pasm 4 194 6090 a Ky po Ob bBoChchuYAV VO i ih 1 me I; and

B AXIS in

І дроумятв ид 7 О7ВЯО очав ни ни EL EL

And grog I te GE ssh YAMI Tv and Ua ANA

About OdalA KAK

M OO MM and Hov oku ru g z

This and oh oh |! "Sh peppery zshchi at

PI

You tsu ps and Mi KU her 5 them, zhk their F 1 2575

Y r i 12 7150 i t

S odido these 18 BIB NO booyash tugu prsche and 15 poh Ya Uk! xx ur ek badobria ZodK

ОО ком : time

In "lapa zi 17 am 10565: and i gozhe Eco KAS ity ba Byach ' tp OoshoAg ba

BM oats! 705 : "uh I I 0 1

Iii A g obr otsov to y ! With che pe | kZ r «i ni FM s KTK NI AJ A / t m zhu ab og: od a 100 9623 o, DNA zdi

EY and I yadonmut bit in and | And ro NN and ! cash price EV ik ory uch

But oh is pul x pose dpa zt o d Mo dizhi sek ue I paro A u gy o u i 1 NI uh 7 shi

Fig. 55

I. and and

TABLE OF THE OUTPUT VALUE OF THE CONVERSION MATRIX. IN

NALPARNISTY DE r, M- 15200 stv; 9 TbK U se 0 1555 712 305 1 1450 5875 1337

From 1741 1129 1184

It is from 294 vob 1565

A 482 605 923 0 925 1579 1777 1274 2 508 151

From 1195 210 4 1484 592

IZ 427 "88 61 825 1123 2 vla 1366 3 1500 255 4 1298 502 0 10065 1701 1 1155 97 2 557 1403 and 1453 524 i 429 1795 o 800 sa5

I 357 151 a 15825 202 3 900 518 4 1401 1039 o 1095 1792 1 1015 14258 2 1281 1584

I 5.b448 1190 (and i477 1945 oblig. 630;

Sas toi 2 aza 098 3 309 577 4 1155 595

Go 631 1000 1732 1368 and 2 1328 329 of 1515 506 ap | sh

Fig. 58

TABLE OF OUTPUT VALUE OF CHECK MATRIX Inc

WAKE WAS SHU, ME 64800 8: AK I PIN 2 0235 2848 3222 and 5500 3492 5243 22757 927 927 90 3 981 4516. 4739 4.1172 3237 6254 1927 2495

In 2429 513 3761; 2508 264 5927 1716 1950 4273 11 4813 6179 3491 12 a865 3286 6005

I3 1343 5923 3529 14 4589 4035 9132 1579 3020 6737 16 1644 1191 5998 71432 9381 4520

From 6791 Bota 6596 9 2733 5918 5736 5 5155 6166 1 1504 4556 2130 1904/3 8027 3187 A BB 759 5 5240 2870 B 2343 1311 T0595 54655 3869: 14 3571 2420 ! b paragraph" 981 collection 2215 4163 17 973 3117 198 8802 6199 19 3794 3948

Fig. 57

(about 2196 0126 1575 1909 2 850 3034 3 5822 1601 sho

Ha 6005 824

BEAN 5783 6172 2032 7875 m 8497 1991 52506 3430 101249 740 11 2944 1945 12 6598 2859 13 2243 3616 14 867 3733 1574 4702 16 428708 3817 28571 3817

C18 1059 4058 19 VI41 3527 at 2138 5066 11206 145 22319 87 /3 3453 1061 (45004 Obi? 5 5837 335 6 58521 4939 7 0306 4756 8 3930 4410 16 4325. 4842

C17 6775 600 s 6500 217 (tv ayu yav (about 3369 ZO

Fig. 58:

3557 3224 2 3028 523 3 3258 440 4 6226 0555 4395 1094 b 1481 69547 74433 1932 (82107 1649

NGO 2119 2006 4005 9385 16720 3622 12 3694 4521 13 1154 0 14 1905 Star 4331 56 18 2970 1798 1798 17 4652 3218 18 1762 4777 89 2543 13 4818 224) (9 4129 4290 10 5325 474 11 2154 5559 12 3703 baht) Her 13 8707 1595 14 1499 325 ! 15 8601 85183 18 6369 4560

And 17 Ya8d6 806

And 7099 6184

О19 6754 7197 о 6353 1951 (73117 6960

Fig. 59

22710 70652 3 1133 3604 (4 3604 657 51355 110 b 3329 8758 72505 3407 8 2452 4900 o 4216 214

And about 6346 5619 11 8627 623 12 9644 5073 13 4212 5068 14 3263 9989 15 5306 478 16 4520 5121 17 3961 1125 ; 15 o. o. 1195

I o5:5R 705

Go 3054 2778 13238 6557 21 6596 3 1457 6226

Y 1446 3085 3907 4043 ge 6839 2373 (71733 5015 3 5202 "obo

OV Zorya 4122 5445 5372 11 370 1825 12 4695 1600 sh

OT tot 6690 r15 2669 1577

One hundred 2483 1681

And OT 18 5728 4984 19 1006 1459

Fig. 60

TABLE OF OUTPUT VALUE OF THE CHECK MATRIX (5. Mm-v6adod

ON PARNISTY DE 10 -k9.10 BAK

And BB11 2563 2900 1 a? IO 5143 4913 2 2451 834 0765 4064 4255 4 1005 2914 5539 5 5539 5 1734 2182 5315 B 3342 56 5329 3179 13 1491 3528 6053 14 1450 10772 5399 2545 1777 43659 516 1334 2145 41653 17 2355 5055 7650 5405

I era 4370 2 3205 1869

From aba4o 5550 2 1354 3021 5117 1713 ob 5425 o255E 7 6047 683

In OB16 Joz 2108 1179 10 953 4921 17 5953 2901 12 1430 4599 13 Bob 450 T4 2250 1846 15 5274 6209 181775 Z476 17 5215 2178 O A165 954 1 A87 651

4 3404 3557 2876 5515 516 1719

And 17 22695 57598 o 5879 2609 1 782 3559 2123 423. 3 4225 2053 4 4296 3517 55531 2184

She was born in 1935 "4560 717 17,

Not 5 3129 1098 10 5239 4440 115722 4124 and 2326 5003

Fig. 82

9 5805 5990 10 4276 1579

And 4407 984

Y 12 1332 5163 13 5359 3975

G14 1907 1854 15 3801 5748 (16 6056 3265

C17 3322 3095

Io 1765. 3244

E 2149 144 2 1559 4291 15154 1252 4 1855 5939 4020 2706 5 1475 3300 7 4256 693 8 4196 2018 9 2103 752 (10 3710 3853 Sh 1 O5123 2 373 931

G13 1939 5002 ! 14 5150 1437 1263 293 16 5049 4565 1? 4548 6380

OO 4590 1 5208 2118 2 6324 5585

IZ 5729 1757 I

T51802 516 ии 51018 3944 7 40195 52885.

From 2257 3007 9 2483 3073 and south to south 6 5329 11 649 3918 12 57 av ,3 obgv 3203

Fig. 53

14 3119 5509 15 4779 431

I5 996 5510 17 4387 4034 0 5835 1692 1 5195 1075 2 M bo 2 3540 7409 4 2225 63485

And 5 1084 1454 B323 4042 11313 5503 2 1303 3450 0 3016 3630 19 5161 2293 11 4682 5545 12 3045 643

And 2403 17277 2 22171514 of 809 716 (4 5155 9553 in Basch

of God 0109 7 52VO 2543 4990 1253 5 5643 1170

Of those 4365, another 1 5561 5358 12 3581 141 5547 001 14 1549 5401 15 5079 2687 16 318 1755 17 3392 1991

Fig. 64

"174 04K: 23506 36098 1140 28859 18148 18510. 8226 540 42014 20879 23802 47088

Іб419 24925 16609 17048 7695 24997 49587 16858 38921 21049 37024 208592 (274 40094 19704 14474 14004 11519 13105 28896 38669 22353 30255 31105 25954 40554 22645 22532 6134 9176 39998 23892 8937 156505 16854 31009 8097 40401 13550 19596 41902 28782 13304 32796 24679 97140 45980 10021 40540 44498 13911 29435 32701 18405 39999 25591 19497 9951 39993 24823 15233 45333 5041 44079 45710 49150 т9415 1892 23121 15850 8839 10308 10458 «442065 3611 1480 37581 32954 13817 6883: 39892 40258 46538. 11940 6705 21634 28150 43757 895 65547 20970 28914 30117 25736 41734 11392 72002 5759 27210 27698 34192 37999 10915 6998 3824 42130 42130 4494 35739 2515

ІБ594 ВЗ2І 20642 45516 32224 26344 9405 18292 12437 27315 35486 41999 5642 5871 46489 26723 23396 7957 8974 3156 37420 44893 35423 1954 42958 32008 419857 38773 26570 2709 27250 46974 1459 20887 97495 38553 22159 24281 8297 19347 9978 27802 34991 6354 33551 29782 20575 29593 0275 48512 14349

And 39091 5167 43978 8548 33179 34410 72535 28511 23950. 20439 4027 24196

ZvBI8 8167 30947 z5538 4880) 21459 7091 45516 15063 5505 9315 21908 36048 32014 11836 7304 397529 33721 15905 29069 12990

PI7B 28709 22460

I ZY541 9937 44000 14035 47316 8815

I5057 45482 24451 chO5iV 38877 879 1583 12954 24332 48 27055 4582. 12083 31378 21870 1159 18031 9921 17028 38715 9550 17343 24543

Fig. 65

16128 31039 32818 20373 35067 19345 16685 20622. 32806

Fig. 66

-K173 CC:: 34903 20927 32093 1052 25611 16093 16454 5520 506 37399 18518. 21120 11036 14594 29158 14753 11650 256529 34379 19878 26898 29935 19750 36058 20179 20029 5457 8157 35554 21237 7943 13879 14980 9912 7143 35911 12043 17360 37253 95589 11827 29159 21996 24195 40870 40701 35035 39555 12356 1997185 29079 165365 35495 92886 11105 8756 34863 19165 15702 135938 40238 4465 40034 40590 37540 17169 1712 20577 14138 31335 19342 9301 39575 3211 1318 33409 28670 12289 5118 29236. 357817 11504 30506 19558 5100 24199 24738 30397 33775 9699 6215 3397 37451 34689 23196 7571 19058 12127 27518 23964 11265 14967 30451 28289 2966 11660 15334 16887 185150 38343 3778 4265 39139 17293 25229 426504 13486 31497 1365 14028 7453 96350 41346 98543 23491 8354 16955 11055 24279

І 15697 124657 13006 5215 41328 23755 20800 8447 7970 2803 33262 39843 5363 22463 38091 98457 ЗББО6 34471 23619 9404 24299 41754 1297 18563. 2673 39070 14480 30279 37483 7580 29519 30519 39931 20252. 18132 20010 34386 7252 27526 12950: 6875 43020 31566 39069 18985 15541 40020 15715 1721 37332 30953 17430 32134 29162. 10490 12971 28581 29331 6489 35383 736 7029 42349 8783 5767 11871 21675 10375 11548 25978 431 24085 1925 10602 28585 12170 15156 34404 9951 13273 90208 5800 15967 21764 16279 37032 34799 21250 34199 7406 41488 19346. 29297 26127 25499 7049 39945 229729 24899 17402 14274 38993 30774 1596585 28459 41404 97749 27425 lair bove 43114 13957 4979 40654 pike 34525 seam 34957 7. baga we 4 /nke 7783 10134

And 41755 30084 29773

And 14515 15503 1545 occupation Z51 39850 4579 33552 533 12991 21137 39508 ! 10244 27261 20417 2939 10172 36479

And 29094 5357 19924 8552 24436 29637

Fig. 67

40177 9325 1350

SYA 21553 42516

DOB 49510 25709 1057 Zhi138 38142 15021 41507 39296

T7560 12205 15245 b Yanbtu 31970 25399 90053 22081 047 0 35208 95854 17073 19995 Goryan 25245 8390 15555 15134 14807 1220: 2804 5035

PIT 121 7056

Which ro BV

Opposite: Jan 24949

And 4107 2959 32194

KOi1A7 r 468 ше 27091 7935 4365 265145 10578 zp Io ZO fig. 68 g2-5 pack

І зцз 10034 28884 947 23050 14484 14809 4968 455 33659 16666 19005 (13172 10930 13354 13719 6132 20088 34040 13442 27958 16813 29619 16553 1499 32075 14962 11578 11204 9217 10485 23069 30936 17899 24904 24855 27490 12056 18007 4957 7285 32073 10038 7159 12486 13483 24808 21759 22391 1059 15520 33521 93030 10645: 26236 19744 21713 36784 ВО16 17859 35597 11120 17948 26180 14729 31943 20416 10000 7882 31380 27859 33356 14125 12131 36199 4058 35902 38594 33698. 15475 1566 18498 12725 7067 17400 8372 35437 2888 1184 30058 25802 11056 5507 26313 32205 37932 5254 5355 17308 22519. 35009 718 5240 16778 23131 94099 20587 33385 2745557

BIV 13645 34501 3393 3840 35227 15562 23615 38342 12139 19471 15483

І2250 5707 23709 379204 95778 21087 и 14588 1000 21854 28375 35591 12514 4655 37190 21379 18723 5802 7182 2579 29936 35880 28338 10835 опо еб010 33026 31017 21259 2165 21807 37578 1175 16710 21939 30841 27292 33730 6836 26476 27539 35784 18245 16394 17939 23004 19916 17432 11655 6153 ЗЕТОВ 28408 35157 17089 13998 36029 15059 15617 5638 36464 5693 28023 28245 9439 11675 95720 96405 5835 31851 25898 8090 37027 24413 27583 7959 35562 37771 17784 11382 11156 37855 7073 21685 34515 10977 13633 30989 7518 11943 18199 5231 13825 19589 23661 11150 35602 от9124 0774 06570 37344 16510 26317 93518 22857 5348 34069 8845 20175 (34085 11441 95668 4116 3019 21049 37308 24551 24727 20104 24850 12114 25137 99527 13108 13085 1425 21477 30807 8613 26241 33368 35913 32477 т002 34320 24641 20556 23007 27305 38947 9691 9122 37805 21554 18585 17237 27292 19033 25790 31795 12152 12184 35088 31226 25263 32386 24092 23114 37895 29796 34335 10551. 36245 25407 175 7203 14654 30201 22605 23404 65295 195295 1952193 29305 1749 lattice 8178 180265 26357 25735 1543 20757 13558 3333 25965 8463 4504 36796 19710 4578 95299 7318 35091 25550 14798

Fig. 69

2224 15 1248 and shoras b3by 17991 s a8932 30240 97073 13082 9192 16206 7129 52069 19619 512 21936 Z8933

K75040 35754 23450 19705 20558 18111

I 22749 27450 39187 2a2iu 31554 30160

Wallpaper WaBo 79009 12BLO 12324 12584 2ob4d 2552 19687 6259 4499 26326 11952 283565 8405

IBOU UBI 7582 10495 2101 20818 roz 36654 21450

MY 92 1532 1205

ZOBI 25469 29153

I 585 11230 34243 20016 35200 13329 br zav 118 ser 11lib 596 52135 11593 19895

ZY 750O OZb5I 0062 22231 10702 12195 21107 21859 4304 21127 4802 souv i0z7 4530 20579 raz 14800

Fig. 70

54 Фя 14502 27561 26909 10919 2534 8597 7903 4635 2530 98130 3093 93930 3651 56 24791 23583 26036 17299 5750 799 9169. 57 511 26154 18653 11551 15447 13695 15264 58 12610 11347 28755 2702 3174 29871 12987 10799 16018 21440 5155 21209 15850 3186 бО 31016 21449 17615 6013 19166 8394 18212 обі 22536 14913 11327 5806 718 11727. 9308 (б2 2001 24941 29966 23634 9013 15587 5444 53 82207 303 16904 28534 21415 27594 25819 (б 29607 4501 29193 14005 14798 16158 5491 85 4520 17094 23397 4264 29370 18041 21526 бб 10490 6192 92970 9597 30841 25954 2762 B7 29120 29120 29855 29870 15147 13688 14959

Maintenance 1262 28039 299888 13083 24053 21951 7963

М б5и 29642 31451 14831 9509 9555 91559. і 72 1355 5454 156533 20354 24508 624 5965 73 19529 995 18011 ЗО80 13961 8039 15393 74 11981 1510 7960 21462 9129 11370 25241 75 0278 29056 4543 30609 20546 21921 28050 (76 15025 25634 5520 31119 13715 21549 196505

Ot 18528 4608 31755 30165 19103 10706. РО2о4

Op.

BO 21355 27777 29919 97000 14897 11409 7122

SVI 29773 2310 263 4877 28629 20545 22095 p2 19605 обо 21964 MO07 14419 22757, 19696 53 30145 1759 10139 29093 26086 10556 5098

VA 18815 16575 7998 24457 96738 6030 5030 505 185 30326 22298 97552

FD 26403 25168 19098 15384 8882 12719 7093 014967 24965 1 3000 100

And 210279 240

Fig.

224102 764 4 12383 4173 poI3rYai 15919 b 21327 1046 7 5285 14579 a 28158 5069 9 165553 110998 10 16561 28303

PRO13980) 24775 12 29169 17989 13 10007 2767 4 21557 VIV 25578 12459 16 7676 8754 17 О1АбО5 20535 15719 28646

NGO Oziooda SU 19975 37197 2 27060 15071 B 8071 26649 23 10395 1176 24 9597 13370 081 17577 26 1433 19513 27 2595

From nBOYA 25291

OZ 17783

Y 33 250694 9345

From T228O 26011 b52b 20122 "AB 95165 11241 37 7686. 26062 38 16290 8480 ! 11774 10120

And 30 30051 30426

In 1335 15824 o ev 17742 43 317790. 17489

E 39120 2100) 14508 6995

Fig. 72

46 979 25024

P47 4554 KBU reports 49 4072 UMBbI 5619 2730 12749 NO 52 29104 505 s 19967 13

Фіг, 73 и бак пня г 22429 10282 11826 19997 11161 2992 3172 99 5625 17064 8279 179 25087 15218 17015 898 20051 75656 4196 11629 22599 17305 29515 5453 11049 22553 25706 14388 5500 19245 8732 2177 13555 11346 17955 3069 (16581 29295 19563 19717 99577 11555 25498 8053 25403 5218 15995 21766 (16509 14287 7043 10715 17449 11119 5679 14155 24213 21000 1118 15620

OBO vbob 16693 143 5535 6518 9482 20189 1066 15013 25361 14043 10506 22296 20912 8952 5421 15691 6126 21595 500 6904 13059 6802

І 8433 4094 9594 14915 3085 19721 25400 8957 23813 9047 25651 15826 (2500 24014 6344 17382 7064 13929 4004 16552 12819 9720 5205 2206 22517 2420 19065 2991 91611 1873 7507 5661 23006 23128 20543 19777 1770 4636 20000 14931 9247 12340 11008 12966 4471 9731 15445 7

Obobuo 14590 18805 29421 22194 19897 9803 25485 7744 18954 11313 9004 19982 23963 18912 7206 19500 4382 90087 6177

І О3065 2400 10019 11087 3746 24325 8060 19826 842 8805 2898 5019 7575 7455 95244 4736 14400 22981 8543 8006 24203 13059 1120 5198 3489 ч270 13059 15895 7453 23747 3556 24585 16542 17507 29462 14670 15527 15290 4198 22748 5842 13395 239185 16985 14999 3796 25350 94157

Overgrowth 16265 16423 13451 16615 8707 24741 3604 25904 8716 9604 20355

Y 2t2o 17245 18445 9862 20831 25326 20517 24619 13289 5099 14183 8804.

Ібапе 17046 15376 18194 25598 1977 8066 21855 14979 12517 4488 17490 400 8135 23575 20979 8476 4084 12935 25596 29309 16582 6402 24350 "боб1Р9 РубОй 198 4761 10443 29530 8607 9752 95446 15053 1955 4040 (377 21160 13474 5451 17170 5935 102585 11972 24910 17833 29047 15108 13075 O0A4B 24546 13150 23867 7309 19798 2988 16958 4825 23950 15125 20526 3553 1153 11595 23360 2452

С4127 2271 17499 15287 29368 21463 7943 15880 5567 8047 23963 8797 (10651 24471 14325. 4081 7258 4949 7044 1078 797 22910 20474. 4318 121374 13231 22085 50965 3821 23718 14178 9978 19030 99594 8895 25358 610 22056 7749 13310 3999 23697 16445 22635 5295 29437 98153 9442 1328 12177 2893 90778 3175 8645 11863 24623 10911 25797 17057 3691 "20473 11204 9914 22815 8439 8439 3699 5431 24540

IB2BA 11275 24953 9347 196557 19190 7957 7174 24819: 2938 9599. 11749

Z607 PubU 13862 1535 23176 8353 2855 17720 2472 7498 573 15036

And 0 198539 19661 1 0502 300

And 9360 Mu

Fig. 74

ИЗ 12290 7028 с ПЯМЕ 13357

OIV 94040 ovo vil 7 187O 10971

In 5229 rush

OT About 150465 20550

NOkhyuyu 2140

ИЗ ЗЕ 1я477

Gas 129 zvo

OA 12254 1383

Г 18 10274 3273 60 9 17 973 VIV ote 4047

One hundred Ib2O 19413 4403 2549

Ol o5B

U» UT Eva 23 tot YATI 24 POT OYAI;

ОВ5 ВК 3725

Sat Mon 27 5742 Call Tue Fri 4285 17542

OO Idbro winter

In OBO I

OZ for B 33 19697 2030

FOR 13001 g3Ib8 and 35 13MO 17528

Зв Яа7Я рубВ7

Oz I 29705 VO38

Gai tva sa63u az 00 99 sah 81911 75713 a I2odo TO 74005 102!

Fig. 75

46 14012 20747 47 11285 15919 48 4073 15531 493 9417 14350 215 5504 51 24864 94590 b? 14443 8815 53 6826 1991 54 8209 20806. 13915 4079 5b 94410 13196 57 13505 17 . . 5 years oob0 2220 50 1570 5044 60 257850 17387 bi 20671 for 62 94558 205914 653 19409 3702 64 8314 1357 55 17014 Зб88

And 57 19837 946 68 15105 12136 69 7750 22805 70 3564 2095. 71 3434 7759

Fig. 76 г174 ОК : бг05 0626 304 7695 4839 4936 1560 144 11203 5567 6347 12557 10601 4959 3059 3734 3071 3494 7687 10313 5954 8059 8295 11090 10775 3613 5908 11177 7676 93549 8746 6583 7239 19255 9674 4992 11859 37085 5981 8718 4908 10550 6805 3334 2627 104851 9285 11120. 7844 3079 0773 3395 10854 5747 1350 12010 12202 689 4241 2343 840 12725 4977

Fig. 77

"1.3 БК с 8009 4156 3216 3112 2560 2919 6405 8593 4969 5723 6912 2978 3011 4339 9312 6396 92957 7988 5485 6031 10218 9226 3575 3263 10029 1114 10008 10147 9384 4990 434 5139 3536 1965 2291 21) бо 7615 7077 743 1941 0716 8215 3840 5140 4582 5420 6110 8551 1515 7404 4879 4946 5383 1831 3441 9569 10472 4306 505 debt 7770 1172 83 5073 zzVrooali 3505 10270 8669 914

ZB obo 9309

Ch950 5Both 4554 4944 9000 9707 so 327 1714 4768 3078 10017 10127 5534 5207

Fig. 78

TIV DEC, today nn o) 4142 8790 583 6720 8071 635 1767 1344 6922 738 6658

ЗБ 1622 3207 415 7019 50923 5608 2605 857 6915 1770 8015 138995 271 8100 2958 8070 7792 1809 1566 6137 8841 886 1931 2105 3721 7577 6810 9322 8226 5396 5867 4428 8827 7766 2954 лат бос 4367 8021 9660 324 5064 4774 297 7859 8405 8953

Oobe3 500 2590 2297 1011 9330 1928 5140 4030 4824 806 3135 1652 BI 1425 2266 6543 2745

ZOV BO 4645 7297 5700 8972 o b597 4429 1709 d276 4041 Zr47 and ZshV3 tat 405 558 nu 186 br t BV odu am VATA 742 chado 1 BNO 2650

Fig. 79 mon nn

CO TR tooth 6354 4001 1059 5045 5158

I YAZ o745 4822 ZAV Z08O 5328 5876 (22 095 5701 269 ZBOU 2438 ZO 3507 (23 2BOz 450) 5577 B32Y toi 4657 4449

G24 5140 2003 1263 4742 BAb) 1185 5200 o 4045 Bodya

I Oovob 20094

Om BV

So what?

SB University Tu 61457 4050

TIN lo; o 4605 Z0gO 24523 fl

Go zorya povo

I'm sorry

Oh, would Pp;

Ha sYai o

Fig. 80 -t3u5 16 - - ше 8765 5713 b295 3598 1374 YVI! 2389 544 3304 9840 4350 77 4951 21 9208 798 1246 0925 355 5739 965 5501 5995 2615 210 4730 5777

AZ 2425 4474 59 1721 796 2997 499 3807 1513 4739 65195 2570 3001 5139 5736 19995889 4962 Z806 4534 5409 6384 5909

And 5516 1622 2006 3295 1257 5797 3816 817 875 2311 3549. 1905

I 424 2121 5415 1705 5849-4095 9333 967 184 1191 3595 6022 2142 ovo 4069 5554 1295 2951 3919 1356 VYE 1786 396. 4738 0 1 2003 1 as

VKEOUULY

OZ Here is the anode

G5 1733 God (6 3196 1936 74992 955 8 5689 3417 (9 265 4878 o aFIO 2247

OR YATI 207 12 30590 203 13 2566 4215

I3 5208 4707 3940 ZOV

STb 5109 4555

Fig. In nya v i:

OLETat75 151 2940 2049 9725 3502 3708 3905 4080 5793 9195

UZ 1SHBYA 1135 18785 2719 3182 3556 5465 5091 610 6114 5597

O160 1749 1251 1526 15656 2129 0929 3095. 3223 2250 4976 4612

And 889 1446 1502 28421 3559 3796 5590 5750 5765 5168 6271 9549 047 1597 2005 2020. 2956 3355 35858 3867 4172 4950 4965 8990 17044 17744

C 1206 2555 3089 share 4027 YOU

Haaroniv, 3206 990 2972 5190 52 76 56 and 129 237 3030 6077 0108 693

Pho 7

OSHSCHYZO diOb 5307 call 5v3ya 5908 3725 3045 40

Pov 2780 330o

OBO 2221 4825 (3033 bobo bNYU 1755 1459 5550 23 Zb74 470 357 1825 5942 3372 5002 «r О1ЯЕ7 и3а8

TE 318 5567 1005 1875 2002

PI schi

Fig. 872

MARKED NUMBERS OF THE ROWS OF THE PEVEVIEKA MATRIX FOR EVENNESS (MATRICES ON INFORMATION

EACH VOLUME IS IDENTIFIED FROM THE STATE OF THE COUNTRY

NUMBERS OF THE PARITY CHECK MATRICES and

THE FIRST STOVYCHIK HE: syu BC NU 1? 125 MO ZIVA ON LO Zb LIA an tka

And | Fail column o On --- ! Only your eV 1407 roYau 3789 i529 ZA I 400 010 ! ! THREE stTOovPCHIK I; -- r ha OOYA 82 SHA ZOZ 3853 107 5281 164 125 20

YUVIysStTOVPchCHIK VAL Yahev sha Zh v, 4 4198 247 Pz. 5 and 5 1880 4836 ! : 5 dv 4910. 23 no. In 011436. 8 2157 25? ; 10 4506 1003 and M 2835 705 : 12 326 2365 and 13 ZV4ya 274

And 14 1385 1743 ; 0 153 2535. 1 5583 180. 2 1542: 503 : Z 418 1005 y y Ba By? and 5 2155 2922 ' There are 347 2696

I I 1725 4296

And in 1580 487

I 9 3925 T640

N b 149 2928. Mo23B4 583 " 12 835 688 ! : 13 M 16

OUTPUT VALUE TABLE 14 1179 3884

PARITY CHECK MATRICES .

Fig. 83 t70-7

S OOBOAM g5ib. 810 BAK cut off | in. Gaia | in B would be bio would

Be | - district

N -- y y х х г, Й п У ! / б / х / уй ХУ and / х more

I H 4 g x sho / rya u

Mr. "A

Yan t vya Uch ch, tia Ty tt stroyah za ok p. A se KOH pudtuk luka Z,

Il sho NK OH pu; bur bu" Su; boo boo boo, boo, boo boo boo boo

Fig. 84

Gret about dnntnnttttrorore s- in Ve ie Ge ih Theo veTveivn ! oe|vyu i in Te | b; | Wow! yin | eat | va wolf | You are Z be E

N i pon zano nen t-- tires pr z pe zhi on I - i and 7 )

I-- Ж a /4 Ж p, u ! ut o, ie ХА . by ; | sleep i i I sho I U / MAX / rock nau sh--

K u: y UK U u U te Ky NYA

VSH nas NM and VN es, bu, bu, r pt. bu ES bu Oh och Yauh bu; was Zu bu, buz bu uz bu Su, bu, ste Suk bu; ZU: fig. 85

TO?AOAM r3.4,576,8y9 10K r374, 575, 9710 BAK fen vasht passe not ex Bena and yah vedery DK zhlomi Dt and KK) in DID KOKO Me mo | You are MV KK. bu; bu; boo boo" boo boo boo boo boo boo boo, boo, boo; bu; buz buz boo, boo boo boo; fig. 86

DOVBOAM g5ib. 8.6 KO ibiB 910 Buck and | I went to university and studied at the university che Bri Tv BUBBLES | B"; My wax k n

SHE g v i naya sny EN pit ve a

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Fig. 87

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Claims (30)

1. A data interleaving device, comprising: a permutation means to perform when a HORS (low density with parity check) code in which the information matrix is that part of its parity check matrix corresponding to the Information bits of the 1ORS code and has a cyclic structure, is transmitted as a symbol or symbols formed by each of two or more code bits, while a symbol is formed from code bits of the GORS code, which are written in a column direction in the storage means for storing the code bits of the GORS code in a row direction and in a column direction and are read in a row direction from said storage medium, interleaving the scrolling of the columns by changing the starting position of the write, when the code bits of the PORS code are to be written in the direction of the column in the said storage means, for each column in the said storage medium, in the role of a permutation process for permuting the code bits of the GORS code . 2. The data processing device according to claim 1, which is characterized in that: the parity matrix in the parity check matrix of the GORS code corresponding to the parity bits of the PORS code has a pseudo-cyclic structure, in which the parity matrix has a section with a cyclic structure except for its part with replacing columns. 3. The data processing device according to claim 2, which is characterized by the fact that: the parity matrix has a step structure, which is transformed into a pseudo-cyclic structure by replacing the columns. 4. The data processing device according to claim 3, which differs in that: the GORS code is a GORS code proposed in the OM B-5.2 standard. 5. The data processing device according to claim 4, which is characterized in that: if t code bits of the GPORS code are converted into one symbol, when the code length for the PORS code is M bits and a predetermined positive integer is represented by b, said storage means stores tb bits in the direction of the row and stores M/(t) bits in the direction of the column, 1 code bits of the GORS code are written in the direction of the column of the mentioned storage medium and read in the direction of the row; tb of code bits read in the direction of the row of the mentioned storage medium are converted into b symbols. 6. The data processing device according to claim 5, which is characterized by the following: parity interleaving means for performing parity interleaving by interleaving the parity bits of the GORS code in the position of other parity bits, while said permutation means interleaves scrolling columns for the GORS code after interspersed parity. 7. The data processing device according to item b, which differs in that: the number of M bits in the parity bits of the GORS code is a value different from simple numbers, and if the two divisors of the number of M bits in the parity bits are different from 1 1 M, the product which is equal to the number of M bits in parity bits, represented by P and a, the number of bits of Information bits of the GPORS code represented by K, an integer equal to or greater than 0 but less than P, represented by x, 1 another integer equal to or greater than 0, but less than d, represented by y, the mentioned parity interleaving means interleaves the (K-ndDx-uchII)-th code bit from the number of parity bits, which are (K--1)-th - (KAM)- and code digits of the GORS code, to the position of the (К-Ру-х--1)-th code digit. 8. The data processing device according to claim 7, which differs in that, if the GORS code is a GORS code with one of 11 different coding rates and a code length M of 64,800 bits, proposed by the OM B-5.2 standard, 1 t of bits is two bits, and the integer B is 1, and in addition, two of the code bits of the PORS code are mapped to two of the four signal points defined in the predetermined modulation method, when said storage means has two columns for storing 2x1 bits in the row direction and stores 64,800/ (2 x 1) bits in the column direction, said permutation means sets, if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an ascending integer, the starting position of the write the first two-column column of said storage medium to the position whose address is 0, 1 sets the starting position of the second two-column entry in the mentioned storage device to the position whose address is 2. 9. The data processing device according to claim 7, which is characterized in that, if the GORS code is a GORS code with one of 11 different coding rates and a code length M with 64,800 bits, which is proposed by the YuU B-5.2 standard, 1 t bits are two bits, and the integer B is 2, and in addition, two of the code bits of the PORS code are displayed in two of the four signal points, defined in a predetermined modulation method, when said storage means has four columns for storing 2x2 bits in the row direction and stores 64,800/(2x2) bits in the column direction, said permutation means determines if the address of the upper position of said storage means in the column direction is represented by 0, and the address of each position of said storage medium in the column direction is represented by an integer specified in ascending order, the starting position of writing the first four-column column of said storage medium to the position whose address is 0 sets the starting position of writing the second four-column column of said of the storage medium to the position whose address is 2 sets the starting position of writing the third column of the four columns of the said storage medium to the position whose address is 4 1 sets the starting position of the writing of the fourth column of the four columns of the said storage medium to the position whose address is 7 . 10. The data processing device according to claim 7, characterized in that, if the GORS code is a GORS code with one of 11 different coding rates and a code length M of 64,800 bits proposed by the U B-5.2 standard, 1 t of bits is four bits , and the integer B is 2, and in addition, four of the code bits of the PORS code are mapped to four of the 16 signal points defined in the predetermined modulation method, when said storage means has eight columns for storing 4x2 bits in the row direction and stores 64,800 /(4x2) bits in the column direction, said permutation means sets, if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an ascending integer, the starting position of the write of the first eight-column column of said storage medium to the position whose address is 0, sets the starting position of writing the second eight-s column columns of said storage medium to a position whose address is 0 sets the starting position of writing the third eight-column column of said storage medium to a position whose address is 2 sets the starting position of writing the fourth eight-column column of said storage medium to a position whose address is 4, sets the write start position of the fifth column of eight columns of said storage medium to the position whose address is 2, sets the write start position of the sixth column of eight columns of said storage medium to the position whose address is 5, sets the write start position of the seventh column of the eight columns of said storage medium to the position whose address is 7, 1 sets the starting position of writing the eighth column of the eight columns of said storage medium to the position whose address is 7. 11. The data processing device according to claim 7, characterized in that, if the GORS code is a GORS code with one of 11 different coding rates and a code length M of 64,800 bits proposed by the OM B-5.2 standard, 1 t of bits is 6 bits , and the integer B is 2, and in addition, six of the code bits of the PORS code are mapped to six of the 64 signal points defined in the predetermined modulation method, when said storage means has twelve columns for storing 6x2 bits in the row direction and stores 64,800/( 6x2) bits in the column direction, said permutation means sets, if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an ascending integer, the starting position of the first column record of the 12 columns of the mentioned storage medium to the position whose address is 0, sets the starting position of writing the second column of the 12 columns of of the given storage medium to the position whose address is 0 sets the starting position of writing the third column of 12 columns of the said storage medium to the position whose address is 2 sets the starting position of writing the fourth column of 12 columns of the said storage medium to the position whose address is 2 , sets the write start position of the fifth column of 12 columns of said storage medium to the position whose address is 3, sets the write start position of the sixth column of 12 columns of said storage medium to the position whose address is 4, sets the write start position of the seventh column of 12 columns of said storage medium to a position whose address is 4 sets the starting position of writing the eighth column of 12 columns of said storage medium to a position whose address is 5 sets the starting position of writing the ninth column of 12 columns of said storage medium to position whose address is 5, sets the starting position writing the tenth column of 12 columns of said storage medium to a position whose address is 7 sets the starting position of writing the eleventh column of 12 columns of said storage medium to a position whose address is 8 1 sets the starting position of writing the twelfth of 12 columns of said storage medium to position whose address is 9. 12. Data processing device according to claim 7, which is characterized in that, if the GORS code is a GORS code with one of 11 different coding rates and a code length M of 64,800 bits proposed by the OM B-5.2 standard, 1 t of bits is 8 bits , and the integer B is 2, and in addition, eight of the code bits of the PORS code are mapped to eight of the 256 signal points defined in the predetermined modulation method, when said storage means has sixteen columns for storing 8x2 bits in the row direction and stores 64,800 /(8x2) bits in the column direction, said permutation means sets, if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an ascending integer, the starting position of the write of the first 16-column column of said storage medium to a position whose address is 0 sets the starting position of the second 16-column write of said storage medium to the position whose address is 2 sets the starting position of writing the third column of 16 columns of said storage medium to the position whose address is 2 sets the starting position of writing the fourth column of 16 columns of said storage medium to the position whose address is 2 , sets the write start position of the fifth column of 16 columns of said storage medium to the position whose address is 2, sets the write start position of the sixth column of 16 columns of said storage medium to the position whose address is 3, sets the write start position of the seventh column of 16 columns of said storage medium to the position whose address is 7 sets the starting position of writing the eighth column of 16 columns of said storage medium to the position whose address is 15 sets the starting position of writing the ninth column of 16 columns of said storage medium to position whose address is 16, sets the starting position sion of writing the tenth column of 16 columns of said storage medium to the position whose address is 20 sets the starting position of writing the eleventh column of 16 columns of said storage medium to the position whose address is 22 sets the starting position of writing the twelfth column of 16 columns of said storage medium to position whose address is 22 sets the starting position of writing the thirteenth column of 16 columns of said storage medium to position whose address is 27 sets the starting position of writing the fourteenth column of 16 columns of said storage medium to position whose address is 27 sets the starting the write position of the fifteenth of the 16 columns of said storage medium to the position whose address is 28, 1 sets the starting position of the write of the sixteenth of the 16 columns of said storage medium to the position whose address is 32. 13. The data processing device according to claim 7, which is characterized in that, if the GORS code is a GORS code with one of 11 different coding rates and a code length M of 64,800 bits proposed by the YuU standard B-5.2, 1 t of bits is 10 bits , and the integer B is 2, and in addition, the code bits of the GORS code are mapped to 10 of the 1024 signal points defined in the predetermined modulation method, when said storage means has twenty columns to store 10x2 bits in the row direction and stores 64,800/ (10x2) bits in the column direction, said permutation means sets, if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an integer specified in ascending order, the starting position of the record of the first column of the 20 columns of said storage medium to the position whose address is 0, 1 sets the starting position of writing the second column of the 20 columns of said th storage medium to a position whose address is equal to 1, sets the starting position of writing the third column of the 20 columns of said storage medium to the position whose address is 3, sets the starting position of writing the fourth column of the 20 columns of said storage medium to the position whose address is 4, sets the starting position of writing the fifth column of the 20 columns of said storage medium to the position whose address is 5, sets the starting position of writing the sixth column of the 20 columns of said storage medium to the position whose address is 6, sets the starting position of writing the seventh column of the 20 columns of said storage medium to the position whose address is 6, sets the starting position of writing the eighth column of the 20 columns of said storage medium to the position whose address is 9, sets the starting position of writing the ninth column of the 20 columns of said storage medium to the position whose address is 13, sets the starting position of writing the tenth column of the 20 columns of said storage medium to the position whose address is 14, sets the starting position of the record of the eleventh column of the 20 columns of said storage medium to the position whose address is 14, sets the starting position of the record of the twelfth column of the 20 columns of said storage medium to the position whose address is 16, sets the starting position of the entry of the thirteenth column of the 20 columns of said storage medium to the position whose address is 21, sets the starting position of the entry of the fourteenth column of the 20 columns of said storage medium to the position whose address is 21, sets the starting position of the record of the fifteenth column of the 20 columns of said storage medium to the position whose address is 23, sets the starting position of writing the sixteenth column of the 20 columns of said storage medium to the position whose address is 25, sets the starting position of the record of the seventeenth of the 20 columns of said storage medium to the position whose address is equal to 25, sets the starting position of the record of the eighteenth column of the 20 columns of said storage medium to the position whose address is 26, sets the starting position of writing the nineteenth column of 20 columns of said storage medium to the position whose address is 28, 1 sets the starting position of writing the twentieth column of 20 columns of said storage medium to the position whose address is 30. 14. The data processing device according to claim 7, which is characterized in that, if the GORS code is a GORS code with one of 11 different coding rates and a code length M of 64,800 bits proposed by the YuU B-5.2 standard, 1 t of bits is 12 bits , and the integer B is 1, and in addition, 12 of the code bits of the GORS code are mapped to 12 of the 4096 signal points defined in the predetermined modulation method, when said storage means has twelve columns for storing 12x1 bits in the row direction and stores 64,800 /(12x1) bits in the column direction, said permutation means sets, if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an ascending integer, the starting position writing the first 12-column column of said storage medium to the position whose address is 0, 1 sets the starting position of writing the second 12-column column of the said storage medium to the position whose address is 0 sets the starting position of writing the third column of 12 columns of the said storage medium to the position whose address is 2 sets the starting position of writing the fourth column of 12 columns of the said storage medium to the position whose address is 2 , sets the write start position of the fifth column of 12 columns of said storage medium to the position whose address is 3, sets the write start position of the sixth column of 12 columns of said storage medium to the position whose address is 4, sets the write start position of the seventh column of 12 columns of said storage medium to a position whose address is 4 sets the starting position of writing the eighth column of 12 columns of said storage medium to a position whose address is 5 sets the starting position of writing the ninth column of 12 columns of said storage medium to position whose address is 5, sets the write start position of the tenth column of 12 columns of said storage medium to the position whose address is 7 sets the write start position of the eleventh column of 12 columns of said storage medium to the position whose address is 8 1 sets the write start position of the twelfth of 12 columns of said storage medium to the position whose address is 9. 15. The data processing device according to claim 7, which is characterized in that, if the GORS code is a GORS code with one of 10 different coding rates and a code length M of 16,200 bits, as proposed by the YuU B-5.2 standard, 1 t of bits is 2 bits , and the integer B is 1, and in addition, two of the code bits of the PORS code are mapped to two of the four signal points defined in the predetermined modulation method, when said storage means has two columns for storing 2x1 bits in the row direction and stores 16,200 /(2x1) bits in the column direction, said permutation means sets, if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an ascending integer, the starting position writing the first two-column column of said storage medium to a position whose address is 0, 1 sets the starting position of writing the second two-column column in the mentioned storage medium to a position whose address is 0. 16. The data processing device according to claim 7, which is characterized in that, if the GORS code is a GORS code with one of 10 different coding rates and a code length M of 16,200 bits, as proposed by the YuU B-5.2 standard, 1 t of bits is 2 bits , and the integer B is 2, and in addition, two of the code bits of the IORS code are mapped to two of the four signal points defined in the predetermined modulation method, when said storage means has four columns for storing 2x2 bits in the row direction and stores 16,200 /(2x2) bits in the column direction, said permutation means sets if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an ascending integer, the write start position of the first four-column column of said storage medium to the position whose address is 0, 1 sets the write start position of the second four-column column of said storage medium to the position whose address is 2, sets the write start position of the third four-column column of said storage medium to the position whose address is 3, 1 sets the starting position of writing the fourth column of the four columns of said storage medium to the position whose address is 3. 17. The data processing device according to claim 7, which is characterized in that, if the GORS code is a GORS code with one of 10 different coding rates and a code length M of 16,200 bits, as proposed by the YuU B-5.2 standard, 1 t of bits is 4 bits , and the integer B is 2, and in addition, four of the code bits of the IORS code are mapped to four of the 16 signal points defined in the predetermined modulation method, when said storage means has eight columns for storing 4x2 bits in the row direction and stores 16,200 /(4x2) bits in the column direction, said permutation means sets, if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an ascending integer, the starting position of the write the first eight-column column of said storage medium to the position whose address is 0, 1 sets the starting position of the second eight-column entry units of said storage medium to a position whose address is 0 sets the starting position of writing the third eight-column column of said storage medium to a position whose address is 0 sets the starting position of writing the fourth eight-column column of said storage medium to a position whose address is 1, sets the write start position of the fifth column of eight columns of said storage medium to the position whose address is 7, sets the write start position of the sixth column of eight columns of said storage medium to the position whose address is 20, sets the write start position of the seventh column of the eight columns of said storage medium to the position whose address is 20, 1 sets the starting position of writing the eighth column of the eight columns of said storage medium to the position whose address is 21. 18. The data processing device according to claim 7, which is characterized in that, if the GORS code is a GORS code with one of 10 different coding rates and a code length M of 16,200 bits proposed by the OM B-5.2 standard, 1 t of bits is 6 bits , and the integer B is 2, and in addition, six of the code bits of the PORS code are mapped to six of the 64 signal points defined in the predetermined modulation method, when said storage means has twelve columns for storing 6x2 bits in the row direction and stores 16,200 /(6x2) bits in the column direction, said permutation means sets, if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an ascending integer, the starting position of the write the first 12-column column of said storage medium to a position whose address is 0, 1 sets the starting position of the second 12-column entry in said storage medium to a position whose address is 0 sets the starting position of writing the third column of 12 columns of said storage medium to a position whose address is 0 sets the starting position of writing the fourth column of 12 columns of said storage medium to position whose address is 2, sets the write start position of the fifth column of 12 columns of said storage medium to the position whose address is 2, sets the write start position of the sixth column of 12 columns of said storage medium to the position whose address is 2, sets the write start position of the seventh column of the 12 columns of said storage medium to the position whose address is 3 sets the starting position of writing the eighth column of the 12 columns of said storage medium to the position whose address is 3 sets the starting position of the writing of the ninth column of the 12 columns of said storage medium to the position , whose address is 3, sets the initial position the recording of the tenth column out of 12 columns of the said storage medium to the position whose address is 6, sets the write start position of the eleventh column of 12 columns of said storage medium to the position whose address is 7, 1 sets the write start position of the twelfth column of 12 columns of said storage medium to the position whose address is 7. 19. The data processing device according to claim 7, which is characterized in that, if the GORS code is a GORS code with one of 10 different coding rates and a code length M of 16,200 bits, as proposed by the YuU B-5.2 standard, 1 t of bits is 8 bits , and the integer B is 1, and in addition, eight of the code bits of the PORS code are mapped to eight of the 256 signal points defined in the predetermined modulation method, when said storage means has 8 columns for storing 8x1 bits in the row direction and stores 16,200/(8x1) bits in the column direction, said permutation means sets, if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an ascending integer, the initial the write position of the first eight-column column of said storage medium to the position whose address is 0, 1 sets the starting position of the second eight-column write in said storage medium to the position whose address is 0 sets the starting position of writing the third eight-column column of said storage medium to the position whose address is 0 sets the starting position of writing the fourth eight-column column of said storage medium to the position whose address is 1, sets the write start position of the fifth column of eight columns of said storage medium to the position whose address is 7, sets the write start position of the sixth column of eight columns of said storage medium to the position whose address is 20, sets the write start position of the seventh column of the eight columns of said storage medium to the position whose address is 20, 1 sets the starting position of writing the eighth column of the eight columns of said storage medium to the position whose address is 21. 20. The data processing device according to claim 7, which is characterized in that, if the GORS code is a GORS code with one of 10 different coding rates and a code length M with 16,200 bits, which is proposed by the OM B-5.2 standard, 1 t bits are 10 bits, and the integer B is 2, and, in addition, of the code bits of the GORS code are mapped to 10 of the 1024 signal points defined in a predetermined modulation method, where said storage means has 20 columns to store 10x2 bits in the row direction and stores 16,200/10x2) bits in the column direction, said permutation means if the address of the top position of said storage in the column direction is represented by 0 and the address of each position of said storage in the direction of the column is represented by an integer in ascending order, the starting position of writing the first column of 20 columns of said storage medium to the position whose address is 0, 1 sets the starting position of writing the second column of 20 columns of said storage medium to the position whose address is 0, sets the starting position of writing the third column of the 20 columns of said storage medium to the position whose address is 0, sets the starting position of writing the fourth column of the 20 columns of said storage medium to the position whose address is 2, sets the starting position of writing the fifth column of the 20 columns of said storage medium to the position whose address is 2, sets the starting position of writing the sixth column of the 20 columns of said storage medium to the position whose address is 2, sets the starting position of writing the seventh column of the 20 columns of said storage medium to the position whose address is 2, sets the starting position of writing the eighth column of the 20 columns of said storage medium to the position whose address is 2, sets the starting position of writing the ninth column of the 20 columns of said storage medium to the position whose address is 5, sets the starting position of writing the tenth column of the 20 columns of said storage medium to the position whose address is 5, set the starting position of the record of the eleventh column of the 20 columns of said storage medium to the position whose address is 5, sets the starting position of the record of the twelfth column of the 20 columns of said storage medium to the position whose address is 5, sets the write start position of the thirteenth column of 20 columns of said storage medium to the position whose address is 5 sets the write start position of the fourteenth column of 20 columns of said storage medium to the position whose address is 7 sets the write start position of the fifteenth column of 20 columns of said storage medium to a position whose address is 7 sets the starting position of writing the sixteenth column of 20 columns of said storage medium to a position whose address is 7 sets the starting position of writing the seventeenth column of 20 columns of said storage medium to a position whose address is 7, sets the write start position of the eighteenth column of 20 columns of said storage medium to the position whose address is 8, sets the write start position of the nineteenth column of 20 columns of said storage medium to the position whose address is 8, 1 sets the write start position of the twentieth Art from the 20 columns of the mentioned storage medium to the position whose address is 10. 21. The data processing device according to claim 7, which is characterized in that, if the GORS code is a GORS code with one of 10 different coding rates and a code length M of 16,200 bits, as proposed by the YuU B-5.2 standard, 1 t of bits is 12 bits , and the integer B is 2, and in addition, 12 of the code bits of the GORS code are mapped to 12 of the 4096 signal points defined in the predetermined modulation method, when said storage means has 24 columns to store 12x2 bits in the row direction and stores 16,200 /12x2) bits in the column direction, said permutation means sets, if the address of the top position of said storage means in the column direction is represented by 0, and the address of each position of said storage means in the column direction is represented by an integer specified in ascending order, the starting position of the entry of the first column of the 24 columns of said storage medium to the position whose address is 0, 1 sets the starting position of the entry of the second column of 24 columns of the said storage entity to the position whose address is 0, sets the starting position of writing the third column of the 24 columns of said storage medium to the position whose address is 0, sets the starting position of writing the fourth column of the 24 columns of said storage medium to the position whose address is 0, sets the starting position of writing the fifth column of the 24 columns of said storage medium to the position whose address is 0, sets the starting position of the record of the sixth column of the 24 columns of said storage medium to the position whose address is 0, sets the starting position of the record of the seventh column of the 24 columns of said storage medium to the position whose address is 0, sets the starting position of writing the eighth column of the 24 columns of said storage medium to the position whose address is 1, sets the starting position of writing the ninth column of the 24 columns of said storage medium to the position whose address is 1, sets the starting position of writing the tenth column of the 24 columns of said storage medium to the position whose address is 1, sets the starting position of the record of the eleventh column of the 24 columns of said storage medium to the position whose address is 2, sets the starting position of the entry of the twelfth column of the 24 columns of said storage medium to the position whose address is 2, sets the starting position of the entry of the thirteenth column of the 24 columns of said storage medium to the position whose address is 2, sets the starting position of the entry of the fourteenth column of the 24 columns of said storage medium to the position whose address is 3, sets the starting position of the record of the fifteenth column of the 24 columns of said storage medium to the position whose address is 7, sets the starting position of writing the sixteenth column of the 24 columns of said storage medium to the position whose address is 9, sets the starting position of the record of the seventeenth column of the 24 columns of said storage medium to the position whose address is 9, sets the starting position of the record of the eighteenth column of the 24 columns of said storage medium to the position whose address is 9, sets the starting position of the record of the nineteenth column of the 24 columns of said storage medium to the position whose address is 10, sets the starting position of the record of the twentieth column of the 24 columns of said storage medium to the position whose address is 10, sets the write start position of the twenty-first column of 24 columns of said storage medium to the position whose address is 10 sets the write start position of the twenty-second column of 24 columns of said storage medium to the position whose address is 10 sets the write start position of the twenty-third column of 24 columns of said storage medium to the position whose address is 10, 1 sets the starting position of writing the twenty-fourth column of the 24 columns of said storage medium to the position whose address is 11. 22. The data processing device according to claim 4, which is characterized by the fact that the GORS code is transmitted after it has been modulated using ОР5К (quadrature phase manipulation), IEOAM (quadrature amplitude modulation), 640OAM, 2560OAM, 10240OAM or 40960OAM. 23. The data processing device according to item b, which is characterized by the fact that the mentioned parity interleaving means and the mentioned permutation means are made jointly with each other. 24. A data processing device which accepts a GORS (low density parity-checked) code transmitted thereto in an interleaved form as a symbol or symbols formed each 13 of two or more code bits, comprising: reverse permutation means to effect, for the GORS code , obtained during the process of permuting the code bits of the GPORS code so that the set of code bits of the GORS code, which correspond to the value И, included in one arbitrary line of the parity check matrix, are not included in the same symbol, the reverse permutation process, which is reverse permutation corresponding to the permutation process; 1 GOYURS decoding means to perform PORS decoding of the GORS code, for which the reverse permutation process is carried out. 25. The data processing device according to claim 24, which is characterized by the fact that the mentioned reverse permutation means performs the reverse permutation process for the GORS code obtained by performing parity interleaving by interleaving the parity bits of the GORS code obtained when performing GORS encoding in accordance with the parity check matrix, in which the parity matrix, which is the section of the GORS code that corresponds to the parity bits of this GORS code, has a step structure, in the position of other parity bits, and then the permutation process is carried out by permuting the code bits of the GORS code so that the set of code bits that correspond to value of AND, included in one arbitrary line of the parity check matrix, are not included in the same symbol, 1 mentioned GORS decoding means carries out ORS decoding of the GORS code for which the reverse permutation process is performed, but parity deinterleaving, which is deinterleaving corresponding to interleaving parity, not implemented, with the help of trans orean parity check matrix obtained by performing at least a column swap corresponding to the parity interleaving for the parity check matrix. 26. A data processing method for a data processing device that accepts a transmitted HORS (low density parity-checked) code in interleaved form as a symbol or symbols formed by each of two or more code bits, comprising: a step performed by the processing device data in order to perform, for the PORS code obtained by carrying out the process of permuting the code bits of the GPORS code so that a set of code bits of the GORS code, which correspond to the value of AND, included in one arbitrary line of the parity check matrix, are not included in the same symbol, the process reverse permutation, which is the reverse permutation corresponding to the permutation process; 1 stage performed by the data processing device to perform the GORS decoding of the GORS code for which the reverse permutation process is performed. 27. A data processing method for a data interleaving data processing device, comprising: a step performed by the data processing device to perform when a HORS (low density parity check) code in which the information matrix that is that part of its verification matrix to the parity corresponding to the Information bits of the GORS code, 1 such that it has a cyclic structure, is transmitted as a symbol or symbols formed by each of two or more code bits, while a symbol is formed from the code bits of the GORS code, which are written in the column direction in storage means for storing code bits of the GORS code in a row direction and in a column direction and read in a row direction from the storage means, interleaving the scrolling of the columns by changing the start position of the write, when the code bits of the GORS code are to be written in a column direction in the storage means, for each column in the storage medium as a permutation process for permuting the code bits of the GORS code. 28. A data processing device that accepts the GORS code (low density with parity control) transmitted to it in an interleaved form as a symbol or symbols formed by each of two or more code bits containing: reverse permutation means to perform when the GORS code is a GORS code in which the information matrix that is that part of its parity check matrix corresponding to the information bits of the GORS code in the parity check matrix of this GORS code has a cyclic structure, 1 character is formed from the code bits of the GORS code, which are written in the column direction in the storage means for storing the code bits of the GORS code in the row direction and in the column direction and read in the row direction from the storage medium, for the PORS code obtained by performing interleaving of the scrolling of the columns by changing the initial recording positions when the code bits of the IORS code are to be written in a column direction in the storage means, for each column in the storage means as a permutation process for permuting the code bits of the GORS code, a reverse permutation process, which is a reverse permutation corresponding to the permutation process; 1 GOYURS decoding means to perform PORS decoding of the GORS code, for which the reverse permutation process is carried out. 29. The data processing device according to claim 28, which is characterized by the fact that the mentioned reverse permutation means performs the reverse permutation process for the GORS code obtained by performing parity interleaving by interleaving the parity bits of the GORS code obtained by performing GORS encoding in accordance with the parity check matrix, in which the parity matrix, which is a section of the GORS code corresponding to the parity bits of this GORS code, has a stair structure, in the position of other parity bits, and then performing a permutation process, 1 said GORS decoding means performs ORS decoding of the GORS code for which the process is carried out reverse permutation, but parity deinterleaving, which is deinterleaving corresponding to parity interleaving, is not performed, using the transformed parity check matrix obtained by performing at least a parity interleaving column swap for the parity check matrix. 30. A data processing method for a data processing device that accepts a transmitted HORS (low density parity-checked) code in interleaved form as a symbol or symbols formed by each of two or more code bits, comprising: a step performed by the processing device data to carry out when the GORS code is a GORS code in which the information matrix, which is that part of its parity check matrix corresponding to the information bits of the GORS code in the parity check matrix of this GORS code, has a cyclic structure, 1 symbol is formed from the code bits of the GORS code, which are written in the column direction in the storage means for storing code bits of the GORS code in the row direction and in the column direction and read in the row direction from the storage means, for the PORS code obtained by interleaving the scrolling of the columns by changing the starting position of the write, when the code bits of the IORS code are to be written in the direction of the column in the storage means, for each column in the storage means as a permutation process to rearrange the code bits of the GORS code, the reverse permutation process, which is the reverse permutation corresponding to the permutation process; 1 stage carried out by the data processing device to perform IORS decoding of the STOR code for which the reverse permutation process is carried out.