TWM679064U - Bridged chip structure for embedded graphene conductive lines - Google Patents

Abstract

This invention provides a bridge chip structure with embedded graphene conductive lines for bridging multiple chips, including a substrate and a bridge layer disposed on the substrate. The bridge layer is a layered structure formed of graphene, and multiple chips are connected to the bridge layer by pins, with the pins of the multiple chips electrically connected to each other along the horizontal direction of the bridge layer. This achieves stable interconnection between two chips and results in faster signal transmission efficiency.

Description

Bridged chip structure for embedded graphene conductive lines

This invention provides a bridging chip structure, and more particularly a bridging chip structure that provides embedded graphene conductive lines for bridging multiple chips.

In most electronic products, bridge chips using Fan-Out Chip on Substrate (FOCoS) technology are better suited to use materials with lower resistivity for their internal conductors. This is because electrical performance values (such as insertion loss) increase or decrease with the resistivity, which depends on the geometry of the conductor, such as its length and cross-sectional area, and is related to manufacturing capabilities, as well as material properties.

As shown in Figure 1, the existing bridge chip package structure PKG typically uses copper (Cu) as the conductor material for its internal bridge circuits, such as circuits P1 and P2. Although copper has good conductivity (resistivity of 1.8 x ^10⁻⁶ Ωcm), using copper as the internal conductor of a bridge chip can easily lead to deformation and breakage due to its thin wire diameter and different coefficient of thermal expansion compared to other materials. Therefore, to keep pace with the increasingly faster signal transmission speeds, existing bridge chips still need improvement in terms of conductor conductivity, heat dissipation, and structural strength.

To solve the above problems, the creators devoted their minds to research and developed a bridging chip structure with embedded graphene conductive lines, which achieves good interconnectivity when bridging two chips.

To achieve the above objectives, this invention provides a bridge chip structure with embedded graphene conductive lines for bridging multiple chips, including a substrate and a bridge layer disposed on the substrate. The bridge layer is a layered structure formed of graphene. The multiple chips are respectively connected to the bridge layer by pins, and the pins of the multiple chips are electrically connected to each other along the horizontal direction of the bridge layer.

In one embodiment, the system further includes multiple vertical conductive layers, each of which is connected to the bridge layer and electrically connected to the bridge layer in a direction perpendicular to the horizontal direction. The pins of the multiple chips are respectively connected to the multiple vertical conductive layers and electrically connected to the bridge layer.

In one embodiment, each of the vertical conductive layers is a carbon nanotube.

In one embodiment, the lattice arrangement direction of each of the vertical conductive layers is substantially perpendicular to the bridge layer.

In one embodiment, multiple channels are recessed in the bridge layer, and multiple vertical conductive layers are respectively disposed at the positions of each channel.

In one embodiment, each of the vertical conductive layers has a contact angle between the channel in which it is located and the bridge connection layer, the contact angle being between 5° and 85°.

In one embodiment, a protective layer is also included, which covers the bridge layer, and each of the channels is recessed in the bridge layer and the protective layer, and each of the vertical conductive layers extends along the channel from the edge of the bridge layer to the location of the pin of each chip on the protective layer.

In one embodiment, each of the vertical conductive layers has a bottom surface that extends along the channel to the protective layer, and each of the vertical conductive layers is electrically connected to the bridging layer within the range of the bottom surface by an electrical connection layer.

In one embodiment, a micropad is further included on each of the vertical conductive layers for connecting the pins of each chip.

In one embodiment, the thickness of the protective layer is between 0.5 μm and 5 μm.

In one embodiment, the thickness of each vertical conductive layer is between 0.5 μm and 5 μm.

In one embodiment, a seed layer is also included, which is disposed on the deposition surface of the substrate, and the bridging layer is disposed on the seed layer.

In one embodiment, the thickness of the seed layer is between 0.1 μm and 0.5 μm.

In one embodiment, an adhesive layer is provided on the back side of the substrate for bonding the bridging wafer structure to the cavity of the carrier.

In one embodiment, the thickness of the bridge layer is between 0.5 μm and 5 μm.

Therefore, the bridge chip structure with embedded graphene conductive lines in this invention, wherein the bridge layer is a layered structure formed by graphene, has a lower resistivity and a higher thermal conductivity than copper under the same geometric shape. In addition, the bonding between carbon atoms in graphene is very stable, so it has better structural strength than copper. It can be used as a bridge chip in fan-out substrate chip packaging technology to achieve stable interconnection between two chips. Compared with copper, it has better electrical performance and can achieve faster signal transmission efficiency.

Furthermore, since each of these vertical conductive layers can be carbon nanotube vias with a resistivity lower than 1.0 x ^10⁻⁶ Ωcm (minimum 0.5 x ^10⁻⁶ Ωcm) and a thermal conductivity greater than 3000 W/m ^· K, it also provides excellent electrical performance in the vertical direction.

To fully understand the purpose, features and effects of this invention, the following specific examples, along with the accompanying drawings, will be used to provide a detailed explanation of this invention, as follows.

The following description, in conjunction with figures and examples, illustrates the specific embodiments of this invention. Through the content described in this specification, those skilled in the art can easily understand the technical problem to be solved and the technical effects that this invention can produce. It is understood that the specific embodiments described herein are merely illustrative and not intended to limit this invention. Furthermore, for ease of description, only the parts relevant to this invention are shown in the figures.

As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

To achieve the above objectives, as shown in Figures 2 to 12, this invention provides a bridging chip structure 100 with embedded graphene conductive lines for bridging multiple chips 200 (see also Figure 3). As shown in Figure 2, which is a first embodiment of this invention, the bridging chip structure 100 includes a substrate 10 and a bridge layer 20 disposed on the substrate 10. The bridge layer 20 is a layered structure formed of graphene. As shown in Figure 3, multiple chips 200 are respectively connected to the bridge layer 20 by pins 201, and the pins 201 of the multiple chips 200 are electrically connected to each other along the horizontal direction X of the bridge layer 20.

As shown in Figures 2-3, in one embodiment, multiple vertical conductive layers 30 are further included. Each vertical conductive layer 30 is connected to a bridge layer 20 and is electrically connected to the bridge layer 20 in a direction perpendicular to the horizontal direction X (as shown in the vertical direction Y in Figure 3). The pins 201 of multiple chips 200 are respectively connected to the multiple vertical conductive layers 30 and electrically connected to the bridge layer 20. In one embodiment, each vertical conductive layer 30 is a carbon nanotube layer, and the lattice arrangement direction of each vertical conductive layer 30 is substantially perpendicular to the bridge layer 20.

As shown in Figures 2-3, in one embodiment, multiple channels 40 (Via) are recessed in the bridge layer 20, and multiple vertical conductive layers 30 are respectively disposed at the positions of each channel 40. In one embodiment, a protective layer 50 (Dielectric Layer) is also included, which covers the bridge layer 20, and each channel 40 is recessed in the bridge layer 20 and the protective layer 50. Each vertical conductive layer 30 extends along its respective channel 40 from the edge of the bridge layer 20 to the position of the pin 201 of each chip 200 on the protective layer 50.

As shown in Figure 2, in one embodiment, each vertical conductive layer 30 has a bottom surface 31 that extends along the channel 40 to the protective layer 50. Each vertical conductive layer 30 is electrically connected to the bridging layer 20 within the area of the bottom surface 31 via an electrical connection layer 32 (catalyst layer). Furthermore, in one embodiment, micropads 21 (μPads) are provided on each vertical conductive layer 30 to connect to the pins 201 of the chip 200.

As shown in Figures 2-3, in one embodiment, a seed layer 60 is also included. The seed layer 60 is disposed on the deposition surface of the substrate 10, and the bridging layer 20 is disposed on the seed layer 60. The thickness of the seed layer 60 is between 0.1 μm and 0.5 μm. As shown in Figure 2, each electrical connection layer 32 is disposed along the bottom surface 31 of the vertical conductive layer 30, and the electrical connection layer 32 contacts the seed layer 60 at the bottom of the channel 40. Thus, the vertical conductive layer 30 can be made in contact with the seed layer 60 within the area of the bottom surface 31 through the electrical connection layer 32.

In one embodiment, an adhesive layer 70 is provided on the back side of the substrate 10 to bond the bridging chip structure 100 to the cavity 301 of the carrier 300 (see FIG3).

As shown in Figure 4, in one embodiment, the thickness GLT of the bridging layer 20 is between 0.5 μm and 5 μm, the edge spacing SBL of the graphene lines is between 20 μm and 200 μm, the distance between the graphene lines and the bottom edge of the vias DBCV is between 0.5 μm and 3 μm, and the thickness of the seed layer 60 is between 0.1 μm and 0.5 μm.

As shown in Figure 4, in one embodiment, the thickness CLT of the vertical conductive layer 30 is between 0.5 μm and 5 μm, and the ratio of the length to the width of the vertical conductive layer 30 other than the thickness CLT is between 100 nm and 10 mm (length) / 100 nm and 10 mm (width). The thickness of the electrical connection layer 32 located on the bottom surface 31 is between 0.1 μm and 0.5 μm. Each vertical conductive layer 30 has a contact angle θ between 5° and 85° in the channel 40 and the bridging layer 20. The vertical conductive layer 30 includes the carbon nanotube conductive region CCZ, which is calculated as thickness GLT x (cot θ), between 0.5 μm and 5 μm.

As shown in Figure 4, in one embodiment, the thickness of the protective layer 50 of the bridging wafer structure 100, BDT, is between 0.5 μm and 5 μm. In one embodiment, the pad extension zone (PEZ) is between 1 μm and 10 μm. In one embodiment, the gap between the wafer 200 and the substrate 10 surface, GBCD, is between 5 μm and 25 μm.

Regarding the fabrication process of the bridge chip structure 100, in one embodiment, as shown in Figures 5A to 5E, the fabrication process includes:

Referring to Figure 5A, as shown in (a), a panel 10A is prepared and a seed layer 60 is formed on the panel 10A; then, as shown in (b), a photoresist PR is applied to the seed layer 60, and photolithography is performed with a photomask of a specific pattern (not shown in the figure); then, as shown in (c), a bridge layer 20 is deposited on the seed layer 60 by physical vapor deposition (PVD); and as shown in (d), chemical etching is performed using photoresist remover to remove the photoresist PR remaining on the panel 10A and the photoresist-covered seed layer 60.

Referring again to Figure 5B, continuing from Figure 5A(d) and as shown in (e), the bridging layer 20 is formed using redistribution layer (RDL) technology; then, as shown in (f), a protective layer 50 is formed on the panel 10A using lamination technology and a thermosetting process; then, as shown in (g), the bridging layer 20 and the protective layer 50 are photolithographically formed using laser light to form a channel 40; then, as shown in (h), an electrical interconnect layer 32 is formed on the surface of the protective layer 50 and the channel 40 by physical vapor deposition.

Referring again to Figure 5C, continuing from Figure 5B(h), as shown in (i), photoresist PR is applied to the protective layer 50 and the channel 40; then, as shown in (j), photolithography is performed with a photomask of a specific pattern (not shown in the figure), and a vertical conductive layer 30 is deposited on the protective layer 50 and the channel 40 by physical vapor deposition (PVD); then, as shown in (k) to (l), chemical etching is performed using photoresist removal to remove the photoresist PR remaining on the protective layer 50 and the electrical connection layer 32 covered by the photoresist PR, thereby forming a vertical conductive layer 30 on the protective layer 50 and the channel 40.

Referring again to Figure 5D, continuing from Figure 5C(l) and as shown in (m), another metal layer 80 is deposited on the protective layer 50 and the vertical conductive layer 30 by physical vapor deposition, and a micro-pad 21 is formed on the vertical conductive layer 30. Then, as shown in (n), photoresist PR is applied to the protective layer 50 and the vertical conductive layer 30; then, as shown in (o), a micro-pad 21 is formed on the protective layer 50 and the vertical conductive layer 30. Photoresist PR is applied to the vertical conductive layer 30, and photolithography is performed on the vertical conductive layer 30 with a photomask of a specific pattern (not shown in the figure), and a micro pad 21 is formed on the metal layer 80 above the vertical conductive layer 30; then, as shown in (p), chemical etching is performed using a photoresist remover to remove the photoresist residue remaining on the protective layer 50 and part of the vertical conductive layer 30, as well as the metal layer 80 covered by the photoresist.

Referring again to Figure 5E, continuing from Figure 5D(p), as shown in (q), the adhesive layer 70 is formed on the back side of the panel 10A; then, as shown in (r), the panel 10A is cut into multiple bridge chip structures 100; finally, as shown in (s), each bridge chip structure 100 can be picked up by a pick-up device and bonded to the cavity 301 of the carrier 300.

Regarding the fabrication process of bonding the bridging chip structure 100 to the cavity 301 of the carrier 300, in one embodiment, as shown in Figures 6A to 6B, the fabrication process includes:

Referring to Figure 6A, as shown in (a), a carrier 300 is prepared. This carrier 300 can be a wafer-level or panel-level substrate. A cavity 301 for bridging the bonding of the chip structure 100 is formed on the carrier 300, and micropads 302 are formed on the surface of the carrier 300 using a redistribution layer technique. Then, as shown in (b), the chip structure 100 is connected to a pickup device. The tool picks up the bridging chip structure 100 into the cavity 301 of the carrier 300, and the bridging chip structure 100 is bonded to the carrier 300 through the adhesive layer 70. Then, as shown in (c), the picking device picks up one of the chips 200 to be bridged (the first chip), each pin 201 of the chip 200 has a microbump 202 (μBump), and the microbump 202 is bonded to the micro pad 302 of the carrier 300 and the micro pad 21 of the bridging chip structure 100 respectively.

Referring again to Figure 6B, continuing from Figure 6A(c) and as shown in (d), another chip 200 to be bridged (the second chip) is picked up by a pickup device, and its microbumps 202 are respectively bonded to the micro pads 302 of the carrier 300 and the micro pads 21 of the bridging chip structure 100, so that the two chips 200 are bridged through the bridging chip structure 100. Then, as shown in (e) to (f), the gap between the chip 200 and the carrier 300 is underfilled by capillary underfill (CUF) technology to complete the process of electrically connecting the two chips 200 through the carrier 300 and the bridging chip structure 100.

Therefore, the bridging chip structure 100 with embedded graphene conductive lines of this invention, wherein the bridging layer 20 is a layered structure formed of graphene, has a lower resistivity than copper under the same geometric shape due to graphene's lower resistivity (less than 0.5 x ^10⁻⁶ Ωcm) and higher thermal conductivity (>5300 W/m·K ^). Furthermore, the bonding between carbon atoms in graphene is very stable, resulting in superior structural strength compared to copper. It can be applied to bridging chips in fan-out substrate chip packaging technology as bridging lines to achieve stable interconnection between two chips 200, and it also exhibits superior electrical performance compared to copper, achieving faster signal transmission efficiency.

Furthermore, since each vertical conductive layer 30 can be a carbon nanotube with a resistivity lower than 1.0 x ^10⁻⁶ Ωcm (minimum 0.5 x ^10⁻⁶ Ωcm) and a thermal conductivity greater than 3000 W/ ^m K, it also provides excellent electrical performance in the vertical direction.

In one embodiment, the non-metallic materials in the packaging structure composed of the aforementioned bridging chip structure 100, chip 200, and carrier 300, such as carrier 300, protective layer 50, adhesive layer 70, and the underfill UF, can be selected from polyimide (PI), epoxy resin, Ajinomoto build-up film (ABF), polypropylene (PP), and/or acrylic resin. Furthermore, the bridging layer 20 and the vertical conductive layer 30 are respectively anisotropic materials. The bridging layer 20, as previously described, is graphene, providing horizontal X-direction conductivity; while the vertical conductive layer 30 is preferably made of carbon nanotubes, providing vertical Y-direction conductivity.

In one embodiment, the carrier 300, the protective layer 50, the adhesive layer 70, and the bottom filler UF and other non-metallic materials may be made of organic photosensitive material, and/or non-photosensitive liquid material, and/or dry-film material.

In one embodiment, the metal materials such as the micropad 21, micropad 302, metal layer 80, seed layer 60, and/or electrical connection layer 32 may be selected from copper (Cu), gold (Au), silver (Ag), aluminum (Al), palladium (Pd), platinum (Pt), and nickel alloys (Ni alloys). Furthermore, the micropads or microbumps of the pin 201 may be selected from deformable materials, such as solder, anisotropic conductive film (ACF), and/or anisotropic conductive paste (ACP).

In one embodiment, the bridging layer 20, vertical conductive layer 30, micropad 21, micropad 302, metal layer 80, seed layer 60, or electrical connection layer 32 may be manufactured using processes selected from physical vapor deposition, electroplating, electroless plating, printing, or potting metal.

As shown in Figure 7, this is a second embodiment of the invention. The main difference between this embodiment and the first embodiment is that the bridging layer 20 and the vertical conductive layer 30 can be applied not only to the bridging chip structure 100, but also to the chip 200 and/or the carrier 300. The substrate of the carrier 300 is, for example, a fan-out substrate.

As shown in Figure 8, this is the third embodiment of the invention. The main difference between this embodiment and the first embodiment is that the bonding method between the microbumps 202 of the pins 201 of the chip 200 and the micropads 21 of the bridging chip structure 100 can be soldering connection and/or metal to metal bonding.

As shown in Figure 9, this is the fourth embodiment of the invention. The main difference between this embodiment and the first embodiment is that when the gap between the wafer 200 and the carrier 300 is filled, in addition to the capillary underfill technique mentioned above, the part of the bridging wafer structure 100 can also be potted and then underfilled with PUF (Potting and then Underfill). The potting is, for example, by pouring liquid resin material (e.g., epoxy resin, silicone or polyurethane) around the bridging wafer structure 100 and then curing it to form a solid protective layer 50.

As shown in Figure 10, this is the fifth embodiment of the invention. The main difference between this embodiment and the first embodiment is that the packaging structure composed of the aforementioned bridging chip structure 100, chip 200 and carrier 300, wherein the bridging chip structure 100 and chip 200 on the carrier 300 can be protected by the aforementioned capillary underfill technology and/or molded underfill (MUF) technology. The molded underfill can be a partial mold as shown in Figure 10(a) or a full mold as shown in Figure 10(b).

As shown in Figure 11, this is the sixth embodiment of the invention. The main difference between this embodiment and the first embodiment is that, in the package structure composed of the aforementioned bridge chip structure 100, chip 200 and carrier 300, in addition to the bottom filler UF on the protective layer 50 being free via as shown in Figure 3, it may also include special vias for heat dissipation. As shown in Figure 11, an electrical isolation interface is provided in the protective layer 50, and the dielectric TC penetrates the material of the bottom filler UF to directly contact the bridge layer 20, and the dielectric TC performs heat conduction.

In the aforementioned embodiments, the carrier 300 can be of different geometric shapes, as shown in Figure 12, for example, a rectangle as shown in (a) or a circle as shown in (b).

The above description is merely a preferred embodiment of this invention and is not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this invention shall be included within the scope of protection of this invention. The scope of protection of this invention shall be determined by the scope of the patent application.

100: Bridged chip structure 200: Chip 201: Pin 202: Microbump 300: Carrier 301: Chamber 302: Micropad 10: Substrate 10A: Panel 20: Bridged layer 21: Micropad 30: Vertical conductive layer 31: Bottom surface 32: Electrical connection layer 40: Channel 50: Protective layer 60: Seed layer 70: Adhesive layer 80: Metal layer X: Horizontal direction Y: Vertical direction BDT: Thickness CCZ: Conductive area CLT: Thickness DBCV: Distance GBCD: Surface clearance GLT: Thickness P1: Circuit P2: Circuit PEZ: Solder pad extension area PKG: Package structure PR: Photoresist PUF: Underfill after potting; SBL: Spacing; TC: Dielectric; UF: Underfill; θ: Contact Angle

Figure 1 is a schematic diagram of the packaging structure of a conventional bridged-chip structure. Figure 2 is a schematic diagram of the individual structure of the bridged-chip structure in Figure 2. Figure 3 is a schematic diagram of the packaging structure of the bridged-chip structure of the first embodiment of this invention. Figure 4 is a diagram showing the dimensional relationship between the components in the packaging structure of Figure 3. Figures 5A-5E are process diagrams of the bridged-chip structure in Figure 2. Figures 6A-6B are process diagrams of the bridged-chip structure in Figure 3. Figure 7 is a schematic diagram of the packaging structure of the bridged-chip structure of the second embodiment of this invention. Figure 8 is a schematic diagram of the packaging structure of the bridged-chip structure of the third embodiment of this invention. Figure 9 is a schematic diagram of the packaging structure of the bridged-chip structure of the fourth embodiment of this invention. Figure 10 is a schematic diagram of the packaging structure of the bridged chip structure according to the fifth embodiment of the present invention. Figure 11 is a schematic diagram of the packaging structure of the bridged chip structure according to the sixth embodiment of the present invention. Figure 12 is a schematic diagram showing that the carrier of the present invention can be of different shapes.

100: Bridged Chip Structure

10:Substrate

20: Bridge Layer

21: Micro-masts

30:Vertical conductive layer

31: Bottom

32: Electrical interconnect layer

40: Channel

50: Protective Layer

60: Seed layer

70: Adhesive layer

80: Metallic layer

X: Horizontal direction

Y: Vertical direction

Claims (15)

A bridge chip structure with embedded graphene conductive lines for bridging multiple chips includes: a substrate; and a bridge layer disposed on the substrate, the bridge layer being a layered structure formed of graphene, the multiple chips being connected to the bridge layer by pins, and the pins of the multiple chips being electrically connected to each other along the horizontal direction of the bridge layer. The bridge chip structure of the embedded graphene conductive lines as described in claim 1 further includes multiple vertical conductive layers, each of which is connected to the bridge layer and electrically connected to the bridge layer in a direction perpendicular to the horizontal direction. The pins of the multiple chips are respectively connected to the multiple vertical conductive layers and electrically connected to the bridge layer. The bridging chip structure of embedded graphene conductive lines as described in claim 2, wherein each of the vertical conductive layers is a carbon nanotube. The bridging wafer structure of the embedded graphene conductive lines as described in claim 2, wherein the lattice arrangement direction of each of the vertical conductive layers is substantially perpendicular to the bridging layer. The bridging chip structure of the embedded graphene conductive lines as described in claim 2, wherein multiple channels are recessed in the bridging layer, and multiple vertical conductive layers are respectively disposed at the positions of each channel. The bridging chip structure of embedded graphene conductive lines as described in claim 5, wherein each of the vertical conductive layers has a contact angle with the bridging layer in the channel in which it is located, the contact angle being between 5° and 85°. The bridging chip structure with embedded graphene conductive lines as described in claim 5 further includes a protective layer covering the bridging layer, and each of the channels is recessed in the bridging layer and the protective layer, and each of the vertical conductive layers extends along the channel from the edge of the bridging layer to the location of the pin of each chip on the protective layer. As described in claim 7, in the bridge chip structure of the embedded graphene conductive lines, each of the vertical conductive layers has a bottom surface that extends along the channel to the protective layer, and each of the vertical conductive layers is electrically connected to the bridge layer within the range of the bottom surface by an electrical connection layer. The bridging chip structure of the embedded graphene conductive lines as described in claim 8 further includes micro-pads disposed on each of the vertical conductive layers for connecting the pins of each chip. The bridging chip structure of the embedded graphene conductive lines as described in claim 7, wherein the thickness of the protective layer is between 0.5 μm and 5 μm. The bridging chip structure of embedded graphene conductive lines as described in claim 2, wherein the thickness of each of the vertical conductive layers is between 0.5 μm and 5 μm. The bridging chip structure of the embedded graphene conductive lines as described in claim 1 further includes a seed layer disposed on the deposition surface of the substrate, and the bridging layer disposed on the seed layer. The bridging wafer structure of embedded graphene conductive lines as described in claim 12, wherein the thickness of the seed layer is between 0.1 μm and 0.5 μm. The bridging chip structure with embedded graphene conductive lines as described in claim 1, wherein an adhesive layer is provided on the back side of the substrate for bonding the bridging chip structure to the cavity of the carrier. The bridging chip structure of the embedded graphene conductive lines as described in claim 1, wherein the thickness of the bridging layer is between 0.5 μm and 5 μm.