TWM651275U - Multi-phase power converter circuit and control circuit thereof - Google Patents

Abstract

The present disclosure provides a multi-phase power converter circuit and a control circuit thereof. The multi-phase power converter circuit receives an input voltage at a voltage input terminal, outputs an output voltage at a voltage output terminal, and includes a power stage circuit and a control circuit. The power stage circuit is coupled to the voltage input terminal, and is coupled to a phase output terminal via an inductor. The control circuit is coupled to the power stage circuit, the phase output terminal and the voltage output terminal, generates an error signal according to a phase current of the phase output terminal, the output voltage and a reference voltage, generates a compensation signal according to the reference voltage and the error signal, generates a ramp signal according to the error signal, and controls the power stage circuit to operate according to a predetermined duty ratio when the ramp signal crosses the compensation signal, so as to increase the phase current.

Description

Multiphase power converter circuit and its control circuit

The present application relates to a control circuit, in particular to a control circuit applied to a multi-phase power converter circuit.

With the development of semiconductor technology, the response ability of multi-phase power converter circuits to load transients has become increasingly important. Some related technologies subtract the output voltage from the reference voltage to obtain an error signal, then convert the error signal into a current signal to charge the capacitor to obtain a sawtooth wave signal, and then compare the sawtooth wave signal with another reference voltage to obtain a pulse wave. Pulse-width modulation (PWM) control signal. However, under the above-mentioned load transient operation, the reference voltage is a certain value, and the sawtooth wave signal is generated by converting the error signal, resulting in a slower response speed and therefore poor transient performance. Therefore, it is necessary to propose new ways to solve the above problems.

One aspect of the present application is a control circuit suitable for a multi-phase power converter circuit. The control circuit includes an error detection circuit, a compensation generation circuit, a slope generation circuit and a comparison circuit. The error detection circuit is coupled to a phase output terminal and a voltage output terminal of the multi-phase power converter circuit, for detecting a phase current of the phase output terminal and an output voltage of the voltage output terminal, and for outputting a correlation An error signal between the phase current, the output voltage and a reference voltage. The compensation generating circuit is coupled to the error detection circuit and used to output a compensation signal according to the error signal and the reference voltage. The slope generating circuit is coupled to the error detection circuit and used to output a slope signal according to the error signal. The comparison circuit is coupled to the compensation generation circuit and the slope generation circuit for receiving the compensation signal and the slope signal, and for generating at least one trigger pulse when the slope signal crosses the compensation signal.

Another aspect of the present application is a multi-phase power converter circuit. The multi-phase power converter circuit is used for receiving an input voltage at a voltage input terminal, for outputting an output voltage at a voltage output terminal, and includes a power stage circuit and a control circuit. The power stage circuit is coupled to the voltage input terminal and coupled to a phase output terminal via an inductor. The control circuit is coupled to the power stage circuit, the phase output terminal and the voltage output terminal, and is used to generate an error signal according to a phase current of the phase output terminal, the output voltage and a reference voltage, to generate an error signal according to the reference voltage. and the error signal generates a compensation signal, used to generate a slope signal based on the error signal, and used to control the power stage circuit to operate according to a preset duty cycle when the slope signal crosses the compensation signal, so that the phase current Increase.

In summary, by using compensation signals and ramp signals that react inversely to changes in output voltage, the control circuit and multi-phase power converter circuit of the present application have advantages such as better load transient response capability compared with related technologies. .

The following is a detailed description of the embodiments together with the accompanying drawings. However, the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operations is not intended to limit the order of execution. Any components Recombining the structure to produce a device with equal functions is within the scope of this application.

Unless otherwise noted, the terms used throughout the specification and patent application generally have their ordinary meanings as used in the field, in the disclosure and in the specific content.

As used herein, “coupling” or “connection” may refer to two or more components that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other. It may also refer to two or more components that are in direct physical or electrical contact with each other. Components interact or act with each other.

Please refer to FIG. 1 , which is a schematic circuit diagram of a multi-phase power converter circuit 100 according to some embodiments of the present application. Specifically, the multi-phase power converter circuit 100 may be, for example, a DC/DC converter such as a multi-phase buck converter. In some embodiments, the multi-phase power converter circuit 100 is used to receive an input voltage VIN at a voltage input terminal NIN, and to output an output voltage VOUT at a voltage output terminal NOUT, for example, a central processing unit (central processing unit). Unit, CPU) and other loads (not shown in the figure) supply power. In Figure 1, a load resistor RL coupled to the voltage output terminal NOUT is the equivalent resistance of the load.

In some embodiments, the multi-phase power converter circuit 100 includes a power stage circuit 10 , a control circuit 20 and an on-time generating circuit 30 . As shown in FIG. 1 , the power stage circuit 10 is electrically coupled to the voltage input terminal NIN. An output terminal NPS of the power stage circuit 10 is coupled to a phase output terminal NPHA through an inductor L, and the phase output terminal NPHA is coupled to the voltage output terminal NOUT. The control circuit 20 is coupled to the phase output terminal NPHA, the voltage output terminal NOUT and the on-time generating circuit 30 , and the on-time generating circuit 30 is coupled to the power stage circuit 10 .

In some embodiments, the power stage circuit 10 includes a driving circuit 11 , a high-side switch 12 and a low-side switch 13 . The high-side switch 12 is coupled between the voltage input terminal NIN (or input voltage VIN) and the output terminal NPS, and the low-side switch 13 is coupled between the output terminal NPS and a ground voltage GND. In other words, the high-side switch 12 and the low-side switch 13 are connected in series between the input voltage VIN and the ground voltage GND. The driving circuit 11 is controlled by a control signal (not shown in the figure), such as a pulse width modulation (PWM) signal, and drives the high-side switch 12 and the low-side switch 12 by a driving signal VGH and a driving signal VGL. The switch 13 is turned on alternately, so that one phase current IL is output from the inductor L. Specifically, each of the high-side switch 12 and the low-side switch 13 can be implemented by a transistor, but the present invention is not limited thereto.

In FIG. 1 , the power stage circuit 10 and the inductor L correspond to one phase of the multi-phase power converter circuit 100 . Although the remaining phases of the multi-phase power converter circuit 100 are not shown in FIG. 1 , it should be understood that the remaining phases of the multi-phase power converter circuit 100 also include a set of power stage circuits and inductors, and the remaining phases The arrangement and operation of the medium power stage circuit and the inductor are similar to those of the power stage circuit 10 and the inductor L in Figure 1, so their description is omitted here. The outputs of all phases in the multi-phase power converter circuit 100 will be summed together at the phase output terminal NPHA to provide an output voltage VOUT at the voltage output terminal NOUT. The sum of all phase outputs in the multi-phase power converter circuit 100 may be, for example, the sum of the phase current IL in FIG. 1 and the phase currents of the other phases. Since the remaining phases of the multi-phase power converter circuit 100 are not shown in Figure 1, in the embodiments described later, the phase current IL in Figure 1 will be used to represent the sum of all phase currents.

In some embodiments, a resistor RCO and a decoupling capacitor CO are connected in series between the phase output terminal NPHA and the voltage output terminal NOUT, and are connected in parallel with the load resistor RL to optimize the multi-phase The ability of the power converter circuit 100 to respond to load transients.

For example, in some practical applications, the load may require a larger operating current due to temporary task changes (such as running specific applications and/or software). That is, the multi-phase power converter circuit 100 needs to increase the number of phases. The magnitude of current IL. Due to some non-ideal factors, the phase current IL cannot immediately increase to the operating current required by the load. At this time, the decoupling capacitor CO electrically coupled to the voltage output terminal NOUT in the multi-phase power converter circuit 100 will be discharged to make up for the lack of phase current IL. However, the discharge of the decoupling capacitor CO causes the output voltage VOUT to undershoot.

In view of this, in some embodiments, the control circuit 20 and the on-time generating circuit 30 are coupled between the voltage output terminal NOUT and the power stage circuit 10 to form a feedback loop. Through this feedback loop, the multi-phase power converter circuit 100 can improve the undershoot phenomenon of the output voltage VOUT. This principle will be further explained in the following paragraphs.

In some embodiments, as shown in FIG. 1 , the control circuit 20 includes an error detection circuit 21 , a compensation generation circuit 22 , a slope generation circuit 23 and a comparison circuit 24 . The error detection circuit 21 is coupled to the phase output terminal NPHA and the voltage output terminal NOUT for detecting the phase current IL and the output voltage VOUT, for receiving a reference voltage VDAC, and for detecting the phase current IL, the output voltage VOUT and the reference voltage VDAC. The voltage VDAC outputs an error signal VERR. It can be seen that the error signal VERR is related to the phase current IL, the output voltage VOUT and the reference voltage VDAC. The compensation generating circuit 22 is coupled to the error detection circuit 21 for receiving the reference voltage VDAC and the error signal VERR, and for outputting a compensation signal VCOMP according to the reference voltage VDAC and the error signal VERR. The slope generating circuit 23 is coupled to the error detection circuit 21 for receiving the error signal VERR, and for outputting a slope signal VRAMP according to the error signal VERR. In addition, the comparison circuit 24 is coupled to the compensation generation circuit 22, the slope generation circuit 23 and the on-time generation circuit 30, for receiving the compensation signal VCOMP and the slope signal VRAMP, and for comparing the compensation signal VCOMP and the slope signal VRAMP.

Following the above description of practical applications, in some embodiments, the output voltage VOUT is significantly reduced due to changes in the load task (that is, the output voltage VOUT undershoots), further affecting the phase current IL, the output voltage VOUT and the reference voltage VDAC. The output error signal VERR. For example, the magnitude (eg, voltage level, etc.) of the error signal VERR will increase. Then, the change in the error signal VERR affects the compensation signal VCOMP and the slope signal VRAMP respectively, causing the magnitude of the compensation signal VCOMP and the magnitude of the slope signal VRAMP to change. Specifically, the ramp signal VRAMP may cross the compensation signal VCOMP at a certain point in time. This part will be further explained in the following paragraphs with Figures 2 and 3. The description of "one signal crossing another signal" herein means that the voltage level of the signal exceeds or is greater than the voltage level of the other signal.

In some embodiments, as shown in FIG. 1 , the comparison circuit 24 generates at least one trigger pulse PTRI to the on-time generating circuit 30 when the ramp signal VRAMP crosses the compensation signal VCOMP. By triggering the trigger pulse PTRI, the on-time generating circuit 30 will, for example, by changing the duty ratio of the aforementioned control signal, control the power stage circuit 10 to operate according to a preset duty ratio to increase the phase current IL. and stabilize the output voltage VOUT.

In some embodiments, the magnitude of the error signal VERR decreases as the phase current IL increases and the output voltage VOUT stabilizes (that is, the undershoot phenomenon of the output voltage VOUT is improved), so that the compensation signal VCOMP may be at a certain time The ramp signal VRAMP is crossed at another time point after the point. In response to the compensation signal VCOMP crossing the ramp signal VRAMP, the comparison circuit 24 stops generating the trigger pulse PTRI to the on-time generating circuit 30, and the on-time generating circuit 30 correspondingly controls the power stage circuit 10 to operate according to an original duty cycle, where this original The duty cycle is lower than the aforementioned preset duty cycle.

As can be seen from the description of the above embodiments, the control circuit 20 is used to generate the error signal VERR based on the phase current IL, the output voltage VOUT and the reference voltage VDAC of the phase output terminal NPHA, and to generate the compensation signal VCOMP based on the reference voltage VDAC and the error signal VERR. used to generate the ramp signal VRAMP according to the error signal VERR, and to trigger the on-time generating circuit 30 to control the power stage circuit 10 to operate according to the preset duty cycle to increase the phase current IL when the ramp signal VRAMP crosses the compensation signal VCOMP. In addition, the control circuit 20 is also used to trigger the on-time generating circuit 30 to control the power stage circuit 10 to operate according to the original duty cycle to reduce the phase current IL when the compensation signal VCOMP crosses the ramp signal VRAMP.

Next, the circuit structure of the error detection circuit 21, the compensation generation circuit 22, the slope generation circuit 23 and the comparison circuit 24 will be explained with reference to Figure 2. Please refer to Figure 2. Figure 2 is a circuit schematic diagram of the control circuit 20 according to some embodiments of the present application.

In the embodiment of FIG. 2 , the error detection circuit 21 includes a resistor 201 , an arithmetic circuit 211 and an arithmetic circuit 221 . In some embodiments, the resistor 201 is coupled to the phase output terminal NPHA of the multi-phase power converter circuit 100 in Figure 1 and is used to generate a conversion voltage VL dependent on the phase current IL, that is, the conversion voltage VL is Dependent power source corresponding to phase current IL. As shown in FIG. 2 , the conversion voltage VL may have a voltage level representing the phase current IL multiplied by a resistance value RI of the resistor 201 . The operation circuit 211 is coupled to the resistor 201 for receiving the conversion voltage VL and the reference voltage VDAC, and for generating a dependent reference voltage VREF according to a difference between the reference voltage VDAC and the conversion voltage VL. Specifically, the dependent reference voltage VREF may have a voltage level equal to the reference voltage VDAC minus the conversion voltage VL. From the description of the conversion voltage VL, it can be seen that the voltage level of the dependent reference voltage VREF is related to the magnitude of the phase current IL. The operation circuit 221 is coupled to the operation circuit 211 for receiving the dependent reference voltage VREF and the output voltage VOUT, and for generating the error signal VERR according to a difference between the dependent reference voltage VREF and the output voltage VOUT. Specifically, the error signal VERR may have a voltage level representing the dependent reference voltage VREF minus the output voltage VOUT. Based on the above, the voltage level of the error signal VERR can be calculated by the following formula (1). …(1)

In the above formula (1), both the resistance value RI and the reference voltage VDAC are preset to fixed values. For example, the resistor value RI is 0.5~4 milliohms, and the reference voltage VDAC is 0~1.52 volts. In addition, the dependent reference voltage VREF is a reference value set for the output voltage VOUT of the multi-phase power converter circuit 100 to follow.

In the embodiment of FIG. 2 , the compensation generating circuit 22 includes an amplifying circuit 202 and an arithmetic circuit 212 . The amplifier circuit 202 is coupled to the error detection circuit 21 for receiving the error signal VERR, and for amplifying the error signal VERR to output an amplified error signal VERRA. The operation circuit 212 is coupled to the amplifier circuit 202 and the comparison circuit 24 for receiving the reference voltage VDAC and the amplified error signal VERRA, and for outputting the compensation signal VCOMP based on a difference between the reference voltage VDAC and the amplified error signal VERRA. Specifically, the compensation signal VCOMP may have a voltage level equal to the reference voltage VDAC minus the amplified error signal VERRA. In the present invention, the error amount (ie, the error signal VERR) is amplified through the amplification circuit 202, and then subtracted from the reference voltage VDAC. In this way, the error amount will quickly react on the compensation signal VCOMP through the amplifier circuit 202 (because the compensation signal VCOMP is not generated through the integrator and the transduction amplifier), allowing the slope signal VRAMP and the compensation signal VCOMP to cross each other faster. Reduce the amount of error (ie, reduce the magnitude of the error signal VERR). Therefore, the overall control loop (for example, the control circuit 20 and the on-time generating circuit 30) will have better transient response.

As can be seen from the description of the compensation generation circuit 22 in Figure 2, in some embodiments, the compensation generation circuit 22 is used to receive the reference voltage VDAC and the error signal VERR, to amplify the error signal VERR, and to generate a signal based on the reference voltage VDAC and the error signal VERR. A calculated value generated by the amplified error signal VERR (that is, the difference between the reference voltage VDAC and the amplified error signal VERRA) outputs the compensation signal VCOMP.

In the embodiment of FIG. 2 , the slope generating circuit 23 includes a capacitor 223 , an integrating circuit 203 and a transconductance amplifier circuit 213 . The integrating circuit 203 is coupled to the error detection circuit 21 for receiving the error signal VERR, integrating the error signal VERR, and outputting an integrated error signal VERRI. The transconduction amplifier circuit 213 is coupled to the integrating circuit 203, the capacitor 223 and the comparison circuit 24, and is used to receive a first power supply voltage VDD, an integrated error signal VERRI and a second power supply voltage VEE, and to convert the integrated error signal VERRI into a The conversion current IERRI is used to charge the capacitor 223 through the conversion current IERRI, thereby outputting the ramp signal VRAMP.

As can be seen from the description of the slope generating circuit 23 in Figure 2, in some embodiments, the slope generating circuit 23 is used to receive the error signal VERR, to perform an operation (that is, an integral operation) on the error signal VERR, and to perform an integral operation on the error signal VERR. The error signal VERR (that is, the integrated error signal VERRI) that performs the operation is converted into voltage and current to output a ramp signal VRAMP.

In the embodiment of FIG. 2 , the comparison circuit 24 includes a comparator 204 and a delay circuit 214 . As shown in Figure 2, the comparator 204 has an inverting input terminal and a non-inverting input terminal. The compensation generating circuit 22 is coupled to the inverting input terminal of the comparator 204 , and the slope generating circuit 23 is coupled to the non-inverting input terminal of the comparator 204 . In other words, the inverting input terminal of the comparator 204 is used to receive the compensation signal VCOMP, and the non-inverting input terminal of the comparator 204 is used to receive the ramp signal VRAMP. Accordingly, the comparator 204 compares the ramp signal VRAMP and the compensation signal VCOMP to output a setting signal SET. In some embodiments, the comparator 204 is used to adjust the voltage level of the setting signal SET according to the comparison result of the ramp signal VRAMP and the compensation signal VCOMP. The delay circuit 214 is coupled to the comparator 204 for receiving the setting signal SET, and for delaying the output of the setting signal SET to output another setting signal SETD.

Next, the relationship between the slope signal VRAMP, the compensation signal VCOMP, the setting signal SET and the setting signal SETD is further explained with Figure 3. Please refer to FIG. 3. FIG. 3 is a timing diagram of some signals in the multi-phase power converter circuit 100 according to some embodiments of the present application.

In some embodiments, as shown in Figure 3, at time T1, the output voltage VOUT decreases due to load task changes. Combining with the aforementioned formula (1), it can be seen that when the phase current IL has not yet increased, the decrease in the output voltage VOUT will cause the voltage level of the error signal VERR to increase. Next, from the above description of the compensation signal VCOMP, it can be known that an increase in the voltage level of the error signal VERR will cause a decrease in the voltage level of the compensation signal VCOMP. Furthermore, as the voltage level of the error signal VERR changes, the voltage level of the ramp signal VRAMP gradually begins to change in a continuous ramp waveform (or continuous triangular waveform, sawtooth waveform, etc.). As can be seen from Figure 3, the compensation signal VCOMP and the ramp signal VRAMP essentially react in opposite ways to the drop of the output voltage VOUT. Accordingly, at time T1, the ramp signal VRAMP crosses (or is greater than) the compensation signal VCOMP.

Following the embodiment in which the comparator 204 adjusts the voltage level of the setting signal SET according to the comparison result of the slope signal VRAMP and the compensation signal VCOMP, as shown in Figure 2, the comparator 204 will set the setting signal when the slope signal VRAMP is greater than the compensation signal VCOMP. The signal SET is adjusted from a first voltage level V1 to a second voltage level V2 higher than the first voltage level V1. In addition, the setting signal SET of the second voltage level V2 is delayed through the delay circuit 214 and outputted at equal time intervals (that is, output as another setting signal SETD) to generate at least one trigger pulse PTRI.

Then, as shown in FIG. 1 , the trigger pulse PTRI triggers the on-time generating circuit 30 to control the power stage circuit 10 to operate according to the preset duty cycle. For example, in some embodiments, the driving circuit 11 in the power stage circuit 10 is controlled by the on-time generating circuit 30 to adjust the driving signal VGH for driving the high-side switch 12 and the driving signal for driving the low-side switch 13 VGL enables the power stage circuit 10 to operate according to the preset duty cycle.

In Figure 3, after time T1, each cycle of the driving signal VGH has an enabling period PE and a disabling period PD. It can be seen from FIG. 3 that the enabling period PE of the driving signal VGH after the time T1 is substantially equal to the enabling period of the driving signal VGH before the time T1 . However, the disabling period PD of the driving signal VGH after the time T1 is significantly shorter than the disabling period of the driving signal VGH before the time T1 . In other words, the duty cycle of the driving signal VGH increases after the time T1 (that is, after the trigger pulse PTRI triggers the on-time generating circuit 30).

In the embodiment of FIG. 3 , the high-side switch 12 turns PE on during the enable period, and turns off (PD) during the disable period. That is to say, after time T1, the high-side switch 12 will frequently turn on and off alternately, which also means that the output of the power stage circuit 10 per unit time will increase. Since the high-side switch 12 and the low-side switch 13 are usually turned on alternately, the operation of the low-side switch 13 can be inferred based on the operation of the high-side switch 12 , so the description of the low-side switch 13 and the driving signal VGL is omitted here.

In summary, the power stage circuit 10 operates according to the preset duty cycle (for example, the enable period PE accounts for the percentage of the enable period PE and the disable period PD), thereby increasing the phase current IL in Figure 1 and causing The output voltage VOUT decreases slowly as shown in Figure 3.

In some embodiments, the phase current IL is substantially close to the operating current required by the load, and the output voltage VOUT is substantially close to the aforementioned dependent reference voltage VREF (that is, the output voltage VOUT is stable, and the undershoot phenomenon of the output voltage VOUT is improved ). The voltage level of the error signal VERR in this case will be significantly smaller than the voltage level of the error signal VERR at time T1. Based on the decrease in the voltage level of the error signal VERR, the voltage level of the compensation signal VCOMP will increase, and the voltage level of the ramp signal VRAMP begins to change from a continuous ramp waveform back to a flat waveform. Accordingly, as shown in Figure 3, at time T2, the compensation signal VCOMP crosses (or is greater than) the ramp signal VRAMP.

It can be seen from the above description of the comparison circuit 24 that as the compensation signal VCOMP crosses the ramp signal VRAMP, the comparator 204 adjusts the setting signal SET from the second voltage level V2 to the first voltage level V1, further causing the delay circuit 214 to output The setting signal SETD is also maintained at the first voltage level V1 (this is equivalent to the trigger pulse PTRI not being generated). It can be seen from this that the comparison circuit 24 stops generating the trigger pulse PTRI when the compensation signal VCOMP crosses the ramp signal VRAMP. Please note that the first voltage level V1 may be a low logic level, and the second voltage level V2 may be a high logic level.

Please refer to FIG. 4. FIG. 4 is a timing diagram of some signals in the multi-phase power converter circuit 100 and some signals in related technologies according to some embodiments of the present application.

Figure 4 shows the compensation signal VCOMP and the ramp signal VRAMP generated by using the circuit structure of the present application, and also shows a ramp signal Vramp and a fixed threshold VTH generated by using the circuit structure of the related technology. As can be seen from Figure 4, compared with the ramp signal Vramp crossing the threshold VTH at time T3 (that is, the ramp signal Vramp crosses the threshold VTH), the compensation signal VCOMP and the ramp signal VRAMP of the present application are earlier than the time T3. The crossover has occurred at time T1 (that is, the ramp signal VRAMP crosses the compensation signal VCOMP). Therefore, as shown in FIG. 4 , the driving signal VGH of the present application generates dense and continuous multiple pulses one step earlier than the driving signal Vgh in the related art (that is, the power stage circuit 10 starts one step earlier with the preset duty cycle). operation).

As can be seen from the above embodiments of the present application, by using the compensation signal VCOMP and the ramp signal VRAMP that react oppositely to changes in the output voltage VOUT, the control circuit 20 and the multi-phase power converter circuit 100 of the present application are better than related technologies. It has the advantages of better load transient response capability.

It should be understood that the multi-phase power converter circuit 100 of the present application is not limited to the circuit architecture shown in FIG. 1 . For example, the on-time generating circuit 30 can be integrated into the control circuit 20 . Accordingly, in some embodiments, the multi-phase power converter circuit 100 includes a power stage circuit 10 and a control circuit 20 . The control circuit 20 is coupled to the power stage circuit 10, the phase output terminal NPHA and the voltage output terminal NOUT. Under this circuit structure, the control circuit 20 will control the power stage circuit 10 to operate according to the preset duty cycle to increase the phase current IL when the ramp signal VRAMP crosses the compensation signal VCOMP.

In addition, it can be seen from the embodiment of FIG. 2 that the comparison circuit 24 includes a comparator 204 and a delay circuit 214, and when the ramp signal VRAMP is greater than the compensation signal VCOMP, the voltage level of the setting signal SETD is changed from the first voltage to the second voltage at equal time intervals. A voltage level V1 is switched to a second voltage level V2 to generate at least one trigger pulse PTRI. However, the present application is not limited to this. For example, the delay circuit 214 can be omitted or integrated into the on-time generating circuit 30 . Accordingly, in some embodiments, the delay circuit 214 is omitted from the comparison circuit 24 in FIG. 2 . Under this circuit structure, when the ramp signal VRAMP crosses the compensation signal VCOMP, the comparison circuit 24 adjusts the setting signal SET from the first voltage level V1 to the second voltage level V2 to generate the trigger pulse PTRI.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention is The scope shall be determined by the appended patent application scope.

10: Power stage circuit 11: Drive circuit 12:High side switch 13: Low side switch 20:Control circuit 21: Error detection circuit 22: Compensation generation circuit 23:Ramp generation circuit 24:Comparison circuit 30: On-time generation circuit 100:Polyphase power converter circuit 201,RCO:Resistor 202: Amplification circuit 203: Integral circuit 204: Comparator 211, 212, 221: Arithmetic circuit 213: Transconduction amplification circuit 214: Delay circuit 223:Capacitor CO: decoupling capacitor GND: ground voltage IERRI: conversion current IL: phase current L:Inductor NIN: voltage input terminal NPHA: Phase output terminal NPS: output NOUT: voltage output terminal PD: period of disablement PE: enabling period PTRI: trigger pulse RI: resistance value RL: load resistor SET, SETD: setting signal T1, T2, T3: time V1: first voltage level V2: second voltage level VCOMP: compensation signal VDAC: reference voltage VDD: first power supply voltage VEE: second power supply voltage VERR: error signal VERRA: Amplify error signal VERRI: Integral error signal VGH, VGL, Vgh: drive signal VIN: input voltage VL: conversion voltage VOUT: output voltage VRAMP, Vramp: ramp signal VREF: dependent reference voltage VTH: threshold value

Figure 1 is a circuit schematic diagram of a multi-phase power converter circuit according to some embodiments of the present application. Figure 2 is a circuit schematic diagram of a control circuit according to some embodiments of the present application. Figure 3 is a timing diagram of some signals in a multi-phase power converter circuit according to some embodiments of the present application. Figure 4 is a timing diagram of some signals in a multi-phase power converter circuit and some signals in related technologies according to some embodiments of the present application.

10: Power stage circuit

11: Drive circuit

12: High side switch

13: Low side switch

20:Control circuit

21: Error detection circuit

22: Compensation generation circuit

23:Ramp generation circuit

24:Comparison circuit

30: On-time generation circuit

100:Polyphase power converter circuit

RCO: resistor

CO: decoupling capacitor

GND: ground voltage

IL: phase current

L:Inductor

NIN: voltage input terminal

NPHA: Phase output terminal

NPS: output

NOUT: voltage output terminal

PTRI: trigger pulse

RL: load resistor

VCOMP: compensation signal

VDAC: reference voltage

VERR: error signal

VGH, VGL: drive signal

VIN: input voltage

VOUT: output voltage

VRAMP: ramp signal

Claims (10)

A control circuit adapted to a multi-phase power converter circuit and comprising: An error detection circuit, coupled to a phase output terminal and a voltage output terminal of the multi-phase power converter circuit, is used to detect a phase current of the phase output terminal and an output voltage of the voltage output terminal, and to output an error signal associated with the phase current, the output voltage and a reference voltage; a compensation generating circuit coupled to the error detection circuit and used to output a compensation signal based on the error signal and the reference voltage; a slope generating circuit coupled to the error detection circuit and used to output a slope signal based on the error signal: and A comparison circuit is coupled to the compensation generation circuit and the slope generation circuit for receiving the compensation signal and the slope signal, and for generating at least one trigger pulse when the slope signal crosses the compensation signal. The control circuit as described in claim 1, wherein the compensation generating circuit includes: an amplifier circuit coupled to the error detection circuit for receiving the error signal and amplifying the error signal to output an amplified error signal; and An operation circuit is coupled to the amplification circuit and the comparison circuit for receiving the reference voltage and the amplified error signal, and for outputting the compensation signal based on a difference between the reference voltage and the amplified error signal. The control circuit as described in claim 1, wherein the slope generating circuit includes: a capacitor; An integrating circuit coupled to the error detection circuit for receiving the error signal and integrating the error signal to output an integrated error signal; and A transconductance amplifier circuit, coupled to the integrating circuit, the capacitor and the comparison circuit, is used to receive the integrated error signal, and to convert the integrated error signal into a conversion current to charge the capacitor through the conversion current. , thereby outputting the slope signal. The control circuit as described in claim 1, wherein the comparison circuit is used to output a setting signal and adjust the voltage level of the setting signal based on the compensation signal and the error signal, wherein the comparison circuit is used when the slope signal is greater than When compensating the signal, the voltage level of the setting signal is switched from a first voltage level to a second voltage level at equal time intervals to generate the at least one trigger pulse. The control circuit as described in claim 1, wherein the comparison circuit includes: A comparator for outputting a setting signal for comparing the slope signal and the compensation signal, and for adjusting the voltage level of the setting signal based on the comparison result of the slope signal and the compensation signal, wherein the comparator is When the ramp signal is greater than the compensation signal, the setting signal is adjusted from a first voltage level to a second voltage level; and A delay circuit is coupled to the comparator and used to output the setting signal of the second voltage level at equal time intervals to generate the at least one trigger pulse. The control circuit as described in claim 1, wherein the error detection circuit includes: a resistor coupled to the phase output end of the multi-phase power converter circuit and used to generate a conversion voltage dependent on the phase current; a first operation circuit coupled to the resistor for receiving the conversion voltage and the reference voltage, and for generating a dependent reference voltage based on a difference between the reference voltage and the conversion voltage; and A second operation circuit is coupled to the first operation circuit for receiving the dependent reference voltage and the output voltage, and for generating the error signal based on a difference between the dependent reference voltage and the output voltage. The control circuit as claimed in claim 1, wherein the multi-phase power converter circuit includes a conduction time generating circuit and a power stage circuit, and the at least one trigger pulse is used to trigger the conduction time generating circuit to control the power stage circuit according to A preset duty cycle operation. A multi-phase power converter circuit is used for receiving an input voltage at a voltage input terminal and for outputting an output voltage at a voltage output terminal, and includes: a power stage circuit coupled to the voltage input terminal and coupled to a phase output terminal via an inductor; and A control circuit, coupled to the power stage circuit, the phase output terminal and the voltage output terminal, is used to generate an error signal based on a phase current of the phase output terminal, the output voltage and a reference voltage, and is used to generate an error signal according to the reference voltage. The voltage and the error signal generate a compensation signal, which is used to generate a slope signal according to the error signal, and is used to control the power stage circuit to operate according to a preset duty cycle when the slope signal crosses the compensation signal, so that the phase The current increases. The multi-phase power converter circuit as claimed in claim 8, wherein the control circuit includes: An error detection circuit, coupled to the phase output terminal and the voltage output terminal, is used to detect the phase current and the output voltage, and is used to output the error associated with the phase current, the output voltage and the reference voltage. signal; a compensation generating circuit coupled to the error detection circuit for amplifying the error signal and outputting the compensation signal based on a calculated value based on the reference voltage and the amplified error signal; A slope generating circuit, coupled to the error detection circuit, is used to perform calculations on the error signal, and is used to perform voltage-current conversion on the calculated error signal to output the slope signal; and A comparison circuit is coupled to the compensation generation circuit and the slope generation circuit for receiving the compensation signal and the slope signal, and for generating at least one trigger pulse when the slope signal is greater than the compensation signal. The multi-phase power converter circuit as described in claim 9, wherein the control circuit further includes: An on-time generating circuit is coupled between the comparison circuit and the power stage circuit, and is used to control the power stage circuit to operate according to the preset duty cycle by being triggered by the at least one trigger pulse.

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