TWM651267U - Signal delay setting circuit, isolation integrated circuit and power conversion circuitry - Google Patents

Abstract

The present disclosure provides signal delay setting circuit, isolation integrated circuit and power conversion circuitry. The signal delay setting circuit is applicable to the isolation integrated circuit. The isolation integrated circuit receives a first power voltage via a first power terminal, receives a first input signal and a second input signal via two signal input terminals respectively, and outputs an output signal generated according to the first input signal and the second input signal via a signal output terminal. When the first power voltage is within a predetermined voltage range, the signal delay setting circuit generates a voltage difference across the two signal input terminals and calculates a delay time according to the voltage difference. When the first power voltage is greater than an upper range value of the predetermined voltage range, the signal delay setting circuit delays the first input signal or the second input signal to control the duty ratio of the output signal.

Description

Signal delay setting circuit, isolated integrated circuit and power conversion circuit system

The present application relates to a signal delay setting circuit, and in particular, to a signal delay setting circuit applied to an isolated integrated circuit.

In a circuit structure composed of a high-side switch and a low-side switch, the high-side switch and the low-side switch usually need to be turned on alternately to complete the operation. However, the high-side switch and the low-side switch may be turned on at the same time due to some non-ideal factors, which may cause the high-side switch and the low-side switch to be damaged due to the flow of large current.

Some related technologies ensure that the high-side switch and the low-side switch are not turned on at the same time by using resistor-capacitor circuit (RC circuit) settings or using trim methods to generate dead time or dead time. Each has its own problems. For example, the dead time generated by related technologies using resistor-capacitor circuits may have higher deviations due to the physical characteristics of the resistors and/or capacitors. For another example, the use of fine-tuning related techniques may increase the complexity of the entire system. Therefore, it is necessary to propose new ways to solve the above problems.

One aspect of the present application is a signal delay setting circuit suitable for an isolated integrated circuit. The isolated integrated circuit includes a first signal input terminal, a second signal input terminal and a signal output terminal. The first signal input terminal is used to receive the first input signal, the second signal input terminal is used to receive the second input signal, and the signal The output terminal is used to output an output signal generated according to the first input signal and the second input signal. The signal delay setting circuit includes a voltage drop generating circuit, a delay time control circuit and a signal delay circuit. The voltage drop generating circuit is used to generate a voltage difference between the first signal input terminal and the second signal input terminal. The delay time control circuit is coupled to the voltage drop generating circuit, and is used to enable the voltage drop generating circuit to generate a voltage difference when the first power supply voltage is within a preset voltage range, and to calculate the delay time based on the voltage difference, wherein the isolated product The body circuit also includes a first power terminal, and the first power terminal is used to receive the first power voltage. The signal delay circuit is coupled to the delay time control circuit and is used to delay one of the first input signal and the second input signal according to the delay time to control the output when the first power supply voltage is greater than the upper limit of the preset voltage range. The duty cycle of the signal.

One aspect of the present application is an isolated integrated circuit. The isolated integrated circuit includes a primary side circuit, an isolation circuit, a secondary side circuit and a signal delay setting circuit. The primary side circuit is used to receive the first power supply voltage through the first power terminal, to receive the first input signal through the first signal input terminal, to receive the second input signal through the second signal input terminal, and to receive the first input signal according to the first input terminal. signal and the second input signal to produce an intermediate signal. The isolation circuit is coupled to the primary circuit and used to transmit intermediate signals. The secondary side circuit is coupled to the isolation circuit, used to receive the intermediate signal through the isolation circuit, and used to output an output signal generated according to the intermediate signal through the signal output terminal. The signal delay setting circuit is coupled to the primary side circuit and is used to calculate the delay time based on the voltage difference between the first signal input terminal and the second signal input terminal when the first power supply voltage is within the preset voltage range, and is used to calculate the delay time when the first power supply voltage is within the preset voltage range. When the voltage is greater than the upper limit of the preset voltage range, one of the first input signal and the second input signal is delayed according to the delay time to control the duty cycle of the output signal.

One aspect of the present application is a power conversion circuit system. The power conversion circuit system includes a high-side switch, a low-side switch, a controller circuit, a first isolated integrated circuit, and a second isolated integrated circuit. The controller circuit is used to output the first input signal and the second input signal. The first isolated integrated circuit is coupled to the controller circuit and the high-side switch, and includes a first signal delay setting circuit for receiving the first input signal through the first signal input terminal and for receiving the second input signal through the second signal input terminal. Two input signals are used to generate a first output signal for driving the high-side switch based on the first input signal and the second input signal. The second isolated integrated circuit is coupled to the controller circuit and the low-side switch, and includes a second signal delay setting circuit for receiving the second input signal through the third signal input terminal, and for receiving the second input signal through the fourth signal input terminal. An input signal is used to generate a second output signal for driving the low-side switch based on the first input signal and the second input signal. When the first power supply voltage is within the preset voltage range, the first signal delay setting circuit calculates the first delay time based on the first voltage difference between the first signal input terminal and the second signal input terminal, and the second signal delay setting circuit calculates the first delay time based on the first voltage difference between the first signal input terminal and the second signal input terminal. The second delay time is calculated from the second voltage difference between the third signal input terminal and the fourth signal input terminal. When the first power supply voltage is greater than the upper limit of the preset voltage range, the first signal delay setting circuit delays the second input signal according to the first delay time to control the duty cycle of the first output signal, and the second signal delay setting circuit The first input signal is delayed according to the second delay time to control the duty cycle of the second output signal, so that the high-side switch and the low-side switch are not turned on at the same time.

In summary, by controlling the duty cycle of the output signal generated by the isolated integrated circuit through the signal delay setting circuit, the power conversion circuit system of the present application can effectively generate dead time to protect the high-side switch and the low-side switch. In addition, compared with some related technologies that use resistor and capacitor circuit settings or use trim methods to generate dead time, the isolated integrated circuit and power conversion circuit system of the present application has low deviation, high reliability, and is suitable for circuits. Advantages include small area requirements.

The following is a detailed description of the embodiments together with the accompanying drawings. However, the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operations is not intended to limit the order of execution. Any components Recombining the structure to produce a device with equal functions is within the scope of this new model.

Unless otherwise noted, the terms used throughout the specification and patent application generally have their ordinary meanings as used in the field, in the disclosure and in the specific content.

As used herein, “coupling” or “connection” may refer to two or more components that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other. It may also refer to two or more components that are in direct physical or electrical contact with each other. Components interact or act with each other.

Please refer to FIG. 1 , which is a circuit block diagram of a power conversion circuit system 100 according to some embodiments of the present application. In some embodiments, the power conversion circuit system 100 includes a controller circuit 11 , an isolated integrated circuit 13 , an isolated integrated circuit 15 , a high-side switch 17 and a low-side switch 19 . Specifically, the power conversion circuit system 100 may be, for example but not limited to, a buck converter.

In some embodiments, as shown in FIG. 1 , the controller circuit 11 is electrically coupled to the isolated integrated circuit 13 and the isolated integrated circuit 15 . The isolated integrated circuit 13 is electrically coupled to the high-side switch 17 , and the second isolated integrated circuit 15 is electrically coupled to the low-side switch 19 . In addition, the high-side switch 17 and the low-side switch 19 are connected in series. It should be understood that in some embodiments, the connection node between the high-side switch 17 and the low-side switch 19 may be electrically coupled to a load circuit (not shown in the figure).

According to the circuit structure of the power conversion circuit system 100 described above, in some embodiments, the controller circuit 11 is used to output a first input signal IN+ and a second input signal IN- to the isolated integrated circuit 13 and the isolated integrated circuit 13 Circuit 15, in which the first input signal IN+ and the second input signal IN- can be inverted to each other. The isolated integrated circuit 13 is used to generate an output signal OUT1 to the high-side switch 17 according to the first input signal IN+ and the second input signal IN-. The isolated integrated circuit 15 is used to generate an output signal OUT2 to the low-side switch 19 according to the first input signal IN+ and the second input signal IN-. Driven by the output signal OUT1 and the output signal OUT2, the high-side switch 17 and the low-side switch 19 will be turned on alternately to generate an output current flowing through the aforementioned load circuit (not shown in the figure). In some embodiments, the first input signal IN+, the second input signal IN-, the output signal OUT1 and the output signal OUT2 are all periodic signals. In addition, the output signal OUT1 and the output signal OUT2 are also basically inverse to each other, thus driving the high-side switch 17 and the low-side switch 19 to turn on alternately.

In some embodiments, the isolated integrated circuit 13 includes a first power terminal P31, a first signal input terminal P32, a second signal input terminal P33, a first ground terminal P34, a second power terminal P35, A signal output terminal P36, an output/clamping terminal P37 and a second ground terminal P38. As shown in Figure 1, the isolated integrated circuit 13 receives a first power supply voltage VCC1 through the first power terminal P31, a first input signal IN+ through the first signal input terminal P32, and a second input signal IN+ through the second signal input terminal P33. The two input signals IN- receive a first ground voltage GND1 through the first ground terminal P34, receive a second power supply voltage VDD1 through the second power terminal P35, output the aforementioned output signal OUT1 through the signal output terminal P36, and output the aforementioned output signal OUT1 through the second ground terminal P34. The terminal P38 receives a second ground voltage VEE1.

In some further embodiments, the output/clamp terminal P37 can be electrically coupled to the high-side switch 17 , and the isolated integrated circuit 13 outputs a first-level output signal (not shown) to the high-side via the signal output terminal P36 The switch 17 may output the second level output signal (not shown in the figure) to the high-side switch 17 via the output/clamp terminal P37 as the output signal OUT1, that is, the signal output terminal P36 and the output/clamp terminal P37 are common For controlling the high-side switch 17, the first level output signal may have a low logic level, and the second level output signal may have a high logic level. In some further embodiments, the isolated integrated circuit 13 outputs the above-mentioned first level output signal or the second level output signal from the signal output terminal P36 to the high-side switch 17 to control the conduction state of the high-side switch 17, and output /The clamping terminal P37 is electrically coupled to an external component (not shown in the figure) to perform a clamping operation when the high-side switch 17 is turned-off.

In some embodiments, the isolated integrated circuit 15 includes a first power terminal P51, a first signal input terminal P52, a second signal input terminal P53, a first ground terminal P54, a second power terminal P55, A signal output terminal P56, an output/clamping terminal P57 and a second ground terminal P58. As shown in Figure 1, the isolated integrated circuit 15 receives a first power supply voltage VCC2 through the first power terminal P51, a second input signal IN- through the first signal input terminal P52, and a second input signal IN- through the second signal input terminal P53. The first input signal IN+ receives a first ground voltage GND2 through the first ground terminal P54, receives a second power supply voltage VDD2 through the second power terminal P55, outputs the aforementioned output signal OUT2 through the signal output terminal P56, and outputs the aforementioned output signal OUT2 through the second ground terminal P54. The terminal P58 receives a second ground voltage VEE2.

In some further embodiments, the output/clamping terminal P57 may be electrically coupled to the low-side switch 19 , and the isolated integrated circuit 15 outputs a first level output signal (not shown in the figure) to a low level through the signal output terminal P56 side switch 19, or output the second level output signal (not shown in the figure) to the low-side switch 19 through the output/clamp terminal P57 as the output signal OUT2, that is, the signal output terminal P56 and the output/clamp terminal P57 is jointly used to control the low-side switch 19, in which the first level output signal may have a low logic level, and the second level output signal may have a high logic level. In some further embodiments, the isolated integrated circuit 15 outputs the above-mentioned first level output signal or the second level output signal from the signal output terminal P56 to the low-side switch 19 to control the conduction state of the low-side switch 19, and The output/clamp terminal P57 is electrically coupled to an external component (not shown in the figure) to implement a clamping operation when the low-side switch 19 is turned-off.

In the above embodiment, as shown in FIG. 1 , the high-side switch 17 is coupled to a third power supply voltage HVDC, and the low-side switch 19 is coupled to the second ground voltage VEE2. That is to say, the high-side switch 17 and the low-side switch 19 are connected in series between the third power supply voltage HVDC and the second ground voltage VEE2. In the above embodiment, the first power supply voltage VCC1, the first power supply voltage VCC2, the second power supply voltage VDD1, the second power supply voltage VDD2 and the third power supply voltage HVDC are different from each other, and the first ground voltage GND1 and the first ground voltage GND2 , the second ground voltage VEE1 and the second ground voltage VEE2 are different from each other, but the present invention is not limited to this.

Generally speaking, each of the high-side switch 17 and the low-side switch 19 can be implemented by a transistor (eg, a metal oxide semiconductor (MOS) transistor). Therefore, if the high-side switch 17 and the low-side switch 19 are turned on at the same time due to some non-ideal factors, a large current may flow through the high-side switch 17 and the low-side switch 19, which further causes the high-side switch 17 and the low-side switch to be turned on at the same time. The switch 19 itself or the transistor inside it is burned out.

In view of this, in some embodiments, the isolated integrated circuit 13 is configured with a signal delay setting circuit 131 , and the isolated integrated circuit 15 is configured with a signal delay setting circuit 151 . It is worth noting that the signal delay setting circuit 131 and the signal delay setting circuit 151 are used to control the duty ratio of the output signal OUT1 and the duty ratio of the output signal OUT2 respectively, thereby ensuring that the high-side switch 17 and the low-side switch 19 will not be turned on at the same time.

Next, the isolated integrated circuit 13 is described in detail with reference to Figure 2. Figure 2 is a circuit schematic diagram of the isolated integrated circuit 13 according to some embodiments of the present application. In some embodiments, the isolated integrated circuit 13 includes the aforementioned signal delay setting circuit 131, primary side circuit 133, isolation circuit 135 and secondary side circuit 137. Specifically, the isolated integrated circuit 13 may be, for example but not limited to, a gate driver. That is, in some embodiments, the output signal OUT1 is output to the gate of the transistor of the high-side switch 17 .

In some embodiments, the signal delay setting circuit 131 includes a voltage drop generating circuit 311, a delay time control circuit 313 and a signal delay circuit 315. In some further embodiments, the voltage drop generating circuit 311 includes a current generating circuit ICS, a resistive element RDT and a switching circuit SW, wherein the switching circuit SW includes a first switch SW1 and a second switch SW2. Specifically, the current generating circuit ICS can be implemented by a current source (for example, a current mirror circuit), the resistive element RDT can be implemented by a resistor, and both the first switch SW1 and the second switch SW2 can be implemented by a transistor. to achieve. It should be understood that in some embodiments, the resistive element RDT can also be replaced by other suitable passive components (such as capacitors, inductors, etc.).

In some embodiments, the primary side circuit 133 includes a logic control circuit 331 , a logic circuit 333 , a logic circuit 335 and a logic circuit 337 . Specifically, the logic control circuit 331 can be implemented by an oscillator, a modulator, a transmitter or a combination thereof, the logic circuit 333 can be implemented by an AND gate, and the logic circuit 335 can be implemented by a buffer gate. , and the logic circuit 337 can be implemented by a NOT gate.

In some embodiments, the logic circuit 335 is coupled between the first signal input terminal P32 and a first data input terminal of the logic circuit 333 . The signal delay circuit 315 is coupled between the second signal input terminal P33 and a data input terminal of the logic circuit 337, and the logic circuit 337 is coupled between the signal delay circuit 315 and a second data input terminal of the logic circuit 333. . In addition, a data output terminal of the logic circuit 333 is coupled to a data input terminal of the logic control circuit 331 .

In some embodiments, the current generating circuit ICS is coupled between the first power terminal P31 and the first switch SW1. The first switch SW1 is coupled between the current generating circuit ICS and the first signal input terminal P32. The resistive element RDT is coupled between the first signal input terminal P32 and the second signal input terminal P33. The second switch SW2 is coupled between the second signal input terminal P33 and the first ground terminal P34.

In some embodiments, the delay time control circuit 313 is coupled to the first power terminal P31, the logic control circuit 331, the signal delay circuit 315, the first signal input terminal P32, the second signal input terminal P33, the first switch SW1 and the second signal input terminal P33. Two switches SW2.

It can be seen from the above description of the signal delay setting circuit 131 and the primary side circuit 133 that the signal delay setting circuit 131 is coupled to the primary side circuit 133 . In addition, in some further embodiments, as shown in FIG. 2 , the resistive element RDT in the signal delay setting circuit 131 is configured outside the isolated integrated circuit 13 , and the current generating circuit ICS, The first switch SW1 and the second switch SW2 are disposed inside the isolated integrated circuit 13 . However, the present invention is not limited to this. Any circuit that can generate the voltage difference VDT between the first signal input terminal P32 and the second signal input terminal P33 within a specific period can be used to implement the signal delay setting circuit 131 .

In some embodiments, one end of the isolation circuit 135 is coupled to the output end of the primary side circuit 133 (ie, a data output end of the logic control circuit 331), and the other end of the isolation circuit 135 is coupled to the secondary side circuit. The input terminal of 137 is used to provide electrical insulation between the primary side circuit 133 and the secondary side circuit 137 in the isolated integrated circuit 13 according to system requirements. Accordingly, the working voltage of the primary side circuit 133 (ie, the first power supply voltage VCC1 and the first ground voltage GND1) is different from the working voltage of the secondary side circuit 137 (ie, the second power supply voltage VDD1 and the second ground voltage VEE1). Specifically, the isolation circuit 135 can be implemented by a passive component (eg, capacitor 351) or an insulating component (eg, transformer).

In some embodiments, while ensuring voltage isolation (ie, the aforementioned electrical insulation) between the primary side circuit 133 and the secondary side circuit 137 , the isolation circuit 135 is also used as the primary side circuit 133 and the secondary side circuit 137 A communication interface between the two circuits to allow data, signals and/or information to be transmitted from the primary side circuit 133 (for example, through voltage coupling phenomena) to the secondary side circuit 137 . Furthermore, in some embodiments, the secondary side circuit 137 may be implemented by a demodulator, a receiver, an amplifier, or a combination thereof.

In some embodiments, the first power supply voltage VCC1 starts to rise from 0 volts. After the first power supply voltage VCC1 rises to a power-on reset voltage POR (for example: 1.2~1.8 volts), the isolated integrated circuit 13 will be initialized to a known state to facilitate the isolated integrated circuit 13. Logic operations in body circuit 13. Then, after the first power supply voltage VCC1 continues to rise and reaches an undervoltage lockout voltage UVLO (for example: 3, 5, 8 volts), the isolated integrated circuit 13 then responds to the first input signal IN+ and the second input signal IN+. Signal IN-operation.

In some embodiments, the delay time control circuit 313 is used to detect the first power supply voltage VCC1. When detecting that the first power supply voltage VCC1 is greater than the power-on reset voltage POR and less than the undervoltage lockout voltage UVLO, the delay time control circuit 313 controls the first switch SW1 and the second switch SW2 to turn on. Accordingly, a current path will be formed between the first power supply voltage VCC1 and the first ground voltage GND1. Specifically, the current path includes the first power terminal P31, the current generating circuit ICS, the first switch SW1, the resistor element RDT, the second switch SW2 and the first ground terminal P34.

In some embodiments, the current generating circuit ICS is used to generate a detection current Id according to the first power supply voltage VCC1, where the detection current Id may be a fixed current. Through the current path, the detection current Id generated by the current generating circuit ICS will sequentially flow through the first power terminal P31, the current generating circuit ICS, the first switch SW1, the resistive element RDT and the second switch SW2, and then flow to the first ground terminal P34. It can be known from Ohm's law that when the detection current Id flows through the resistive element RDT, a voltage difference VDT will be generated at both ends of the resistive element RDT (ie, the first signal input terminal P32 and the second signal input terminal P33). In some embodiments, the delay time control circuit 313 is used to calculate a delay time DT based on the voltage difference VDT, which will be described in detail in the following paragraphs with FIG. 3 .

Please refer to Figure 3, which is a circuit block diagram of the delay time control circuit 313 according to some embodiments of the present application. In some embodiments, the delay time control circuit 313 includes a central control circuit 3131, a voltage sensing circuit 3133, a storage circuit 3135, a delay time calculation circuit 3137 and a switch driving circuit 3139. As shown in FIG. 3 , the voltage sensing circuit 3133 is coupled to the first signal input terminal P32 and the second signal input terminal P33. The storage circuit 3135 is coupled to the voltage sensing circuit 3133, and the delay time calculation circuit 3137 is coupled to the storage circuit 3135. The central control circuit 3131 is coupled to the voltage sensing circuit 3133, the storage circuit 3135, the delay time calculation circuit 3137 and the switch driving circuit 3139.

In some embodiments, the central control circuit 3131 is used to detect the first power supply voltage VCC1 and to control the operations of the voltage sensing circuit 3133, the storage circuit 3135, the delay time calculation circuit 3137 and the switch driving circuit 3139.

In some embodiments, the voltage sensing circuit 3133 senses the voltage difference VDT between the first signal input terminal P32 and the second signal input terminal P33 to output a sensing voltage value VSEN corresponding to the voltage difference VDT. In some embodiments, the sensing voltage value VSEN is the current value of the detection current Id (for example: 0.1~100 microamps (µA)) multiplied by the resistance value of the resistive element RDT (for example: 1~500 kiloohms (kΩ) )).

In some embodiments, the storage circuit 3135 is used to store the sensing voltage value VSEN to provide the sensing voltage value VSEN to the delay time calculation circuit 3137. Specifically, the storage circuit 3135 can be implemented by one or more memories.

In some embodiments, the delay time calculation circuit 3137 is used to calculate the delay time DT according to the sensing voltage value VSEN. In some further embodiments, a lookup table (not shown in the figure) is prestored in the storage circuit 3135, where the lookup table records multiple voltage values and corresponding multiple durations. Therefore, the delay time calculation circuit 3137 can find a voltage value among the multiple voltage values that is the same as the sensing voltage value VSEN by comparing the multiple voltage values in the lookup table with the sensing voltage value VSEN, and compare the voltage value with the sensing voltage value VSEN. The duration corresponding to the voltage value is regarded as the delay time DT. It should be understood that, if the voltage value that is the same as the sensed voltage value VSEN is not found from multiple voltage values, the delay time calculation circuit 3137 may further calculate the delay time DT through, for example, but not limited to, an interpolation method.

The method of calculating the delay time DT is not limited to the above. For example, in some embodiments, the delay time calculation circuit 3137 calculates the delay time DT by substituting the sensing voltage value VSEN into the following formula (1), where a and b can each be any preset value. It should be understood that the delay time calculation circuit 3137 is not limited to using formula (1) to calculate the delay time DT. Any formula that can describe the relationship between the sensing voltage value VSEN and the delay time DT can be used by the delay time calculation circuit 3137 to calculate Delay time DT. …(1)

Following the above embodiment in which the delay time control circuit 313 controls the first switch SW1 and the second switch SW2 to be turned on, the delay time control circuit 313 can control the first switch SW1 and the second switch SW2 to be turned on or off through the switch driving circuit 3139 in Figure 3. break. For example, when the central control circuit 3131 detects that the first power supply voltage VCC1 is greater than the power-on reset voltage POR and less than the undervoltage lockout voltage UVLO, the central control circuit 3131 controls the switch driving circuit 3139 to output the enable signal SEN to the first switch SW1 and the second switch SW2 to control the first switch SW1 and the second switch SW2 to be turned on.

In some embodiments, when it is detected that the first power supply voltage VCC1 is not greater than the power-on reset voltage POR or not less than the undervoltage lockout voltage UVLO, the delay time control circuit 313 controls the first switch SW1 and the second switch SW1 through the switch driving circuit 3139. Switch SW2 is turned off. Accordingly, the detection current Id does not flow through the resistive element RDT.

It can be seen from the description of Figures 2 and 3 that the delay time control circuit 313 is used to when the first power supply voltage VCC1 is within a preset voltage range (that is, between the power-on reset voltage POR and the undervoltage lockout voltage UVLO), Enabling the voltage drop generating circuit 311 (that is, turning on the first switch SW1 and the second switch SW2) generates a voltage difference VDT at the first signal input terminal P32 and the second signal input terminal P33. In addition, the delay time control circuit 313 can calculate the delay time DT based on the voltage difference VDT using a table lookup or formula calculation method.

In some embodiments, after the delay time calculation circuit 3137 calculates the delay time DT, the delay time control circuit 313 provides the delay time DT to the signal delay circuit 315 as shown in FIG. 2 .

In some embodiments, as described above, when it is detected that the first power supply voltage VCC1 continues to rise above the undervoltage lockout voltage UVLO, the delay time control circuit 313 disables the voltage drop generating circuit 311 (that is, turns off the first switch SW1 and the second switch SW2). Accordingly, the isolated integrated circuit 13 can operate according to the first input signal IN+ and the second input signal IN-, and the signal delay circuit 315 can delay the received signal according to the delay time DT.

Next, the operation of the isolated integrated circuit 13 based on the first input signal IN+ and the second input signal IN- is illustrated with Figures 2 and 4. Figure 4 illustrates an isolated integrated circuit according to some embodiments of the present application. Timing diagram of some signals related to circuit 13.

In some embodiments, as shown in FIG. 2 , the primary side circuit 133 receives the first input signal IN+ from the first signal input terminal P32 via the logic circuit 335 .

In some embodiments, as shown in Figure 2, the signal delay circuit 315 receives the second input signal IN- from the second signal input terminal P33, and delays the second input signal IN- according to the delay time DT to output a delayed input Signal DIN- to logic circuit 337. In some further embodiments, as shown in FIG. 4 , the signal delay circuit 315 delays the falling edge RE- of the second input signal IN- according to the delay time DT to generate the delayed input signal DIN-. Therefore, in Figure 4, the falling edge DRE- of the delayed input signal DIN- will lag behind the falling edge RE- of the second input signal IN- by approximately the delay time DT. In this embodiment, the signal delay circuit 315 may be a digital circuit so as to only delay the falling edge RE- of the second input signal IN-, but the invention is not limited thereto. In addition, although the signal delay circuit 315 is disposed on the transmission path of the second input signal IN- in this embodiment, in some variations of the present invention, the signal delay circuit 315 may be disposed on the transmission path of the first input signal IN+. On the transmission path, the same effect can be achieved.

In the embodiment of FIG. 2, the logic circuit 335 buffers the first input signal IN+ and transmits it to the logic circuit 333, and the logic circuit 337 inverts the delayed input signal DIN- and transmits it to the logic circuit 333. Thereafter, the logic circuit 333 generates an intermediate signal MID1 to the logic control circuit 331 based on the first input signal IN+ and the delayed input signal DIN-, and the logic control circuit 331 can appropriately process the intermediate signal MID1 (for example: signal buffering, signal amplification, etc. ) and then coupled to the isolation circuit 135.

In some embodiments, as shown in Figure 2, the isolation circuit 135 is used to couple and transmit the intermediate signal MID1 from the primary side circuit 133 to the secondary side circuit 137, so that the secondary side circuit 137 generates an output signal according to the intermediate signal MID1. OUT1. In some further embodiments, the secondary side circuit 137 receives and appropriately processes (eg, signal buffering, signal amplification, etc.) substantially the same signal as the intermediate signal MID1 to generate the output signal OUT1. Therefore, in some embodiments, as shown in FIG. 4 , the waveform of the output signal OUT1 and the waveform of the intermediate signal MID1 have substantially the same frequency and/or period.

Next, the output signal OUT1 will be further explained with Figure 4. In the case of using the circuit architecture in Figure 2, each cycle of the output signal OUT1 has an enable period DTEN1 (corresponding to the output signal OUT1 at the enable level) and a disable period DTDE1 (corresponding to the output signal at the disable level). OUT1).

In addition, the thick dotted line in FIG. 4 also represents the rising edge of the output signal OUT1 when the isolated integrated circuit 13 does not delay the second input signal IN- in the primary side circuit 133 . In this case, each cycle of the signal output by the isolated integrated circuit 13 has an enabling period TEN1 and a disabling period TDE1. As can be seen from Figure 4, compared with the output signal OUT1 generated without delaying the second input signal IN- in the primary side circuit 133, the output signal OUT1 generated by using the circuit structure of Figure 2 has a lower duty cycle. (That is, the proportion of the enable period DTEN1 in one cycle of the output signal OUT1). The aforementioned "lower duty cycle" can prevent the high-side switch 17 and the low-side switch 19 from being turned on at the same time. This effect will be explained in detail in the following paragraphs with reference to Figure 6.

Please refer to FIG. 5 , which is a timing diagram of some signals related to the isolated integrated circuit 15 according to some embodiments of the present application. It should be understood that the isolated integrated circuit 15 in FIG. 1 can adopt the same or similar circuit structure as the isolated integrated circuit 13 in FIG. 2, so a detailed description of the isolated integrated circuit 15 is omitted here.

As shown in FIG. 5 , the main difference between the isolated integrated circuit 15 and the isolated integrated circuit 13 is that the isolated integrated circuit 15 receives the second input signal IN- through the first signal input terminal P52 and passes the The second signal input terminal P53 receives the first input signal IN+. In other words, in some embodiments, the signal delay setting circuit 151 in the isolated integrated circuit 15 delays the falling edge RE+ of the first input signal IN+, so that the isolated integrated circuit 15 generates the output signal OUT2. Similar to the output signal OUT1, each cycle of the output signal OUT2 has an enable period DTEN2 (corresponding to the output signal OUT2 at the enable level) and a disable period DTDE2 (corresponding to the output signal OUT2 at the disable level).

In addition, the thick dotted line in FIG. 5 also represents the rising edge of the output signal OUT2 when the first input signal IN+ is not delayed in the primary side circuit of the isolated integrated circuit 15 . In this case, each cycle of the signal output by the isolated integrated circuit 15 has an enabling period TEN2 and a disabling period TDE2. As can be seen from FIG. 5 , compared with the output signal OUT2 generated without delaying the first input signal IN+ in the primary side circuit of the isolated integrated circuit 15 , the output signal OUT2 is generated by delaying the first input signal IN+ in the primary side circuit of the isolated integrated circuit 15 . The output signal OUT2 generated by the delay of the first input signal IN+ has a lower duty cycle (that is, the proportion of the enable period DTEN2 in one cycle of the output signal OUT2). The aforementioned "lower duty cycle" can prevent the high-side switch 17 and the low-side switch 19 from being turned on at the same time. This effect will be explained in detail in the following paragraphs with reference to Figure 6.

In the above embodiment, the high-side switch 17 in Figure 1 is turned on according to the output signal OUT1 of the enable level (corresponding to the enable period DTEN1 in Figure 4), and is turned on according to the output signal OUT1 of the disable level (corresponding to the enable period DTEN1 in Figure 4). DTDE1) is turned off during the disable period of the figure. The low-side switch 19 in Figure 1 is turned on according to the output signal OUT2 of the enable level (corresponding to the enable period DTEN2 of Figure 5), and is turned on according to the output signal OUT2 of the disable level (corresponding to the disable period DTDE2 of Figure 5). ) shut down.

Next, the relationship between the output signal OUT1 and the output signal OUT2 is further explained with reference to Figure 6. Figure 6 is a timing diagram of the output signal OUT1 and the output signal OUT2 according to some embodiments of the present application. As can be seen from the above description, the signal delay setting circuit 131 controls the isolated integrated circuit 13 to generate the output signal OUT1 with a lower duty cycle, and the signal delay setting circuit 151 controls the isolated integrated circuit 15 to generate the output signal OUT2 with a lower duty cycle. Accordingly, as shown in Figure 6, the high-side switch 17 will be turned on during a period QON1 (corresponding to the enabling period DTEN1 of the output signal OUT1), while the low-side switch 19 will be turned on during a period QON2 (corresponding to the enabling period DTEN1 of the output signal OUT2). DTEN2) is turned on during the operation. The period QON1 and the period QON2 do not overlap, which means that the high-side switch 17 and the low-side switch 19 are not turned on at the same time. A period DZ between period QON1 and period QON2 is usually called dead time or dead time.

In the above embodiment, as shown in Figure 2, the logic circuit 337 is coupled between the signal delay circuit 315 and the logic circuit 333, but the invention is not limited to this. For example, in some embodiments, the logic circuit 337 is coupled between the second signal input terminal P33 and the signal delay circuit 315 . Under this configuration, the logic circuit 337 inverts the second input signal IN- and then transmits it to the signal delay circuit 315 . The signal delay circuit 315 then delays multiple rising edges of the inverted second input signal IN- according to the delay time DT, so that the output signal OUT1 as shown in FIG. 4 can also be generated.

In the above embodiment, as shown in Figure 2, the signal delay circuit 315 is used to delay the second input signal IN- from the second signal input terminal P33, but the present invention is not limited to this. For example, in some embodiments, the signal delay circuit 315 can be connected in series before or after the logic circuit 335, and delays a plurality of rises of the first input signal IN+ from the first signal input terminal P32 according to the delay time DT. edge, and the second input signal IN- from the second signal input terminal P33 is directly transmitted to the logic circuit 337, so that the output signal OUT1 as shown in Figure 4 can also be generated.

It can be seen from the above description that the signal delay circuit 315 of the present application can delay the first input signal according to the delay time DT when the first power supply voltage VCC1 is greater than the upper limit of the preset voltage range (that is, exceeds the undervoltage lockout voltage UVLO). One of IN+ and the second input signal IN- is used to control the duty cycle of the output signal OUT1. It should be understood that the above description is also applicable to the signal delay setting circuit 151 in the isolated integrated circuit 15, that is, the signal delay setting circuit 151 can delay one of the first input signal IN+ and the second input signal IN- according to the delay time DT. Or, to control the duty cycle of the output signal OUT2. Since the signal delay setting circuit 151 can be configured with reference to the signal delay setting circuit 131 , the remaining detailed description of the signal delay setting circuit 151 is omitted here.

In the above embodiment, as shown in FIG. 2 , the logic control circuit 331 appropriately processes the intermediate signal MID1 (for example, signal buffering, signal amplification, etc.) and then couples it to the isolation circuit 135 . In some further embodiments, the logic control circuit 331 modulates the intermediate signal MID1 according to the fundamental frequency signal provided by the oscillator through a modulator to generate a modulation signal. Isolation circuit 135 couples the modulation signal to secondary side circuit 137 . The secondary side circuit 137 demodulates the modulated signal through a demodulator to generate a signal that is substantially the same as the intermediate signal MID1.

In addition, the delay time control circuit 313 of the present application is not limited to the circuit architecture shown in FIG. 3 . For example, in some embodiments, the central control circuit 3131 can receive and store the sensing voltage value VSEN through its internal storage circuit (not shown in the figure) to provide the sensing voltage value VSEN to the delay time calculation circuit 3137 . In such embodiments, storage circuit 3135 may be omitted from FIG. 3 .

It can be known from the above embodiments of the present application that the duty cycle of the output signal OUT1 generated by the isolated integrated circuit 13 and the output signal generated by the isolated integrated circuit 15 are controlled by the signal delay setting circuit 131 and the signal delay setting circuit 151 respectively. According to the duty cycle of OUT2, the power conversion circuit system 100 of the present application can effectively generate dead time to prevent the high-side switch 17 and the low-side switch 19 from being turned on at the same time, so the effect of protecting the high-side switch 17 and the low-side switch 19 can be achieved. In addition, compared with some related technologies that use resistor and capacitor circuit settings or use trim methods to generate dead time, the isolated integrated circuit 13, isolated integrated circuit 15 and power conversion circuit system 100 of the present application have It has the advantages of low deviation, high reliability, and small requirement for circuit area.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the scope of the present invention. Those with ordinary skill in the technical field can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope of the patent application attached.

11:Controller circuit 13,15: Isolated integrated circuit 17:High side switch 19: Low side switch 100:Power conversion circuit system 131,151: Signal delay setting circuit 133: Primary side circuit 135:Isolation circuit 137:Secondary side circuit 311: Voltage drop generating circuit 313: Delay time control circuit 315: Signal delay circuit 331: Logic control circuit 333,335,337: Logic circuit 351:Capacitor 3131: Central control circuit 3133:Voltage sensing circuit 3135:Storage circuit 3137: Delay time calculation circuit 3139: Switch drive circuit DIN-: delayed input signal DT: Delay time GND1, GND2: first ground voltage HVDC: third supply voltage ICS: current generating circuit Id: detect current IN+: first input signal IN-: Second input signal MID1: middle signal OUT1, OUT2: output signal P31, P51: first power terminal P32, P52: first signal input terminal P33, P53: second signal input terminal P34, P54: first ground terminal P35, P55: second power terminal P36, P56: signal output terminal P37, P57: output/clamp end P38, P58: second ground terminal POR: power-on reset voltage QON1,QON2,DZ:period RDT: Resistive element RE-,DRE-,RE+: falling edge SEN: enabling signal SW: switch circuit SW1: first switch SW2: Second switch TDE1, TDE2, DTDE1, DTDE2: disable period TEN1,TEN2,DTEN1,DTEN2: enabling period UVLO: Undervoltage lockout voltage VCC1, VCC2: first power supply voltage VDD1, VDD2: second power supply voltage VDT: voltage difference VEE1, VEE2: second ground voltage VSEN: Sensing voltage value

Figure 1 is a circuit block diagram of a power conversion circuit system according to some embodiments of the present application. Figure 2 is a schematic circuit diagram of an isolated integrated circuit according to some embodiments of the present application. Figure 3 is a circuit block diagram of a delay time control circuit according to some embodiments of the present application. Figure 4 is a signal timing diagram of an isolated integrated circuit according to some embodiments of the present application. Figure 5 is a signal timing diagram of an isolated integrated circuit according to some embodiments of the present application. Figure 6 is an output signal timing diagram of two isolated integrated circuits according to some embodiments of the present application.

13:Isolated integrated circuit

131: Signal delay setting circuit

133: Primary side circuit

135:Isolation circuit

137:Secondary side circuit

311: Voltage drop generating circuit

313: Delay time control circuit

315: Signal delay circuit

331: Logic control circuit

333,335,337: Logic circuit

351:Capacitor

DIN-: delayed input signal

DT: Delay time

GND1: first ground voltage

ICS: current generating circuit

Id: detect current

IN+: first input signal

IN-: Second input signal

MID1: middle signal

OUT1: output signal

P31: First power terminal

P32: First signal input terminal

P33: Second signal input terminal

P34: First ground terminal

P35: Second power terminal

P36: Signal output terminal

P37: Output/clamp end

P38: Second ground terminal

POR: power-on reset voltage

RDT: Resistive element

SW: switch circuit

SW1: first switch

SW2: Second switch

UVLO: Undervoltage lockout voltage

VCC1: first power supply voltage

VDD1: Second power supply voltage

VDT: voltage difference

VEE1: Second ground voltage

Claims (10)

A signal delay setting circuit suitable for an isolated integrated circuit, wherein the isolated integrated circuit includes a first signal input terminal, a second signal input terminal and a signal output terminal, the first signal input terminal is used to Receive a first input signal, the second signal input terminal is used to receive a second input signal, the signal output terminal is used to output an output signal generated based on the first input signal and the second input signal, and the signal The delay setting circuit includes: a voltage drop generating circuit for generating a voltage difference between the first signal input terminal and the second signal input terminal; A delay time control circuit, coupled to the voltage drop generating circuit, and used to enable the voltage drop generating circuit to generate the voltage difference when a first power supply voltage is within a preset voltage range, and used to generate the voltage difference according to the voltage difference Obtain a delay time, wherein the isolated integrated circuit further includes a first power terminal, the first power terminal is used to receive the first power voltage; and A signal delay circuit, coupled to the delay time control circuit, and used to delay the first input signal and the second input signal according to the delay time when the first power supply voltage is greater than the upper limit of the preset voltage range. One of them to control the duty cycle of the output signal. The signal delay setting circuit as described in claim 1, wherein the voltage drop generating circuit includes: a current generating circuit coupled to the first power terminal and used to output a detection current; a resistive element coupled between the first signal input terminal and the second signal input terminal; and A switch circuit is coupled to the current generating circuit, the resistive element and a first ground voltage, and is used to conduct when the delay time control circuit enables the voltage drop generating circuit to allow the detection current to flow through the resistor. element, so that the voltage difference is generated across the resistive element. The signal delay setting circuit as described in claim 2, wherein the resistive element is arranged outside the isolated integrated circuit, and the current generating circuit and the switching circuit are arranged inside the isolated integrated circuit. The signal delay setting circuit as described in claim 2, wherein the switch circuit includes: a first switch coupled between the current generating circuit and the first signal input terminal; and A second switch is coupled between the second signal input terminal and a first ground terminal of the isolated integrated circuit, wherein the first ground terminal is used to receive the first ground voltage. The signal delay setting circuit as described in claim 1, wherein the delay time control circuit includes: a voltage sensing circuit for sensing the voltage difference between the first signal input terminal and the second signal input terminal to output a sensing voltage value corresponding to the voltage difference; a delay time calculation circuit for calculating the delay time based on the sensed voltage value to output the delay time to the signal delay circuit; A switch drive circuit used to control a switch circuit in the voltage drop generating circuit to turn on or off; and A central control circuit is coupled to the voltage sensing circuit, the delay time calculation circuit and the switch drive circuit, and is used to control the voltage sensing circuit, the delay time calculation circuit and the switch drive circuit. The signal delay setting circuit as described in claim 5, wherein the delay time control circuit further includes: A storage circuit is coupled to the voltage sensing circuit, the delay time calculation circuit and the central control circuit, and is used to store the sensing voltage value to provide the sensing voltage value to the delay time calculation circuit. The signal delay setting circuit as described in claim 1, wherein the signal delay circuit is coupled to the second signal input terminal and used to allow a plurality of falling edges of the second input signal or the inverted second input signal to Multiple rising edges are delayed by this delay time. The signal delay setting circuit of claim 1, wherein the preset voltage range is between a power-on reset voltage and an undervoltage lockout voltage. An isolated integrated circuit has a first power terminal, a first signal input terminal, a second signal input terminal and a signal output terminal, and includes: A primary-side circuit for receiving a first power supply voltage via the first power terminal, for receiving a first input signal via the first signal input terminal, and for receiving a second second input signal via the second signal input terminal. An input signal used to generate an intermediate signal based on the first input signal and the second input signal; An isolation circuit is coupled to the primary circuit and used to transmit the intermediate signal; A secondary side circuit is coupled to the isolation circuit, and is used to receive the intermediate signal through the isolation circuit, and to output an output signal generated based on the intermediate signal through the signal output terminal; and A signal delay setting circuit is coupled to the primary side circuit and used to calculate a voltage difference based on a voltage difference between the first signal input terminal and the second signal input terminal when the first power supply voltage is within a preset voltage range. Delay time, and used to delay one of the first input signal and the second input signal according to the delay time to control the output signal when the first power supply voltage is greater than the upper limit of the preset voltage range. of duty cycle. A power conversion circuit system including: a high-side switch; a low-side switch; a controller circuit for outputting a first input signal and a second input signal; A first isolated integrated circuit, coupled between the controller circuit and the high-side switch, has a first signal input terminal and a second signal input terminal, and includes a first signal delay setting circuit, wherein The first isolated integrated circuit is used to receive the first input signal through the first signal input terminal, receive the second input signal through the second signal input terminal, and according to the first input signal and the second input The signal generates a first output signal for driving the high-side switch; and A second isolated integrated circuit is coupled between the controller circuit and the low-side switch, has a third signal input terminal and a fourth signal input terminal, and includes a second signal delay setting circuit, wherein The second isolated integrated circuit is used to receive the second input signal through the third signal input terminal, receive the first input signal through the fourth signal input terminal, and according to the first input signal and the second input The signal generates a second output signal for driving the low-side switch; When a first power supply voltage is within a preset voltage range, the first signal delay setting circuit calculates a first delay time based on a first voltage difference between the first signal input terminal and the second signal input terminal, and The second signal delay setting circuit calculates a second delay time based on a second voltage difference between the third signal input terminal and the fourth signal input terminal; When the first power supply voltage is greater than the upper limit of the preset voltage range, the first signal delay setting circuit delays the second input signal according to the first delay time to control the duty cycle of the first output signal, And the second signal delay setting circuit delays the first input signal according to the second delay time to control the duty cycle of the second output signal, so that the high-side switch and the low-side switch are not turned on at the same time.

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