TWM650457U - Isolation integrated circuit and carrier frequency control circuit - Google Patents

Abstract

The present disclosure provides isolation integrated circuits and carrier frequency control circuits. The isolation integrated circuit includes a carrier frequency generation circuit, a carrier frequency control circuit and a modulation circuit. The carrier frequency generation circuit generates a carrier frequency signal. The carrier frequency control circuit is electrically connected to the carrier frequency generation circuit, detects an enable period and a disable period of input signal, controls the carrier frequency generation circuit to output the carrier frequency signal during the enable period, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal for output period of timing pulse during the disable period. The timing pulse is generated in response to detection of the disable period. The modulation circuit is electrically connected to the carrier frequency generation circuit, receives the input signal and the carrier frequency signal, and outputs modulation signals according to the input signal and the carrier frequency signal.

Description

Isolated integrated circuits and carrier frequency control circuits

The present disclosure relates to a carrier frequency control circuit, particularly a carrier frequency control circuit applied to an isolated integrated circuit.

In some related technologies for generating modulation signals, the modulator usually modulates an input signal by a carrier frequency signal output by an oscillator to generate the modulation signal. However, these related technologies still allow the oscillator to continuously output the carrier frequency signal even when the carrier frequency signal is not needed, resulting in an increase in circuit power consumption of the related technologies.

One aspect of the present disclosure is an isolated integrated circuit. The isolated integrated circuit includes a primary side circuit, an isolation circuit and a secondary side circuit. The primary side circuit includes a carrier frequency generating circuit, a carrier frequency control circuit and a modulation circuit. The carrier frequency generating circuit is used to generate a carrier frequency signal. The carrier frequency control circuit is electrically coupled to the carrier frequency generating circuit, and is used to detect at least one enabling period and at least one disabling period of an input signal, and to control the output of the carrier frequency generating circuit during the at least one enabling period. The carrier frequency signal is used to control the carrier frequency generating circuit to stop outputting the carrier frequency signal during the output of at least one timing pulse during the at least one disable period, wherein the at least one timing pulse is in response to detecting entry into the at least one generated during the disabling period, and when the output period of one of the at least one timing pulses does not overlap with one of the at least one enabling period that is adjacent and located after the at least one timing pulse, the The output period of the next one of at least one timing pulse will be adjusted. The modulation circuit is electrically coupled to the carrier frequency generating circuit for receiving the input signal and the carrier frequency signal, and for outputting a modulation signal according to the input signal and the carrier frequency signal. The isolation circuit is coupled to the primary circuit and used to transmit the modulation signal. The secondary side circuit is coupled to the isolation circuit, is used to receive the modulation signal through the isolation circuit, and is used to generate an output signal according to the modulation signal.

One aspect of the present disclosure is a carrier frequency control circuit. The carrier frequency control circuit is electrically coupled to a carrier frequency generation circuit for receiving an input signal, and includes an edge detection circuit, a timing pulse generation circuit and a switch control circuit. The edge detection circuit is used to output at least one rising signal during at least one enabling period of the input signal, and to output at least one falling signal during at least one disabling period of the input signal. The timing pulse generation circuit is electrically coupled to the edge detection circuit for outputting a frequency filter signal, and for adjusting the voltage level of the frequency filter signal according to the at least one falling signal to generate the at least one timing pulse, wherein In the case where the output period of one of the at least one timing pulses does not overlap with one of the at least consistent enable periods that are adjacent and located after the at least one timing pulse, the next one of the at least one timing pulses The output period will be adjusted. The switch control circuit is electrically coupled to the carrier frequency generating circuit, the edge detection circuit and the timing pulse generating circuit, and is used to control the carrier frequency generating circuit to output the carrier frequency signal based on the at least one rising signal, and to control the carrier frequency generating circuit to output the carrier frequency signal based on the at least one rising signal. The at least one timing pulse controls the carrier frequency generating circuit to stop outputting the carrier frequency signal.

In summary, the carrier frequency control circuit of the present disclosure detects the enable period and disable period of the input signal, and controls the carrier frequency generating circuit to stop outputting the carrier frequency signal during the output period of the timing pulse during the disable period of the input signal. Therefore, compared with related technologies that do not stop outputting the carrier frequency signal during the disabling period of the input signal, the isolated integrated circuit of the present disclosure has lower power consumption.

The following is a detailed description of the embodiments together with the accompanying drawings. However, the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operations is not intended to limit the order of execution. Any components Recombining the structure to produce a device with equal functions is within the scope of this disclosure.

Unless otherwise noted, the terms used throughout the specification and patent application generally have their ordinary meanings as used in the field, in the disclosure and in the specific content.

As used herein, “coupling” or “connection” may refer to two or more components that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other. It may also refer to two or more components that are in direct physical or electrical contact with each other. Components interact or act with each other.

Please refer to FIG. 1 , which is a block diagram of an isolated integrated circuit 100 according to some embodiments of the present disclosure. In some embodiments, the isolated integrated circuit 100 includes a primary circuit 10 , an isolation circuit 20 and a secondary circuit 30 . Specifically, the isolated integrated circuit 100 may be a gate driver.

In some embodiments, as shown in FIG. 1 , one end of the isolation circuit 20 is coupled to the output end of the primary side circuit 10 , and the other end of the isolation circuit 20 is coupled to the input end of the secondary side circuit 30 to cope with the problem. The system requirement is to provide electrical isolation between the primary circuit 10 and the secondary circuit 30 in the isolated integrated circuit 100 . Accordingly, the primary side circuit 10 can use a first power supply voltage VCC1 and a first ground voltage GND1 as operating voltages, and the secondary side circuit 30 can use a second power supply voltage VCC2 different from the first power supply voltage VCC1 and different A second ground voltage GND2 that is higher than the first ground voltage GND1 serves as the operating voltage. Specifically, the isolation circuit 20 can be implemented by insulating components such as transformers and capacitors.

In some embodiments, while ensuring voltage isolation (ie, the aforementioned electrical insulation) between the primary side circuit 10 and the secondary side circuit 30 , the isolation circuit 20 can also serve as the primary side circuit 10 and the secondary side circuit 30 The communication interface between them allows data, signals and/or information to be transmitted from the primary side circuit 10 to the secondary side circuit 30 so that the isolated integrated circuit 100 can operate normally.

In some embodiments, as shown in FIG. 1 , the primary side circuit 10 includes a carrier frequency generating circuit 11 , a carrier frequency control circuit 13 , a modulation circuit 15 , a buffer circuit 17 and a transmitting circuit 19 . Specifically, the modulation circuit 15 is electrically coupled to the carrier frequency generating circuit 11 , the buffer circuit 17 and the transmitting circuit 19 , and the carrier frequency control circuit 13 is electrically coupled to the carrier frequency generating circuit 11 . One end of the isolation circuit 20 is coupled to the transmitting circuit 19 of the primary circuit 10 through the output end of the primary circuit 10 . In addition, the secondary side circuit 30 includes a receiving circuit 31 and a demodulation circuit 33. The receiving circuit 31 is coupled to the other end of the isolation circuit 20 through the input end of the secondary side circuit 30 , and the demodulating circuit 33 is electrically coupled to the receiving circuit 31 .

Next, the operation of the primary circuit 10 is further explained with reference to Figures 1 and 2. Figure 2 is a timing diagram of some signals related to the operation of the primary circuit 10 according to some embodiments of the present disclosure.

In some embodiments, as shown in FIG. 1 , the primary side circuit 10 is used to receive an input signal Vin. Furthermore, as shown in Figure 2, the input signal Vin is a periodic signal, such as a pulse width modulation (PWM) signal, and has a period TC. Specifically, the frequency of the input signal Vin can be 100~1MHz, and the reciprocal of the frequency of the input signal Vin is the period TC.

In some embodiments, in each cycle TC, the input signal Vin is at the enabled level for a period of time and is at a disabled level for another period of time. In other words, as shown in Figure 2, each cycle TC of the input signal Vin has an enable period EA (corresponding to the input signal Vin of the enable level) and a disable period DA (corresponding to the input signal Vin of the disable level). ).

For clarity and convenience of explanation, in Figure 2, number indexes [1]~[4] are used to refer to individual components or signals respectively, but this is not intended to limit the number of the components or signals to a specific number. If only a component or signal symbol is used without specifying the index of the component or signal symbol, it means that the component or signal symbol refers to an unspecified member of the component or signal group to which it belongs. For example, cycle TC refers to any unspecified one of cycles TC[1]~TC[4].

In some embodiments, as shown in FIG. 1 , the carrier frequency generating circuit 11 is used to generate a carrier frequency signal Vosi. The carrier frequency signal Vosi is also a periodic signal, and in one embodiment, the frequency of the carrier frequency signal Vosi is approximately 500 MHz. It can be seen that the frequency of the carrier frequency signal Vosi is higher than the frequency of the input signal Vin. Specifically, the carrier frequency generating circuit 11 can be implemented by an oscillator.

In some embodiments, as shown in FIG. 1 , the modulation circuit 15 is used to receive the input signal Vin and the carrier frequency signal Vosi buffered by the buffer circuit 17 , and to output a signal based on the input signal Vin and the carrier frequency signal Vosi. The modulation signal Vmod is used by the transmitting circuit 19 to couple the modulation signal Vmod to the isolation circuit 20 . Specifically, the modulation circuit 15 can use the carrier frequency signal Vosi to modulate the input signal Vin to generate the modulation signal Vmod. As shown in FIG. 2 , during the enable period EA of the input signal Vin, the modulation circuit 15 controls the modulation signal Vmod to oscillate at the frequency of the carrier frequency signal Vosi according to the enable level input signal Vin. During the disabling period DA of the input signal Vin, the modulation circuit 15 controls the modulation signal Vmod to stop oscillating according to the input signal Vin at the disabling level.

From the above description of generating the modulation signal Vmod, it can be seen that when the input signal Vin is at the disabled level, the carrier frequency signal Vosi basically does not play any role in generating the modulation signal Vmod. However, in some related technologies, the carrier frequency signal is continuously output by the oscillator. That is to say, no matter whether the input signal is an enable level or a disable level, the oscillator will not stop outputting the carrier frequency signal, which leads to an increase in power consumption of the entire circuit in the related art.

In view of this, the present disclosure utilizes the carrier frequency control circuit 13 to control the carrier frequency generation circuit 11 at a possible level when the input signal Vin is at the disable level (that is, during the disable period DA in Figure 2). Stop outputting the carrier frequency signal Vosi within the adjusted time length.

In some embodiments, as shown in FIG. 1 , the carrier frequency control circuit 13 includes an edge detection circuit 131 , a timing pulse generation circuit 133 , a switch control circuit 135 and a delay judgment circuit 137 . The carrier frequency control circuit 13 is used to receive the input signal Vin through the edge detection circuit 131 . The timing pulse generating circuit 133 is electrically coupled to the edge detection circuit 131 . The switch control circuit 135 is electrically coupled to the carrier frequency generation circuit 11 , the edge detection circuit 131 , the timing pulse generation circuit 133 and the delay judgment circuit 137 . In addition, the delay judgment circuit 137 is electrically coupled to the edge detection circuit 131 and the timing pulse generation circuit 133 .

Next, the operation of the carrier frequency control circuit 13 is further explained with reference to Figures 2 and 3A~3B. Figure 3A illustrates the carrier frequency control circuit 13 during the enabling period EA of the input signal Vin according to some embodiments of the present disclosure. , and Figure 3B is a schematic diagram of the operation of the carrier frequency control circuit 13 during the disabling period DA of the input signal Vin according to some embodiments of the present disclosure.

In some embodiments, the input signal Vin is an enable level. Accordingly, as shown in FIG. 3A , the edge detection circuit 131 outputs a rising signal Vris according to the input signal Vin of the enable level. In other words, the edge detection circuit 131 outputs the rising signal Vris during the enabling period of the input signal Vin. The switch control circuit 135 controls the carrier frequency generating circuit 11 to output the carrier frequency signal Vosi according to the rising signal Vris. Specifically, after receiving the rising signal Vris, the switch control circuit 135 can generate an enable signal (not shown in the figure) to the carrier frequency generating circuit 11 . Then, the carrier frequency generating circuit 11 outputs the carrier frequency signal Vosi after receiving the enable signal. Therefore, as shown in Figure 2, during the enabling period EA of the input signal Vin, the carrier frequency generation circuit 11 outputs the carrier frequency signal Vosi for the modulation circuit 15 to control the modulation signal Vmod to oscillate at the frequency of the carrier frequency signal Vosi. .

In some embodiments, the input signal Vin is at a disabled level. Accordingly, as shown in FIG. 3B , the edge detection circuit 131 outputs a falling signal Vfal according to the input signal Vin of the disable level. In other words, the edge detection circuit 131 outputs the falling signal Vfal during the disabled period of the input signal Vin. In some embodiments, as shown in Figures 3A and 3B, the timing pulse generation circuit 133 is used to output a frequency filter signal Vtpl to the switch control circuit 135. As shown in Figures 2 and 3B, after receiving the falling signal Vfal, the timing pulse generating circuit 133 adjusts the voltage level of the frequency filter signal Vtpl to sequentially generate a first buffer pulse Ton1, a timing pulse Toff and a second Buffer pulse Ton2.

In some further embodiments, as shown in FIG. 2 , the frequency filter signal Vtpl is a reference voltage level during the enable period EA[1] of the input signal Vin. When entering the disable period DA[1] (that is, when the timing pulse generation circuit 133 receives the falling signal Vfal), the timing pulse generation circuit 133 changes the voltage level of the frequency filter signal Vtpl from the reference voltage at a first slope. The level is raised to a preset voltage level, and then the voltage level of the frequency filter signal Vtpl is dropped from the preset voltage level back to the reference voltage level to generate the first buffer pulse Ton1[1].

After generating the first buffer pulse Ton1[1], the timing pulse generating circuit 133 increases the voltage level of the frequency filter signal Vtpl from the reference voltage level to the preset voltage level at a second slope, and then The voltage level of the frequency filter signal Vtpl is reduced from the preset voltage level back to the reference voltage level to generate a timing pulse Toff[1].

After generating the timing pulse Toff[1], the timing pulse generation circuit 133 increases the voltage level of the frequency filter signal Vtpl from the reference voltage level to the preset voltage level at a third slope, and then changes the frequency The voltage level of the filter signal Vtpl is reduced from the preset voltage level back to the reference voltage level to generate a second buffer pulse Ton2[1].

In addition, after generating the second buffer pulse Ton2[1], the timing pulse generation circuit 133 maintains the voltage level of the frequency filter signal Vtpl at the reference voltage level until entering the disable period DA[2] (that is, After receiving the next falling signal Vfal), the timing pulse generation circuit 133 again adjusts the voltage level of the frequency filter signal Vtpl to sequentially generate the first buffer pulse Ton1[2], the timing pulse Toff[2], and the second buffer pulse. Ton2[2].

In some embodiments, the switch control circuit 135 controls the carrier frequency generation circuit 11 to output the carrier frequency signal Vosi according to the first buffer pulse Ton1, controls the carrier frequency generation circuit 11 to stop outputting the carrier frequency signal Vosi according to the timing pulse Toff, and controls the carrier frequency generation circuit 11 to stop outputting the carrier frequency signal Vosi according to the second buffer pulse. Ton2 controls the carrier frequency generating circuit 11 to output the carrier frequency signal Vosi. Accordingly, as shown in Figure 2, during the disabling period DA of the input signal Vin, the carrier frequency signal Vosi maintains output during the output period of the first buffer pulse Ton1, stops output during the output period of the timing pulse Toff, and then stops output during the output period of the timing pulse Toff. The output is resumed during the output period of the second buffer pulse Ton2. In addition, the carrier frequency signal Vosi still maintains output after the falling edge of the second buffer pulse Ton2.

It can be known from the above description of the first buffer pulse Ton1, the timing pulse Toff and the second buffer pulse Ton2 that each of the first buffer pulse Ton1, the timing pulse Toff and the second buffer pulse Ton2 can be a kind of ramp pulse. Accordingly, in some further embodiments, during the disable period DA of the input signal Vin, the switch control circuit 135 is used to count the number of ramp pulses it receives, and is used to count the number of ramp pulses it receives when receiving the second ramp pulse (ie, receiving When the timing pulse Toff is reached), the carrier frequency generating circuit 11 is controlled to stop outputting the carrier frequency signal Vosi.

In the above embodiment, as shown in Figure 2, the timing pulse generation circuit 133 generates the first buffer pulse Ton1, the timing pulse Toff and the second buffer pulse Ton2 through a single signal (ie, the frequency filter signal Vtpl) to the switch. Control circuit 135. However, this disclosure is not limited thereto. In some embodiments, the timing pulse generation circuit 133 generates the first buffer pulse Ton1, the timing pulse Toff, and the second buffer pulse Ton2 respectively through three independent signals to the switch control circuit 135. For example, when receiving the falling signal Vfal, the timing pulse generating circuit 133 adjusts the voltage level of the first signal to generate the first buffer pulse Ton1. After the first buffer pulse Ton1 is generated, the timing pulse generating circuit 133 adjusts the voltage level of the second signal to generate the timing pulse Toff. After the timing pulse Toff is generated, the timing pulse generating circuit 133 adjusts the voltage level of the third signal to generate the second buffer pulse Ton2.

In some embodiments, as shown in Figures 3A and 3B, the delay judgment circuit 137 is used to receive the frequency filter signal Vtpl from the timing pulse generation circuit 133, and to receive the rising signal Vris and falling signal Vfal from the edge detection circuit 131, And used to output a judgment signal Vjud to control the timing pulse generating circuit 133.

In some embodiments, as shown in Figure 2, the timing of the falling edge of the second buffer pulse Ton2[1] corresponding to the period TC[1] is located at the timing of the rising edge of the input signal Vin corresponding to the period TC[2]. (that is, before the start time of the enabling period EA[2]). Accordingly, the delay judgment circuit 137 will first detect the falling edge of the second buffer pulse Ton2[1] before receiving the rising signal Vris corresponding to the period TC[2]. When the falling edge of the second buffer pulse Ton2[1] is detected and the rising signal Vris corresponding to the period TC[2] has not been received, the delay judgment circuit 137 will adjust the voltage level of the judgment signal Vjud to generate a delay. The pulse Td[1] is sent to the timing pulse generating circuit 133. After receiving the delay pulse Td[1], the timing pulse generation circuit 133 will adjust the timing pulse Toff[2] corresponding to the period TC[2]. For example, as shown in FIG. 2 , the output period Pb[2] of the timing pulse Toff[2] is increased by the timing pulse generation circuit 133 and is longer than the output period Pb[1] of the timing pulse Toff[1].

By analogy with the above description, in the embodiment of FIG. 2, the delay judgment circuit 137 adjusts the voltage level of the judgment signal Vjud to generate a delay pulse Td[2] to control the timing pulse generation circuit 133 to increase the corresponding period TC[3]. The output period Pb[3] of the timing pulse Toff[3]; the delay judgment circuit 137 will adjust the voltage level of the judgment signal Vjud to generate the delay pulse Td[3] to control the timing pulse generation circuit 133 to increase the corresponding period TC[ 4] is the output period Pb[4] of the timing pulse Toff[4].

In some further embodiments, the output period Pb[2] of the timing pulse Toff[2] is the output period Pb[1] of the timing pulse Toff[1] plus the output period Pb[1] of the timing pulse Toff[1]; The output period Pb[3] of the timing pulse Toff[3] is the output period Pb[2] of the timing pulse Toff[2] plus the output period Pb[1] of the timing pulse Toff[1]; and the timing pulse Toff[4] The output period Pb[4] is the output period Pb[3] of the timing pulse Toff[3] plus the output period Pb[1] of the timing pulse Toff[1]. That is to say, the output period Pb of the timing pulse Toff corresponding to the next period TC is the output period Pb of the timing pulse Toff corresponding to the current period TC plus the output of the timing pulse Toff[1] corresponding to the first period TC[1]. Period Pb[1].

Furthermore, in some embodiments, the output period Pb[1] of the timing pulse Toff[1] is 1 times the output period of the first buffer pulse Ton1[1], and is the output period of the second buffer pulse Ton2[1]. 1 times. The output period Pb[2] of the timing pulse Toff[2] is twice the output period of the first buffer pulse Ton1[2], and is twice the output period of the second buffer pulse Ton2[2]. The output period Pb[3] of the timing pulse Toff[3] is three times the output period of the first buffer pulse Ton1[3], and is three times the output period of the second buffer pulse Ton2[3]. The output period Pb[4] of the timing pulse Toff[4] is four times the output period of the first buffer pulse Ton1[4] and four times the output period of the second buffer pulse Ton2[4]. It can be seen from this that regarding the timing pulse Toff, the first buffer pulse Ton1 and the second buffer pulse Ton2 corresponding to the same period TC, the output period Pb of the timing pulse Toff is M times the output period of the first buffer pulse Ton1 and is the third M times the output period of the second buffer pulse Ton2, where M is a positive integer.

Specifically, in some embodiments, the output period of the first buffer pulse Ton1 is 20~50 nanoseconds (ns), and the output period of the second buffer pulse Ton2 is 20~50 nanoseconds.

It should be understood that Pb may be excessively increased during the output of the timing pulse Toff at a time after the period TC[4], causing a situation to occur. In one case, the timing of the falling edge of the second buffer pulse Ton2 corresponding to the current period TC is after the timing of the rising edge (or rising signal Vris) of the input signal Vin of the next period TC. In such a case, the delay judgment circuit 137 will not generate the delay pulse Td to the timing pulse generation circuit 133, so that the output period Pb corresponding to the timing pulse Toff of the next period TC remains the same as the output period of the timing pulse Toff of the current period TC. Pb is the same.

In addition, due to some non-ideal factors, the carrier frequency control circuit 13 may cause the timing of the falling edge of the timing pulse Toff corresponding to the current period TC to be behind the timing of the rising edge (or rising signal Vris) of the input signal Vin of the next period TC. . In this case, the switch control circuit 135 receives the timing pulse Toff during the enable period EA. Even so, since the edge detection circuit 131 also outputs the rising signal Vris to the switch control circuit 135 in response to the enable period EA, the switch control circuit 135 still controls the carrier frequency generation circuit 11 to output the carrier frequency signal Vosi according to the rising signal Vris.

It can also be seen from the description of the embodiments in Figures 2 and 3A~3B that the carrier frequency control circuit 13 is used to detect the enable period EA and the disable period DA of the input signal Vin, and to control the carrier frequency generation during the enable period EA The circuit 11 outputs the carrier frequency signal Vosi, and is used to control the carrier frequency generating circuit 11 during the disable period DA to stop outputting the carrier frequency signal Vosi during the output period Pb of the timing pulse Toff.

It should be understood that the timing pulse Toff of the present disclosure is not limited to that shown in Figure 2 . In some embodiments, the timing pulse Toff has the same output period Pb in each cycle TC. Correspondingly, in some embodiments, the delay judgment circuit 137 in Figure 1 will be omitted.

In addition, the frequency filter signal Vtpl of the present disclosure is not limited to that shown in Figures 2 and 3B. In some embodiments, after receiving the falling signal Vfal, the timing pulse generating circuit 133 adjusts the voltage level of the frequency filter signal Vtpl to generate the timing pulse Toff. In other words, the first buffer pulse Ton1 and the second buffer pulse Ton2 will be omitted. Correspondingly, the delay judgment circuit 137 will generate or not generate the delay pulse Td to the timing pulse generation circuit 133 according to the falling edge of the timing pulse Toff.

In some embodiments, when the falling edge of the timing pulse Toff corresponding to the current period TC is detected and the rising signal Vris corresponding to the next period TC has not been received (that is, when the timing pulse Toff corresponding to the current period TC is not received) If the timing of the falling edge is before the timing of the rising edge of the input signal Vin corresponding to the next period TC), the delay judgment circuit 137 will adjust the voltage level of the judgment signal Vjud to generate a delay pulse Td to control the timing pulse generation circuit 133 increases the output period Pb of the timing pulse Toff corresponding to the next cycle TC.

In some embodiments, when the rising signal Vris corresponding to the next period TC is received but the falling edge of the timing pulse Toff corresponding to the current period TC has not been detected (that is, when the timing pulse Toff corresponding to the current period TC If the timing of the falling edge is after the timing of the rising edge of the input signal Vin corresponding to the next period TC), the delay judgment circuit 137 will not generate the delay pulse Td to the timing pulse generation circuit 133, so that the timing corresponding to the next period TC The output period Pb of the timing pulse Toff remains the same as the output period Pb of the timing pulse Toff of the current period TC. Furthermore, as explained above, although in this case the switch control circuit 135 receives the timing pulse Toff during the enable period EA, the switch control circuit 135 still controls the carrier frequency generation circuit 11 to output the carrier frequency signal Vosi according to the rising signal Vris.

To sum up, in the above embodiment, the output period Pb of the timing pulse Toff (for example: the output period Pb[1] of the timing pulse Toff[1]) and the enable period EA adjacent and located after the timing pulse Toff (for example: If the enable period EA[2]) does not overlap, the output period Pb of the next timing pulse Toff (for example: the output period Pb[2] of the timing pulse Toff[2]) will be adjusted.

Based on the above, when the output period Pb of the timing pulse Toff partially overlaps with the adjacent enable period EA located after the timing pulse Toff, the output period Pb of the next timing pulse Toff will not be adjusted. In addition, the time interval between the timing pulse Toff and the adjacent enable period EA located after the timing pulse Toff is shorter than the output period of the second buffer pulse Ton2 (that is, the output period of the second buffer pulse Ton2 corresponding to the current period TC If the timing of the falling edge is after the timing of the rising edge of the input signal Vin corresponding to the next period TC), the output period Pb of the next timing pulse Toff will not be adjusted.

Please refer to Figures 1 and 4 together. Figure 4 is a schematic diagram of the modulation signal Vmod and the output signal Vout according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 1 , the isolation circuit 20 is used to couple and transmit the modulation signal Vmod from the primary side circuit 10 to the secondary side circuit 30 so that the secondary side circuit 30 generates an output signal Vout. Specifically, the receiving circuit 31 receives and transmits a signal that is substantially the same as the modulation signal Vmod to the demodulation circuit 33, and the demodulation circuit 33 demodulates the signal that is substantially the same as the modulation signal Vmod to generate the output signal Vout. It can be seen from this that the secondary side circuit 30 generates the output signal Vout according to the modulation signal Vmod. Furthermore, in some embodiments, as shown in Figures 2 and 4, the waveform of the output signal Vout is substantially the same as the waveform of the input signal Vin.

Please refer to FIG. 5 , which is a flow chart of a modulation signal generating method 500 according to some embodiments of the present disclosure. In some embodiments, the modulation signal generating method 500 may be performed by the isolated integrated circuit 100 of FIG. 1 . As shown in FIG. 5 , the modulation signal generating method 500 includes steps S501 to S504.

In step S501, the carrier frequency control circuit 13 detects at least one enabling period EA and at least one disabling period DA of the input signal Vin. In some embodiments, the carrier frequency control circuit 13 detects the enable period EA and the disable period DA of the input signal Vin through the edge detection circuit 131 . Specifically, as shown in Figures 3A and 3B, the edge detection circuit 131 is used to output the rising signal Vris in response to the enable period of the input signal Vin, and to output the falling signal DA in response to the disable period of the input signal Vin. Vfal.

In step S502, during at least an enabling period EA, the carrier frequency control circuit 13 controls the carrier frequency generation circuit 11 to output the carrier frequency signal Vosi. In some embodiments, as shown in Figures 2 and 3A, the switch control circuit 135 in the carrier frequency control circuit 13 controls the carrier frequency generation circuit 11 to output the carrier frequency signal Vosi according to the rising signal Vris.

In step S503, during at least one disable period DA, the carrier frequency control circuit 13 controls the carrier frequency generating circuit 11 to stop outputting the carrier frequency signal Vosi during at least one output period Pb of the timing pulse Toff. In some embodiments, as shown in Figures 2 and 3B, the timing pulse generation circuit 133 in the carrier frequency control circuit 13 adjusts the voltage level of the frequency filter signal Vtpl according to the falling signal Vfal to sequentially generate the first buffer pulses Ton1, Ton1, The timing pulse Toff and the second buffer pulse Ton2 are sent to the switch control circuit 135, so that the switch control circuit 135 controls the carrier frequency generating circuit 11 to stop outputting the carrier frequency signal Vosi during the output period Pb of the timing pulse Toff.

In step S504, the modulation circuit 15 generates the modulation signal Vmod according to the input signal Vin and the carrier frequency signal Vosi. In some embodiments, as shown in Figures 1 and 2, the modulation circuit 15 controls the modulation signal Vmod according to the enable level of the input signal Vin (ie, during the enable period EA of the input signal Vin) to carry The frequency signal Vosi oscillates at the frequency, and the modulation signal Vmod is controlled to stop oscillating according to the input signal Vin at the disabled level (that is, during the disabled period DA of the input signal Vin).

For the rest of the description from step S501 to step S504, please refer to the above description of the isolated integrated circuit 100, so they will not be described again here.

It can be seen from the above embodiments of the present disclosure that the carrier frequency control circuit 13 of the present disclosure detects the enable period EA and the disable period DA of the input signal Vin, and controls the carrier frequency generating circuit during the disable period DA of the input signal Vin. 11 During the output period of the timing pulse Toff, Pb stops outputting the carrier frequency signal Vosi. Therefore, compared with related technologies that do not stop outputting the carrier frequency signal during the disabling period of the input signal, the isolated integrated circuit 100 of the present disclosure has lower power consumption.

Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Those with ordinary skill in the technical field can make various modifications and modifications without departing from the spirit and scope of the present disclosure. Therefore, this disclosure The scope of protection of the disclosed content shall be determined by the scope of the patent application attached.

10: Primary side circuit 11: Carrier frequency generation circuit 13:Carrier frequency control circuit 15: Modulation circuit 17:Buffer circuit 19: Transmitting circuit 20:Isolation circuit 30: Secondary side circuit 31: Receiving circuit 33: Demodulation circuit 100:Isolated integrated circuit 131: Edge detection circuit 133: Timing pulse generation circuit 135: Switch control circuit 137: Delay judgment circuit 500: Modulation signal generation method DA: period of disablement EA: enabling period GND1: first ground voltage GND2: second ground voltage Pb: output period S501~S504: steps TC: cycle Td: delayed pulse Toff: timing pulse Ton1: first buffer pulse Ton2: second buffer pulse VCC1: first power supply voltage VCC2: Second power supply voltage Vfal: falling signal Vin: input signal Vjud: Judgment signal Vmod: Modulation signal Vosi: carrier frequency signal Vout: output signal Vris: rising signal Vtpl: frequency filter signal

Figure 1 is a block diagram of an isolated integrated circuit according to some embodiments of the present disclosure. Figure 2 is a timing diagram illustrating some signals related to the operation of the primary circuit according to some embodiments of the present disclosure. FIG. 3A is a schematic diagram illustrating the operation of a carrier frequency control circuit during an enable period of an input signal according to some embodiments of the present disclosure. Figure 3B is a schematic diagram illustrating the operation of the carrier frequency control circuit during the disabling period of the input signal according to some embodiments of the present disclosure. FIG. 4 is a schematic diagram of a modulation signal and an output signal according to some embodiments of the present disclosure. FIG. 5 is a flow chart illustrating a modulation signal generation method according to some embodiments of the present disclosure.

10: Primary side circuit

11: Carrier frequency generation circuit

13:Carrier frequency control circuit

15: Modulation circuit

17:Buffer circuit

19: Transmitting circuit

20:Isolation circuit

30: Secondary side circuit

31: Receiving circuit

33: Demodulation circuit

100:Isolated integrated circuit

131: Edge detection circuit

133: Timing pulse generation circuit

135: Switch control circuit

137: Delay judgment circuit

GND1: first ground voltage

GND2: second ground voltage

VCC1: first power supply voltage

VCC2: Second power supply voltage

Vin: input signal

Vmod: Modulation signal

Vosi: carrier frequency signal

Vout: output signal

Claims (10)

An isolated integrated circuit includes: a primary side circuit, including: a carrier frequency generating circuit for generating a carrier frequency signal; a carrier frequency control circuit electrically coupled to the carrier frequency generating circuit and including An edge detection circuit, a timing pulse generation circuit and a switch control circuit, wherein the timing pulse generation circuit is electrically coupled to the edge detection circuit, and the switch control circuit is electrically coupled to the carrier frequency generation circuit, the An edge detection circuit and the timing pulse generation circuit. The edge detection circuit is used to detect at least an enabling period and at least a disabling period of an input signal. The switch control circuit is used to control the carrier during the at least enabling period. The frequency generating circuit outputs the carrier frequency signal, and is used to control the carrier frequency generating circuit to stop outputting the carrier frequency signal during the output period of at least one timing pulse during the at least one disable period, wherein the at least one timing pulse is in response to detecting Entering the at least one disable period is generated by the timing pulse generating circuit, and during the output period of one of the at least one timing pulses and the at least one enabling period adjacent to and located after the at least one of the timing pulses If one does not overlap, the output period of the next one of the at least one timing pulse will be adjusted; and a modulation circuit electrically coupled to the carrier frequency generating circuit for receiving the input signal and The carrier frequency signal is used to output a modulation signal according to the input signal and the carrier frequency signal; an isolation circuit is coupled to the primary side circuit and is used to transmit the modulation signal; and A secondary side circuit is coupled to the isolation circuit, used to receive the modulation signal through the isolation circuit, and used to generate an output signal according to the modulation signal. The isolated integrated circuit of claim 1, wherein: the edge detection circuit is used to output at least one rising signal during the at least one enabling period, and to output at least one falling signal during the at least one disabling period; wherein The timing pulse generating circuit is used to output a frequency filter signal, and is used to adjust the voltage level of the frequency filter signal according to the at least one falling signal to generate the at least one timing pulse; wherein the switch control circuit is used to generate the at least one timing pulse according to the at least one rising signal. The signal controls the carrier frequency generating circuit to output the carrier frequency signal, and is used to control the carrier frequency generating circuit to stop outputting the carrier frequency signal according to the at least one timing pulse; wherein the carrier frequency control circuit also includes a delay judgment circuit, and the delay The judgment circuit is electrically coupled to the edge detection circuit and the timing pulse generation circuit, and is used to output a judgment signal according to the frequency filter signal, the at least one rising signal and the at least one falling signal to control the timing pulse generation circuit. The isolated integrated circuit of claim 2, wherein the at least one timing pulse includes a current timing pulse corresponding to a current cycle of the input signal, and the at least one rising signal includes a next cycle corresponding to the current cycle. rising signals one by one; When a falling edge of the current timing pulse is detected and the next rising signal has not been received, the delay judgment circuit adjusts the voltage level of the judgment signal to generate a delay pulse to control the timing pulse generation circuit. Increase the output period of the next timing pulse corresponding to the next period in the at least one timing pulse. The isolated integrated circuit of claim 2, wherein the timing pulse generating circuit is used to adjust the voltage level of the frequency filter signal according to the at least one falling signal to sequentially generate at least one first buffer pulse, the at least one Timing pulses and at least one second buffer pulse; wherein the switch control circuit is used to control the carrier frequency generation circuit to output the carrier frequency signal based on the at least one first buffer pulse, and is used to control the carrier frequency signal based on the at least one second buffer pulse. The frequency generating circuit outputs the carrier frequency signal. The isolated integrated circuit of claim 4, wherein the at least one second buffer pulse includes a current second buffer pulse corresponding to a current cycle of the input signal, and the at least one rising signal includes a current second buffer pulse corresponding to the current cycle. The next rising signal in the next cycle; when a falling edge of the current second buffer pulse is detected and the next rising signal has not been received, the delay judgment circuit adjusts the voltage level of the judgment signal A delay pulse is generated to control the timing pulse generating circuit to increase the output period of the next timing pulse corresponding to the next cycle in the at least one timing pulse. A carrier frequency control circuit is electrically coupled to a carrier frequency generating circuit for receiving an input signal, and includes: an edge detection circuit for detecting at least one enable period and at least one disable function of the input signal. period, for outputting at least one rising signal during the at least one enabling period, and for outputting at least one falling signal during the at least one disabling period; a timing pulse generating circuit electrically coupled to the edge detection circuit, for Output a frequency filter signal, and adjust the voltage level of the frequency filter signal according to the at least one falling signal to generate at least one timing pulse, wherein the output period of one of the at least one timing pulse is adjacent to and located at the at least If one of the at least one enabling period after the one of the timing pulses does not overlap, the output period of the next one of the at least one timing pulse will be adjusted; and a switch control circuit electrically coupled to The carrier frequency generating circuit, the edge detection circuit and the timing pulse generating circuit are used to control the carrier frequency generating circuit to output a carrier frequency signal during at least one disabling period, and to control the carrier frequency signal during at least one disabling period. The frequency generator stops outputting the carrier frequency signal during the output period of the at least one timing pulse. The carrier frequency control circuit of claim 6, wherein the at least one timing pulse includes a current timing pulse corresponding to a current cycle of the input signal, and the input signal includes a next timing pulse corresponding to the next cycle after the current cycle. rising edge; wherein the timing of a falling edge of the current timing pulse is located on the next Before the timing of the rising edge, the timing pulse generating circuit increases the output period of the next timing pulse corresponding to the next period in the at least one timing pulse, so that the output period of the next timing pulse is longer than the output period of the current timing pulse. The output period is long. The carrier frequency control circuit as claimed in claim 6, wherein the timing pulse generating circuit is used to adjust the voltage level of the frequency filter signal according to the at least one falling signal to sequentially generate at least one first buffer pulse, the at least one timing pulse pulse and at least one second buffer pulse; wherein the switch control circuit is used to control the carrier frequency generation circuit to output the carrier frequency signal based on the at least one first buffer pulse, and is used to control the carrier frequency based on the at least one second buffer pulse The generating circuit outputs the carrier frequency signal. The carrier frequency control circuit of claim 8, wherein the at least one second buffer pulse includes a current second buffer pulse corresponding to a current cycle of the input signal, and the input signal includes a next next buffer pulse corresponding to the current cycle. The next rising edge of the cycle; when the timing of a falling edge of the current second buffer pulse is before the timing of the next rising edge, the timing pulse generating circuit increases the timing pulse corresponding to the next cycle. during the output of the next timing pulse. The carrier frequency control circuit as described in claim 6 further includes: a delay judgment circuit electrically coupled to the edge detection circuit and the timing A pulse generating circuit, and is used to output a judgment signal according to the frequency filter signal, the at least one rising signal and the at least one falling signal to control the timing pulse generating circuit; wherein the delay judgment circuit is also used to adjust the voltage level of the judgment signal Generating at least one delay pulse controls the timing pulse generating circuit to adjust the output period of the at least one timing pulse.

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