TWM643437U - Voltage conversion system - Google Patents

Abstract

A voltage conversion system includes a multi-phase voltage converter and a controller. The multi-phase voltage converter is coupled to a load and includes a first phase circuit, a second phase circuit, a third phase circuit, and at least one driver circuit. The first phase circuit, the second phase circuit, and the third phase circuit have a charging state in sequence during a first period. The at least one driver circuit is coupled to the first phase circuit, the second phase circuit, the third phase circuit. The controller is coupled to the at least one driver circuit. The controller outputs at least one driving signal to the at least one driver circuit such that the at least one driver circuit adjusts the second phase circuit or the third phase circuit to be a first-working item according to a trigger event.

Description

voltage conversion system

The present disclosure relates to technologies related to phase-shedding, in particular to a voltage conversion system capable of automatic phase-shedding.

With the advancement of technology, various integrated circuits have been developed. For example, the voltage converter can provide current to the output terminal to supply power to the back-end load, wherein the multi-phase voltage converter includes multiple sets of power switch groups to adaptively supply power to the back-end load. However, how to improve the reliability of the multi-phase voltage converter is one of the important issues in this field.

Some embodiments of the present disclosure relate to a voltage conversion system. The voltage conversion system includes a multi-phase voltage converter and a controller. The multi-phase voltage converter is coupled to a load and includes a first phase circuit, a second phase circuit, a third phase circuit and at least one driving circuit. The first phase circuit, the second phase circuit and the third phase circuit have a charging state sequentially in a first period. At least one driving circuit is coupled to the first phase circuit, the second phase circuit and the third phase circuit. The controller is coupled to at least one driving circuit. The controller outputs at least one driving signal to at least one driving circuit according to a trigger event so that the at least one driving circuit adjusts the second phase circuit or the third phase circuit as a front work item in a second period after the first period.

As used herein, the term "coupled" may also refer to "electrically coupled", and the term "connected" may also refer to "electrically connected". "Coupled" and "connected" may also mean that two or more elements cooperate or interact with each other.

Refer to Figure 1. FIG. 1 is a schematic diagram of a voltage conversion system 100 according to some embodiments of the present disclosure.

The voltage conversion system 100 includes a multi-phase voltage converter 110 , a controller 120 and a detection circuit 130 . The multi-phase voltage converter 110 is coupled between the input voltage VIN, the controller 120 and the load LD. In this example, the multi-phase voltage converter 110 is a multi-phase step-down (buck) converter, and the multi-phase voltage converter 110 can provide the total current IOUT_TOTAL to the load LD.

The multi-phase voltage converter 110 includes a plurality of driving circuits D1 - D8 and a plurality of phase circuits 111 - 118 . The driving circuits D1 - D8 are respectively coupled to the phase circuits 111 - 118 . The phase circuits 111 - 118 are coupled to the load LD. Each of the phase circuits 111 - 118 includes a high-side switch HS, a low-side switch LS, an inductor L, and a capacitor CO.

Taking the phase circuit 111 as an example, the first end of the high-bridge switch HS is used to receive the input voltage VIN. The second terminal of the high-bridge switch HS is coupled to the first terminal of the low-bridge switch LS and coupled to the first terminal of the inductor L. The second end of the low bridge switch LS is coupled to the ground. The control terminal of the high-bridge switch HS and the control terminal of the low-bridge switch LS are coupled to the driving circuit D1. The driving circuit D1 can turn on or turn off the high-side switch HS or the low-side switch LS. The second end of the inductor L is coupled to the first end of the capacitor CO and the load LD. The second end of the capacitor CO is coupled to the ground. Since the other phase circuits 112 - 118 have similar circuit structures, details are not repeated here. To explain in another way, the phase circuits 111 - 118 are coupled in parallel.

The controller 120 can send out driving signals PWM1-PWM8 according to the setting signal SET and transmit these driving signals PWM1-PWM8 to the driving circuits D1-D8 respectively. The driving signals PWM1-PWM8 are pulse width modulation (PWM) signals.

Taking the driving circuit D1 as an example, the driving circuit D1 can receive the driving signal PWM1 from the controller 120 and turn on or off the high-side switch HS and the low-side switch LS in the phase circuit 111 according to the driving signal PWM1 . For example, when the driving signal PWM1 has a high logic value (for example: high potential or logic value 1), the driving circuit D1 turns on the high-side switch HS in the phase circuit 111 and turns off the low-side switch LS in the phase circuit 111 . When the driving signal PWM1 has a low logic value (for example, low potential or logic value 0), the driving circuit D1 turns off the high-side switch HS in the phase circuit 111 and turns on the low-side switch LS in the phase circuit 111 . When the driving signal PWM1 has a medium logic value (eg, a medium potential between high and low), the driving circuit D1 turns off the high-side switch HS in the phase circuit 111 and the low-side switch LS in the phase circuit 111 . By controlling the operation of the phase circuit 111 by the driving circuit D1, the phase circuit 111 can provide a current (for example: the detection current I1 in FIG. 2 ) to the load LD. Since the other driving circuits D2-D8 have similar circuit operations, they will not be repeated here. The coordinated operation of the phase circuits 111 - 118 is controlled by the driving circuits D1 - D8 to provide the total current IOUT_TOTAL to the load LD.

In some embodiments, the controller 120 may be implemented by using an Application Specific Integrated Circuit (ASIC). Specifically, the controller 120 can be realized by using an analog circuit, a digital circuit or a combination thereof.

It is particularly noted here that the number of driving circuits and phase circuits in FIG. 1 (the number in FIG. 1 is 8) is for illustrative purposes only. Various other suitable quantities are within the scope of the present disclosure.

In some embodiments, the detection circuit 130 can detect the currents of the phase circuits 111 - 118 to generate detection currents I1 - I8 respectively and send the detection currents I1 - I8 back to the controller 120 . In some embodiments, the detection circuit 130 can further add all the detection currents I1˜I8 to generate the total current IOUT_TOTAL and send the total current IOUT_TOTAL back to the controller 120 . In some embodiments, the detection circuit 130 can detect the temperatures of the phase circuits 111 - 118 to generate detected temperatures T1 - T8 correspondingly, and send the detected temperatures T1 - T8 back to the controller 120 .

It is particularly noted here that, in some other embodiments, the detection circuit 130 may be disposed inside the controller 120 .

Refer to Figure 2. FIG. 2 is a schematic diagram illustrating the operation of the controller 120 according to some embodiments of the present disclosure.

The controller 120 includes a feedback signal circuit 121 , a system command receiving circuit 122 , a phase management circuit 123 and a pulse width modulation circuit 124 . The feedback signal circuit 121 and the system command receiving circuit 122 are coupled to the phase management circuit 123 . The phase management circuit 123 is coupled to the pulse width modulation circuit 124 .

Taking the example in FIG. 2 as an example, the feedback signal circuit 121 can generate the control signal CS1 according to the total current IOUT_TOTAL from the detection circuit 130 , the detection currents I1-I8 or the detection temperatures T1-T8.

The system command receiving circuit 122 can receive commands from the system. Taking the example in FIG. 2 as an example, the system command receiving circuit 122 can receive the power saving mode command LP1 to enter a low-power state or receive the power saving mode command LP2 to enter a sleep state. The system command receiving circuit 122 can generate the control signal CS2 according to the power saving mode command LP1 and the power saving mode command LP2 .

The phase management circuit 123 can generate the phase management signal CS3 according to the control signal CS1, the control signal CS2 or the setting signal SET and transmit the phase management signal CS3 to the pulse width modulation circuit 124, so that the pulse width modulation circuit 124 generates the driving signals PWM1-PWM8 and respectively transmits the driving signals PWM1-PWM8 to the driving circuits D1-D8.

In this disclosure, the controller 120 can change the working order of the phase circuits 111 - 118 according to a trigger event. The different trigger events in FIG. 3 , FIG. 4 and FIG. 5 will be described below.

Refer to Figure 1, Figure 2 and Figure 3 together. FIG. 3 is a timing diagram of a non-power-saving mode according to some embodiments of the present disclosure. In some embodiments, when both the power saving mode command LP1 and the power saving mode command LP2 in FIG. 2 are logic low, it means that the system is in a non-power saving mode (normal mode).

Taking the example in FIG. 3 as an example, each of the driving signals PWM1 - PWM8 may have at least one pulse. The pulses correspond to a high logic value and a low logic value. For example, as mentioned above, when the driving signal PWM1 has a high logic value, the driving circuit D1 turns on the high-side switch HS in the phase circuit 111 and turns off the low-side switch LS in the phase circuit 111 to control the phase circuit 111 to have a charging state. When the driving signal PWM1 has a low logic value, the driving circuit D1 turns off the high-side switch HS in the phase circuit 111 and turns on the low-side switch LS in the phase circuit 111 to control the phase circuit 111 to have a discharge state. When the driving signal PWM1 has a middle logic value, the driving circuit D1 turns off the high-side switch HS in the phase circuit 111 and the low-side switch LS in the phase circuit 111 to control the phase circuit 111 to be in an off state. The other driving signals PWM2-PWM8 and the other phase circuits 112-118 have similar operations, so they are not repeated here.

In the period P1, since the driving signals PWM1-PWM8 have pulses sequentially, the phase circuits 111-118 will enter the charging state sequentially. That is, the phase circuit 111 is the first work item, the phase circuit 112 is the second work item, and so on.

At the time point TP1 in the period P1, when the system enables the automatic phase cut mechanism, the automatic phase cut enable signal APS_EN changes from a low logic value to a high logic value, indicating that the automatic phase cut mechanism is enabled. At this time, the detection circuit 130 detects the current (for example: the detection currents I1-I8 in FIG. 2 ) or the temperature (for example: the detection temperatures T1-T8 in FIG. 2 ) of the circuits 111-118 of each phase, and generates a detection result DR according to the maximum current or the maximum temperature therein.

In application, when the total current IOUT_TOTAL drops, some phase circuits can be turned off to reduce the number of work items. Taking the example in FIG. 3 as an example, if the phase circuit 115 has the maximum current or the highest temperature as an example, the controller 120 will control the next phase circuit 116 to be the new first work item (i.e., the first work item) in the cycle P2 (and subsequent cycles), and the next phase circuit 117 to be the new second work item, and so on. That is to say, in the period P2 (and subsequent periods), the next driving signal PWM6 is the first pulse, and the next driving signal PWM7 is the second pulse, and so on. Accordingly, in period P2 (and subsequent periods), the next phase circuit 116 is the first to have a charging state, and the next phase circuit 117 is the second to have a charging state, and so on. After the above adjustment sequence, the driving signal PWM5 corresponding to the maximum current or the maximum temperature remains at a low logic value in the period P2. The driving circuit D5 controls the phase circuit 115 to maintain a discharge state according to the driving signal PWM5.

In the period P3, the next phase circuit 116 is still the new first work item, the next next phase circuit 117 is the new second work item, and so on. That is to say, in the period P3, the driving signal PWM6 is still the first pulse, and the next driving signal PWM7 is the second pulse, and so on. That is to say, in the period P3, the phase circuit 116 is still the first to have the charging state, the phase circuit 117 is still the second to have the charging state, and so on. The previous driving signal PWM4 of the last driving signal PWM5 maintains a low logic value in the period P3. The driving circuit D4 controls the phase circuit 114 to maintain the discharge state according to the driving signal PWM4. The controller 120 controls the driving signal PWM5 to change from a low logic value to a middle logic value in the period P3. The driving circuit D5 controls the phase circuit 115 to remain in the off state according to the driving signal PWM5. That is, the phase circuit 115 corresponding to the highest current or highest temperature will be turned off. Subsequent cycles have similar operations (the phase circuit 114 will be turned off in the next cycle), so details will not be repeated here.

The following will take the driving signal PWM4 as an example to illustrate the release mechanism of the off state. Under the condition that the internal threshold of the controller 120 (switching from four phases to three phases) is 50 amperes and the hysteresis value is 2 amperes, when the detection current I4 is lower than 50 amperes, the driving signal PWM4 is at a middle logic value. When the detection current I4 is higher than 52 amperes, the driving signal PWM4 will change from a middle logic value to a low logic value, and will not turn to a high logic value until the next charging is required. Another situation is that when the automatic phase-cut enabling signal APS_EN becomes a low logic value, the driving signal PWM4 will change from a middle logic value to a low logic value, and will not turn to a high logic value until the next charging is required.

Refer to Figure 1, Figure 2 and Figure 4 together. FIG. 4 is a timing diagram of a sequential definition method of a power saving mode according to some embodiments of the present disclosure.

In the period S1, since the driving signals PWM1-PWM8 have pulses sequentially in the period P1, the phase circuits 111-118 are in a charging state sequentially. That is, the phase circuit 111 is the first work item, the phase circuit 112 is the second work item, and so on.

In the period S2, the driving signal PWM1 is still the first to have a pulse, the driving signal PWM2 is still the second to have a pulse, and so on.

However, at the time point TP2 in the cycle S2, the power saving mode command LP1 or the power saving mode command LP2 changes from a low logic value to a high logic value and the normal mode command NORMAL changes from a high logic value to a low logic value, which means that the system enters the power saving mode (low power consumption mode or sleep mode).

Between the time point TP2 and the time point TP2' (the power-saving period), the controller 120 controls only the driving signal PWM2 of the second working item in the original cycle S1 to have a pulse, and the other driving signals PWM1 and PWM3-PWM8 maintain a middle logic value. That is, there will only be a single work item left during the power save period. Accordingly, the driving circuit D2 controls the phase circuit 112 to have a charging state according to the driving signal PWM2. The other driving circuits D1 and D3-D8 control the phase circuits 111 and 113-118 to remain in the off state according to the driving signals PWM1 and PWM3-PWM8 respectively.

After the time point TP2', taking the system back to the normal mode as an example, the controller 120 defines the phase circuit 112 of the second work item in the original cycle S1 as the new first work item according to the charging sequence in the cycle S1, defines the next phase circuit 113 as the new second work item, and so on, and the phase circuit 111 is the last work item (that is, the last work item). For example, at the time point TP2', the power saving mode command LP1 or the power saving mode command LP2 changes from a high logic value to a low logic value and the normal mode command NORMAL changes from a low logic value to a high logic value, which means that the system leaves the power saving mode (low power consumption mode or sleep mode). Next, the controller 120 controls the driving circuits D1 - D8 according to the newly defined sequence of work items.

In the period S3, the driving signal PWM2 of the new first working item is the first pulse, the driving signal PWM3 of the new second working item is the second pulse, and so on.

However, taking the time point TP3 in the period S3 to enter the power saving mode again as an example, the power saving mode command LP1 or the power saving mode command LP2 changes from a low logic value to a high logic value again and the normal mode command NORMAL changes from a high logic value to a low logic value, which means that the system enters the power saving mode again.

Between the time point TP3 and the time point TP3' (the power-saving period), the controller 120 controls only the driving signal PWM3 of the third working item in the original cycle S1 to have a pulse, and the other driving signals PWM1-PWM2 and PWM4-PWM8 maintain a middle logic value. That is, there will only be a single work item left during the power save period. Accordingly, the driving circuit D3 controls the phase circuit 113 to have a charging state according to the driving signal PWM3. The other driving circuits D1~D2 and D4~D8 control the phase circuits 111~112 and 114~118 to remain in the off state according to the driving signals PWM1~PWM2 and PWM4~PWM8 respectively.

After the time point TP3', taking the system back to the normal mode as an example, the controller 120 defines the phase circuit 113 of the third work item in the original cycle S1 as the new first work item according to the charging sequence in the cycle S1, defines the next phase circuit 114 as the new second work item, and so on, and the phase circuit 112 is the last work item. For example, at the time point TP3', the power saving mode command LP1 or the power saving mode command LP2 changes from a high logic value to a low logic value and the normal mode command NORMAL changes from a low logic value to a high logic value, which means that the system leaves the power saving mode (low power consumption mode or sleep mode). Next, the controller 120 controls the driving circuits D1 - D8 according to the newly defined sequence of work items.

Since other subsequent cycles have similar operations, details are not repeated here. In the embodiment of FIG. 4, in the power-saving mode, one of the phase circuits 112-118 and 111 is controlled to be in a non-closed state according to the charging sequence (work item sequence) in the cycle S1, and the other phase circuits are controlled to be kept in a closed state, so it is called "sequential definition method".

Refer to Figure 1, Figure 2 and Figure 5 together. FIG. 5 is a timing diagram of a random definition method of a power saving mode according to some embodiments of the present disclosure.

In the period K1, since the driving signals PWM1-PWM8 have pulses sequentially in the period P1, the phase circuits 111-118 are in the charging state sequentially. That is, the phase circuit 111 is the first work item, the phase circuit 112 is the second work item, and so on.

In the period K2, the phase circuit 111 is still the first to have a pulse, the driving signal PWM2 is still the second to have a pulse, and so on.

However, at the time point TP4 in the cycle K2, the power saving mode command LP1 or the power saving mode command LP2 changes from a low logic value to a high logic value and the normal mode command NORMAL changes from a high logic value to a low logic value, which means that the system enters the power saving mode.

Since the phase circuit 115 is the currently working phase circuit at the time point TP4 when it turns into the power saving mode, the controller 120 controls only the driving signal PWM5 for driving the current working phase circuit 115 to have pulses between the time point TP4 and the time point TP4' (power saving period), and the other driving signals PWM1~PWM4 and PWM6~PWM8 maintain a middle logic value. That is, there will only be a single work item left during the power save period. Accordingly, the driving circuit D5 controls the phase circuit 115 to have a charging state according to the driving signal PWM5. The other driving circuits D1-D4 and D6-D8 control the phase circuits 111-114 and 116-118 to be kept in the off state according to the driving signals PWM1-PWM4 and PWM6-PWM8 respectively.

After the time point TP4', taking the system back to the normal mode as an example, the controller 120 defines the phase circuit 115 as the new first work item, defines the next phase circuit 116 as the new second work item, and so on, and the phase circuit 114 is the last work item. For example, at the time point TP4', the power saving mode command LP1 or the power saving mode command LP2 changes from a high logic value to a low logic value and the normal mode command NORMAL changes from a low logic value to a high logic value, which means that the system leaves the power saving mode (low power consumption mode or sleep mode). Next, the controller 120 controls the driving circuits D1 - D8 according to the newly defined sequence of work items.

In the period K3, the driving signal PWM5 of the new first working item is the first to have a pulse, the driving signal PWM6 of the new second working item is the second to have a pulse, and so on.

However, taking the time point TP5 in the period K3 to enter the power saving mode again as an example, the power saving mode command LP1 or the power saving mode command LP2 changes from a low logic value to a high logic value again and the normal mode command NORMAL changes from a high logic value to a low logic value, which means that the system enters the power saving mode again.

Since the phase circuit 117 is the currently working phase circuit at the time point TP5 when it turns into the power-saving mode again, the controller 120 controls only the driving signal PWM7 for driving the currently working phase circuit 117 to have pulses between the time point TP5 and the time point TP5' (power-saving period), while the other driving signals PWM1-PWM6 and PWM8 remain at the middle logic value. That is, there will only be a single work item left during the power save period. Accordingly, the driving circuit D7 controls the phase circuit 117 to have a charging state according to the driving signal PWM7. The other driving circuits D1 ˜ D6 and D8 control the phase circuits 111 ˜ 116 and 118 to remain in the off state according to the driving signals PWM1 ˜ PWM6 and PWM8 respectively.

After the time point TP5', taking the system back to the normal mode as an example, the controller 120 defines the phase circuit 117 as the new first work item, defines the next phase circuit 118 as the new second work item, and so on, and the phase circuit 116 is the last work item. For example, at the time point TP5', the power saving mode command LP1 or the power saving mode command LP2 changes from a high logic value to a low logic value and the normal mode command NORMAL changes from a low logic value to a high logic value, which means that the system leaves the power saving mode (low power consumption mode or sleep mode). Next, the controller 120 controls the driving circuits D1 - D8 according to the newly defined sequence of work items.

Since other subsequent cycles have similar operations, details are not repeated here. In the embodiment of FIG. 5, in the power-saving mode, the currently working phase circuit (for example: phase circuit 115 or phase circuit 117) is controlled to have a non-closed state according to the time point when the power-saving mode command LP1 or the power-saving mode command LP2 changes from a low logic value to a high logic value (for example: time point TP4 or time point TP5), and the other phase circuits are controlled to remain in the closed state, so it is called "random definition method".

In some related technologies, in the non-power-saving mode, the first-to-last phase circuit, the second-to-last phase circuit (and so on) are sequentially controlled to be closed, and the first phase circuit is controlled to be non-closed. In the power-saving mode, other phase circuits other than the first phase circuit are controlled to be in an off state, and the first phase circuit is controlled to be in a non-off state. In these related technologies, the first phase circuit will be continuously kept in a non-closed state, so the usage rate of the first phase circuit is much higher than that of other phase circuits. This may reduce the reliability of the multiphase voltage converter.

Compared with the related technologies mentioned above, no matter in the non-power-saving mode or the power-saving mode in the present disclosure, each of the phase circuits 111 - 118 may be in a non-off state. That is to say, the usage rates of the phase circuits 111 - 118 are relatively average. Accordingly, the reliability of the multi-phase voltage converter 110 can be improved.

Refer to Figure 6. FIG. 6 is a flowchart of a control method 600 according to some embodiments of the present disclosure. The control method 600 includes operation S610 and operation S620.

In some embodiments, the control method 600 can be applied to the voltage conversion system 100 in FIG. 1 , but the disclosure is not limited thereto. For ease of understanding, the control method 600 will be described below with reference to FIG. 1 .

In operation S610 , the plurality of phase circuits 111 - 118 in the multi-phase voltage converter 110 are controlled by the controller 120 to have charging states sequentially.

In operation S620, the top work item is adjusted by the controller 120 according to the trigger event. Taking FIG. 3 as an example, in the non-power-saving mode, when the total current IOUT_TOTAL drops and the phase circuit 115 has the maximum current or the maximum temperature, the controller 120 outputs the driving signal PWM5 to the driving circuit D5 so that the driving circuit D5 controls the phase circuit 115 to maintain the discharge state in the next cycle, and the controller 120 respectively outputs the driving signals PWM6~PWM8 and PWM1~PWM4 to the driving circuits D6~D8 and D1~D4 to make the driving circuit D6 ~D8 and D1~D4 adjust the phase circuit 116 to be the first working item in the next cycle and control the phase circuits 116~118 and 111~114 to have charging states in sequence.

Since the details of the above-mentioned operations S610-S620 have been described in the paragraphs related to FIG. 3 to FIG. 5, details are not repeated here.

In summary, the reliability of the disclosed multi-phase voltage converter can be effectively improved.

Although this disclosure has been disclosed as above in terms of implementation, it is not intended to limit this disclosure. Anyone with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure should be defined by the scope of the appended patent application.

100:Voltage conversion system 110:Multiphase Voltage Converter 111~118: phase circuit 120: Controller 121: Feedback signal circuit 122: System command receiving circuit 123: Phase management circuit 124: Pulse width modulation circuit 130: Detection circuit 600: control method APS_EN: Automatic phase cut enabling signal CO:capacitance CS1, CS2: Control signal CS3: Phase management signal D1~D8: drive circuit DR: Detection result HS: High bridge switch I1~I8: Detection current IOUT_TOTAL: total current K1, K2, K3: cycle L: inductance LD: load LP1, LP2: power saving mode command LS: lower bridge switch NORMAL: normal mode command P1, P2, P3: period PWM1~PWM8: drive signal S1, S2, S3: period S610, S620: Operation SET: set signal T1~T8: Detect temperature TP1, TP2, TP2', TP3, TP3', TP4, TP4', TP5, TP5': time points VIN: input voltage

In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more comprehensible, the accompanying drawings are described as follows: FIG. 1 is a schematic diagram of a voltage conversion system according to some embodiments of the present disclosure; FIG. 2 is a schematic diagram illustrating the operation of a controller according to some embodiments of the present disclosure; FIG. 3 is a timing diagram of a non-power-saving mode according to some embodiments of the present disclosure; FIG. 4 is a timing diagram of a sequential definition method of a power saving mode according to some embodiments of the present disclosure; FIG. 5 is a timing diagram of a random definition method of a power saving mode according to some embodiments of the present disclosure; and FIG. 6 is a flow chart of a control method according to some embodiments of the present disclosure.

100:Voltage conversion system

110:Multiphase Voltage Converter

111~118: phase circuit

120: Controller

130: Detection circuit

CO:capacitance

D1~D8: drive circuit

HS: High bridge switch

I1~I8: Detection current

IOUT_TOTAL: total current

L: inductance

LD: load

LS: lower bridge switch

PWM1~PWM8: drive signal

SET: set signal

T1~T8: Detect temperature

VIN: input voltage

Claims (9)

A voltage conversion system comprising: A multi-phase voltage converter coupled to a load and comprising: a first phase circuit; a second phase circuit; a third phase circuit, wherein the first phase circuit, the second phase circuit and the third phase circuit sequentially have a charging state in a first cycle; and at least one driving circuit coupled to the first phase circuit, the second phase circuit and the third phase circuit; and A controller, coupled to the at least one driving circuit, outputs at least one driving signal to the at least one driving circuit according to a trigger event so that the at least one driving circuit adjusts the second-phase circuit or the third-phase circuit as a front-most work item in a second cycle after the first cycle. The voltage conversion system as described in claim 1, wherein when the trigger event is a total current drop in a non-power-saving mode and the second phase circuit has a maximum current or a maximum temperature, the controller outputs the at least one drive signal to the at least one drive circuit so that the at least one drive circuit adjusts the third phase circuit to the front work item in a second period after the first period and controls the third phase circuit and the first phase circuit to have the charging state in sequence and the second phase circuit to maintain a discharge state. The voltage conversion system as described in claim 2, wherein each of the first phase circuit, the second phase circuit and the third phase circuit includes an upper switch and a lower switch, wherein when the second phase circuit has the charging state, the upper switch of the second phase circuit is turned on and the lower switch of the second phase circuit is turned off, wherein when the second phase circuit has the discharging state, the upper switch of the second phase circuit is turned off and the lower switch of the second phase circuit is turned on. The voltage conversion system according to claim 2, wherein the controller controls the third phase circuit to have the charge state, the first phase circuit to maintain the discharge state and the second phase circuit to maintain an off state in a third period after the second period. The voltage conversion system as described in claim 4, wherein each of the first phase circuit, the second phase circuit and the third phase circuit includes an upper bridge switch and a lower bridge switch, wherein when the second phase circuit has the closed state, the upper bridge switch of the second phase circuit and the lower bridge switch of the second phase circuit are turned off. The voltage conversion system as described in claim 1, wherein when the trigger event is a power-saving mode, the controller controls the second-phase circuit to have the charging state according to a charging sequence in the first cycle during a first power-saving period after the first cycle, and the first-phase circuit and the third-phase circuit remain in a closed state, and adjusts the second-phase circuit to be the first working item and the first-phase circuit to be the last working item according to the charging sequence. The voltage conversion system as described in claim 6, wherein in the power saving mode, the controller controls the third phase circuit to have the charging state and the first phase circuit and the second phase circuit remain in the off state during a second power saving period after the first power saving period. The voltage conversion system as described in claim 1, wherein when the trigger event is a power-saving mode, if the second-phase circuit is a current working phase circuit when a power-saving mode command changes to a high logic value, the controller controls the second-phase circuit to have the charging state during a first power-saving period, and the first-phase circuit and the third-phase circuit remain in a closed state, and adjusts the second-phase circuit to be the first working item and the first-phase circuit to be the last working item. The voltage conversion system as described in claim 8, wherein the multi-phase voltage converter further comprises a fourth phase circuit, wherein the first phase circuit, the second phase circuit, the third phase circuit and the fourth phase circuit have the charging state sequentially in the first cycle, Wherein in the power saving mode, if the fourth phase circuit is the current working phase circuit when the power saving mode command turns to the high logic value again, the controller controls the fourth phase circuit to have the charging state during a second power saving period, and the first phase circuit, the second phase circuit and the third phase circuit remain in the off state.

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