TWM635837U - Semiconductor device - Google Patents

Abstract

A semiconductor device includes a substrate, an epitaxial layer, a well region, a source region, a base region, a first JFET region, a second JFET region, a gate dielectric layer, and a gate layer. The epitaxial layer is at one side of the substrate. The well region is in the epitaxial layer. The source region is in the well region. The base region is in the well region and adjacent the source region. The first JFET region is adjacent the well region. The second JFET region is in the first JFET region. The first JFET region and the second JFET region include a plurality of first semiconductor-type dopants, and a dopant concentration of the second JFET region is higher than a dopant concentration of the first JFET region. The gate dielectric layer is at one side of the epitaxial layer distal to the substrate. The gate layer is at one side of the gate electric layer distal to the epitaxial layer.

Description

Semiconductor device

Some embodiments of the present disclosure relate to a semiconductor device.

Silicon carbide power transistors have the characteristics of high blocking voltage, low on-resistance, and high thermal conductivity, making silicon carbide power transistors more and more important. Wherein, the resistance value of the silicon carbide power transistor can be composed of the resistance values of different components in the transistor, such as the resistance values of contacts, channels, gates, junction field effect transistor regions, and substrates. Wherein, the resistance value of the junction field effect transistor region accounts for a large part of the resistance value of the SiC power transistor.

The disclosure provides a semiconductor device, including a substrate, an epitaxial layer, a well region, a source region, a base region, a first junction field effect transistor region, a second junction field effect transistor region, and a gate dielectric layer with the gate layer. The epitaxial layer is on one side of the substrate. The well region is in the epitaxial layer. The source region is in the well region. The base region is in the well region and is adjacent to the source region. The first junction field effect transistor region is adjacent to the well region. The second junction field effect transistor region is in the first junction field effect transistor region, and the first junction field effect transistor region and the second junction field effect transistor region include a plurality of doped doped particles having the first semiconductor type. impurities, wherein the doping concentration of the second junction field effect transistor region is higher than that of the first junction field effect transistor region. The gate dielectric layer is on the side of the epitaxial layer away from the substrate. The gate layer is on the side of the gate dielectric layer away from the epitaxial layer.

In some embodiments, the well region includes a plurality of dopants having a second semiconductor type, and the second semiconductor type is different from the first semiconductor type.

In some embodiments, the well region wraps the bottom of the source region and the bottom of the base region.

In some embodiments, the bottom of the first junction field effect transistor region and the bottom of the second junction field effect transistor region are closer to the substrate than the bottom of the well region.

In some embodiments, the semiconductor device further includes a third junction field effect transistor region adjacent to the second junction field effect transistor region, and the third junction field effect transistor region includes the junction field effect transistor region having the first semiconductor type. Some dopants, the doping concentration of the third junction field effect transistor region is higher than the doping concentration of the second junction field effect transistor region.

In some embodiments, the semiconductor device further includes a source contact contacting the source region.

In some embodiments, the semiconductor device further includes a drain electrode on the other side of the substrate.

In some embodiments, the doping concentration of the well region is lower than that of the base region.

In some embodiments, the epitaxial layer includes a drift region, and the doping concentration of the first junction field effect transistor region and the doping concentration of the second junction field effect transistor region are higher than the doping concentration of the drift region .

In some embodiments, the doping concentration of the source region is higher than that of the drift region.

To sum up, the semiconductor devices according to some embodiments of the present disclosure may include JFET regions with different doping concentrations. When the doping concentration of the junction field effect transistor region is lower near the well region and higher in the center, and the doping concentration of the junction field effect transistor region is higher than that of the underlying drift region, the The resistance value of the junction field effect transistor region of a semiconductor device. In addition, the breakdown voltage drop of the semiconductor device can be avoided, so that the semiconductor device cannot bear too much driving voltage.

Some embodiments of the present disclosure relate to the structure of semiconductor devices and the manner in which they are formed. Some embodiments of the present disclosure are applicable to a junction gate field-effect transistor (JFET) region of a semiconductor device. A two-step ion implantation process can be carried out for the junction field effect transistor region in the semiconductor device, so that the doping concentration of the junction field effect transistor region is increased, and the resistance of the junction field effect transistor region of the semiconductor device is reduced. value. In addition, the doping concentration of the outer portion of the junction field effect transistor region is relatively low, so the breakdown voltage of the semiconductor device will not drop significantly, and the semiconductor device can withstand a certain driving voltage.

FIG. 1 illustrates a cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 includes a substrate 110, an epitaxial layer 120, a drift region 121, a well region 126, a source region 124, a base region 122, a first junction field effect transistor region 127, a second junction field effect transistor region 128 . The gate dielectric layer 140 and the gate layer 150 .

The epitaxial layer 120 is on one side of the substrate 110 . Well region 126 is in epitaxial layer 120 and on drift region 121 . Source region 124 is in well region 126 . The base region 122 is in the source region 124 and is adjacent to the source region 124 . The first junction field effect transistor region 127 is adjacent to the well region 126 . The second junction field effect transistor region 128 is in the first junction field effect transistor region 127 . The substrate 110, the drift region 121, the source region 124, the first junction field effect transistor region 127 and the second junction field effect transistor region 128 contain a plurality of dopants having the first semiconductor type, wherein the second junction field effect transistor region The doping concentration of the field effect transistor region 128 is higher than that of the first junction field effect transistor region 127, and the first junction field effect transistor region 127 and the second junction field effect transistor region The doping concentration of 128 is higher than that of the drift region 121 . The base region 122 and the well region 126 contain a plurality of dopants having a second semiconductor type, and the second semiconductor type is different from the first semiconductor type. In some embodiments, the first semiconductor type may be N-type, and the dopant of the first semiconductor type may be phosphorus, arsenic, nitrogen, or the like. The second semiconductor type can be P-type, and the dopant of the second semiconductor type can be boron, gallium, aluminum or the like. The gate dielectric layer 140 is on a side of the epitaxial layer 120 away from the substrate 110 . The gate layer 150 is on a side of the gate dielectric layer 140 away from the epitaxial layer 120 .

The semiconductor device 100 further includes a dielectric layer 160 , a source contact 170 and a drain electrode 180 . The dielectric layer 160 is on the epitaxial layer 120 . A source contact 170 contacts the source region 124 . The drain electrode 180 is on the other side of the substrate 110 , and the term “the other side” here is relative to the epitaxial layer 120 . That is, the drain electrode 180 and the epitaxial layer 120 are located on opposite sides of the substrate 110 . . When the gate layer 150 of the semiconductor device 100 is turned on, the electron flow follows the arrow C from the source contact 170 through the source region 124, the well region 126, the first junction field effect transistor region 127, and the second junction The field effect transistor region 128 , the drift region 121 , the substrate 110 , and flow to the drain electrode 180 . Compared with the drift region 121, the doping concentration of the first junction field effect transistor region 127 and the second junction field effect transistor region 128 is higher, so the first junction field effect transistor region 127 and the second junction field effect transistor region 127 The resistance of the field effect transistor region 128 can be reduced, thereby reducing the resistance of the semiconductor device 100 . In addition, in order to prevent the breakdown voltage of the semiconductor device 100 from dropping so that the semiconductor device 100 cannot bear too much driving voltage, the doping concentration of the second junction field effect transistor region 128 can be designed to be higher than that of the first junction field effect transistor region 128 . The doping concentration of the crystal region 127 is still high, that is, the doping concentration of the first junction field effect transistor region 127 close to the well region 126 is lower than that of the second junction field effect transistor region 128 far away from the well region 126 .

2 to 19 illustrate cross-sectional views of the manufacturing method of the semiconductor device 100 according to some embodiments of the present disclosure. Referring to FIG. 2 , referring to FIG. 2 , a substrate 110 and an epitaxial layer 120 are provided. Substrate 110 is any suitable substrate. In some embodiments, the substrate 110 may be made of, for example, but not limited to, silicon carbide. The substrate 110 may be doped with a dopant of the first semiconductor type. For example, the substrate 110 can be an N-type heavily doped substrate, such as a heavily doped region containing N-type dopants such as phosphorus, arsenic, and nitrogen. Next, an epitaxial layer 120 may be formed on the substrate 110 . In some embodiments, the epitaxial layer 120 can be made of, for example, but not limited to, silicon carbide. The epitaxial layer 120 may be doped with a dopant of the first semiconductor type. For example, the epitaxial layer 120 can be an N-type lightly doped substrate, such as a lightly doped region containing N-type dopants such as phosphorus, arsenic, and nitrogen. That is, the doping concentration of the epitaxial layer 120 may be lower than that of the substrate 110 .

Referring to FIG. 3 , a base region 122 is formed in the epitaxial layer 120 . Specifically, the photoresist material can be coated on the epitaxial layer 120 first, then the photoresist material is exposed using an opaque mask, and the photoresist material is developed to form the photoresist layer PR on the epitaxial layer 120, The photoresist layer PR exposes part of the epitaxial layer 120 . Next, using the photoresist layer PR as a mask, a second semiconductor-type ion implantation process is performed to form the base region 122 in the epitaxial layer 120 . In some embodiments, the base region 122 may be a P-type heavily doped region, for example, a heavily doped region containing P-type dopants such as boron, gallium, and aluminum. After the base region 122 is formed, the epitaxial layer 120 can be divided into a base region 122 that is doped with ions of the second semiconductor type and a drift region 121 that is not doped with ions of the second semiconductor type. Therefore, the drift region 121 remains N type lightly doped region. In some embodiments, the doping concentration of the drift region 121 may be in the range of 1E16 atoms/cm3 to 1E19 atoms/cm3. Next, referring to FIG. 4, the photoresist layer PR is removed. The photoresist layer PR can be removed by ashing, etching and the like.

Referring to FIG. 5 , a sacrificial stack 130 is formed on the epitaxial layer 120 . The sacrificial stack 130 includes a first sub-layer 132 and a second sub-layer 134 on the first sub-layer 132 . Specifically, the first sub-layer 132 can be formed on the epitaxial layer 120 first, and then the second sub-layer 134 can be formed on the first sub-layer 132 . The first sub-layer 132 and the second sub-layer 134 are made of different materials. In some embodiments, the first sub-layer 132 is made of silicon dioxide, and the second sub-layer 134 is made of silicon nitride.

Referring to FIG. 6 , the sidewall 134S of the second sub-layer 134 of the sacrificial stack 130 is retracted. Specifically, a wet etchant having a high etch selectivity to the second sublayer 134 may be used. That is, a wet etchant that is easy to etch the second sublayer 134 but not easy to etch the first sublayer 132 can be selected to expose the underlying first sublayer 132 , and the second sublayer 134 is perpendicular to the epitaxial layer 120 The projection does not cover the base region 122 . The second sub-layer 134 has a distance between the vertical projection of the epitaxial layer 120 and the base region 122 . In this embodiment, the first sub-layer 132 is still in place and has not been etched. When the first sub-layer 132 is silicon dioxide and the second sub-layer 134 is silicon nitride, the wet etchant may be hot phosphoric acid.

Referring to FIG. 7 , the source region 124 adjacent to the base region 122 is formed using the second sub-layer 134 as a mask. Specifically, a first semiconductor-type ion implantation process is performed to form the source region 124 in the epitaxial layer 120 . In some embodiments, the source region 124 can be an N-type heavily doped region, for example, a heavily doped region containing N-type dopants such as phosphorus, arsenic, and nitrogen. Dopants may be implanted into the epitaxial layer 120 through the first sub-layer 132 . The source region 124 is formed between the base region 122 and the vertical projection of the second sub-layer 134 on the epitaxial layer 120 . In some embodiments, the doping concentration of the source region 124 is higher than that of the drift region 121 . In some embodiments, a hard mask layer may be formed on the base region 122 when the source region 124 is formed, so that the base region 122 is not affected when the source region 124 is formed. Alternatively, in FIG. 3 , the doping concentration of the base region 122 can be increased, so that the ion concentration of the base region 122 can be adjusted to a desired concentration when the source region 124 is formed.

Referring to FIG. 8, the sidewall 134S of the second sub-layer 134 of the sacrificial stack 130 is retracted again. In some embodiments, the same wet etchant as described in FIG. Covers the base region 122 and the source region 124 . The second sub-layer 134 has a distance between the vertical projection of the epitaxial layer 120 and the source region 124 . In this embodiment, the first sub-layer 132 is still in place and has not been etched. In some embodiments, the length L1 of the retracted second sub-layer 134 may be in the range of 0.8 microns to 1.2 microns.

Referring to FIG. 9 , the well region 126 covering the base region 122 and the source region 124 is formed by using the retracted second sub-layer 134 as a mask. Specifically, a second semiconductor-type ion implantation process may be performed on the epitaxial layer 120 to form a well region 126 in the epitaxial layer 120 . Dopants may be implanted into the epitaxial layer 120 through the first sub-layer 132 . The well region 126 is formed between the source region 124 and the vertical projection of the second sub-layer 134 on the epitaxial layer 120 , and further extends down to the bottom of the base region 122 and the source region 124 . The well region 126 covers the bottom 124B of the source region 124 and the bottom 122B of the base region 122 . The boundary of the well region 126 is also substantially aligned with the sidewall 134S of the second sub-layer 134 . In some embodiments, the well region 126 can be a P-type lightly doped region, such as a lightly doped region containing P-type dopants such as boron, gallium, aluminum, etc., and the doping concentration of the well region 126 is higher than that of the base region. The doping concentration of 122 is still low. Therefore, the doping concentration of the base region 122 and the source region 124 will not be substantially affected when the well region 126 is formed.

Referring to FIG. 10 , a third sub-layer 136 is deposited on the first sub-layer 132 of the sacrificial stack 130 and surrounds the second sub-layer 134 . Specifically, a material layer having the same material as that of the first sub-layer 132 may be formed on the first sub-layer 132 and the second sub-layer 134 . Next, the layer of material over the second sub-layer 134 is removed to form a third sub-layer 136 that still covers the first sub-layer 132 but exposes the second sub-layer 134 . In this way, the third sub-layer 136 surrounds the second sub-layer 134 .

Referring to FIG. 11 and FIG. 12 , the second sublayer 134 is removed, and the third sublayer 136 is used as a mask to form the first junction field effect transistor region 127 adjacent to the well region 126 . Since the material of the second sub-layer 134 is different from that of the first sub-layer 132 and the third sub-layer 136 , an appropriate wet etchant can be selected to remove the second sub-layer 134 . In some embodiments, the second sub-layer 134 may be removed using the same wet etchant as described in FIG. 6 . Since the positions of the well regions 126 are defined by the second sub-layer 134 , after the second sub-layer 134 is removed, the drift region 121 of the epitaxial layer 120 between adjacent well regions 126 can be exposed.

Next, a first semiconductor-type ion implantation process is performed to form a first junction field effect transistor region 127 between adjacent well regions 126 . In some embodiments, the first junction field effect transistor region 127 can be an N-type heavily doped region, for example, a heavily doped region containing N-type dopants such as phosphorus, arsenic, nitrogen, and the like. The doping concentration of the first junction field effect transistor region 127 is higher than that of the drift region 121 . In some embodiments, the doping concentration of the first junction field effect transistor region 127 may be in the range of 3E11 atoms/cm3 to 5E13 atoms/cm3. The depth of the first junction field effect transistor region 127 can be controlled such that the bottom 127B of the first junction field effect transistor region 127 is lower than the bottom 126B of the well region 126 .

Referring to FIG. 13 , spacers 138 are formed on sidewalls 136S of the third sub-layer 136 of the sacrificial stack 130 . Specifically, a dielectric material layer conformal to the first sub-layer 132 and the third sub-layer 136 may be formed on the sacrificial stack 130 first, and the dielectric material layer is formed along the first sub-layer 132 and the third sub-layer 136 The upper surface of and the sidewall 136S of the third sublayer 136 are formed. Next, the dielectric material layer on the upper surfaces of the first sub-layer 132 and the third sub-layer 136 is removed to form spacers 138 left on the sidewalls 136S of the third sub-layer 136, and the spacers 138 are epitaxially formed. The vertical projection of the layer 120 covers a portion of the first junction field effect transistor region 127 . Spacers 138 may be made of any suitable dielectric material, such as silicon oxide, silicon nitride, the like, or combinations thereof. In some embodiments, the length L2 of the spacer 138 may be in the range of 50 nm to 200 nm.

Referring to FIG. 14, the second junction field effect transistor region 128 is formed in the first junction field effect transistor region 127 by using the spacer 138 as a mask. Specifically, a first semiconductor type ion implantation process is performed to form the second junction field effect transistor region 128 in the first junction field effect transistor region 127 . In some embodiments, the second junction field effect transistor region 128 can be an N-type heavily doped region, for example, a heavily doped region containing N-type dopants such as phosphorus, arsenic, nitrogen, and the like. The doping concentration of the second junction field effect transistor region 128 is higher than that of the first junction field effect transistor region 127 . The doping concentration of the first junction field effect transistor region 127 may be in the range of 1E11 atoms/cm3 to 5E13 atoms/cm3. Since the vertical projection of the spacer 138 on the epitaxial layer 120 covers the peripheral portion of the first junction field effect transistor region 127, the second junction field effect transistor region 128 can be surrounded by the first junction field effect transistor region 127. surrounded. The first junction field effect transistor region 127 can separate the well region 126 from the second junction field effect transistor region 128 . The depth of the second junction field effect transistor region 128 can be controlled such that the bottom 128B of the second junction field effect transistor region 128 is lower than the bottom 126B of the well region 126 . In some embodiments, by controlling the length L1 of the second sublayer 134 in FIG. 8 and the length L2 of the spacer 138 in FIG. 13, the overall junction field effect transistor region (including the first The width W1 of the junction field effect transistor region 127 and the second junction field effect transistor region 128) and the width W2 of the first junction field effect transistor region 127, and the entire junction field effect transistor region (including The width W1 of the first junction field effect transistor region 127 and the second junction field effect transistor region 128) and the width W2 of the first junction field effect transistor region 127 are respectively the same as the second sublayer 134 of FIG. 8 The length L1 of the spacer 138 is the same as the length L2 of the spacer 138 in FIG. 13 .

Compared with the drift region 121, the doping concentration of the first junction field effect transistor region 127 and the second junction field effect transistor region 128 is higher, so the first junction field effect transistor region 127 and the second junction field effect transistor region 127 The resistance of the field effect transistor region 128 can be reduced, thereby reducing the resistance of the semiconductor device 100 . In addition, the doping concentration of the second junction field effect transistor region 128 can be higher than the doping concentration of the first junction field effect transistor region 127, so the breakdown voltage drop of the semiconductor device 100 can be avoided, and the semiconductor device 100 can Can not withstand too much driving voltage. In addition, in some embodiments, the bottom 127B of the first junction field effect transistor region 127 and the bottom 128B of the second junction field effect transistor region 128 are lower than the bottom 126B of the well region 126 and reach the bottom of the well region 126 The bottom of 126B expands, so the first junction field effect transistor region 127 and the second junction field effect transistor region 128 can also be used to expand the flow range of the electron current.

Next, referring to FIG. 15, the sacrificial stack 130 and the spacer 138 are removed. In some embodiments, an annealing process is performed on the first junction field effect transistor region 127 and the second junction field effect transistor region 128 before or after removing the sacrificial stack 130 and the spacer 138 . In some embodiments, the temperature of the annealing process is in the range of 1400°C to 1800°C. Therefore, the ions in the first junction field effect transistor region 127 and the second junction field effect transistor region 128 can be activated, and the lattice damage caused by ion implantation can be repaired.

Next, referring to FIG. 16 , a dielectric layer 142 is formed on the epitaxial layer 120 , and a conductive layer 152 is formed on the dielectric layer 142 . In some embodiments, the dielectric layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, polysilicon, combinations thereof, or the like. In some embodiments, the conductive layer 152 may include polysilicon, metal, metal compounds, combinations thereof, or the like.

Next, referring to FIG. 17 , the dielectric layer 142 and the conductive layer 152 are patterned to form the gate dielectric layer 140 and the gate layer 150 on the epitaxial layer 120 . The conductive layer 152 may be patterned first to form the gate layer 150 . Next, using the gate layer 150 as a mask, the dielectric layer 142 is patterned to form the gate dielectric layer 140 . Therefore, the sidewalls of the gate dielectric layer 140 and the gate layer 150 can be aligned with each other. The gate dielectric layer 140 contacts the source region 124 , and the gate dielectric layer 140 covers the well region 126 on the surface of the epitaxial layer 120 . That is, the gate dielectric layer 140 may extend from one source region 124 to the other source region 124 .

Next, referring to FIG. 18 , a dielectric layer 160 may be formed on the gate dielectric layer 140 and the gate layer 150 . Next, a source contact 170 is formed in the dielectric layer 160 . Specifically, the dielectric layer 160 can be formed on the gate dielectric layer 140 and the gate layer 150 first, so that the dielectric layer 160 covers the gate dielectric layer 140 , the gate layer 150 and the epitaxial layer 120 . Next, an opening is formed in the dielectric layer 160 and a source contact 170 is formed in the opening. A source contact 170 contacts the base region 122 and the source region 124 . Referring to FIG. 19 , a drain electrode 180 may be formed under the substrate 110 . The drain electrode 180 may be under the substrate 110 and contact the substrate 110 .

FIG. 20 illustrates a cross-sectional view of a semiconductor device 100 in other embodiments of the present disclosure. In some embodiments, more junction field effect transistor regions can be formed in the semiconductor device 100, so that the resistance of the junction field effect transistor region can be reduced more effectively, while maintaining the breakdown voltage of the semiconductor device 100 . In some embodiments, the semiconductor device 100 further includes a third junction field effect transistor region 129 , and the third junction field effect transistor region 129 is adjacent to the second junction field effect transistor region 128 . The third junction field effect transistor region 129 includes a dopant having the first semiconductor type, and the doping concentration of the third junction field effect transistor region 129 is higher than that of the second junction field effect transistor region 128 The concentration is still high. In other embodiments, the semiconductor device 100 may include more junction field effect transistor regions, and in general, the doping concentration of the junction field effect transistor region is from the edge of the well region 126 to the junction field effect transistor region. The center of the district is promoted.

The formation of the third junction field effect transistor region 129 can be performed after FIG. 14 . After performing the process of FIG. 14 , additional spacers may be formed on the sidewalls of the spacers 138 . Next, the third junction field effect transistor region 129 is formed in the second junction field effect transistor region 128 by using the additional spacer as a mask. That is, the process of forming different junction field effect transistor regions using spacers may be performed multiple times to form junction field effect transistor regions with different doping concentrations.

To sum up, the semiconductor devices according to some embodiments of the present disclosure may include JFET regions with different doping concentrations. When the doping concentration of the junction field effect transistor region is lower near the well region and higher in the center, and the doping concentration of the junction field effect transistor region is higher than that of the underlying drift region, the The resistance value of the junction field effect transistor region of a semiconductor device. In addition, the breakdown voltage drop of the semiconductor device can be avoided, so that the semiconductor device cannot bear too much driving voltage.

100: Semiconductor device 110: Substrate 120: epitaxial layer 121: Drift zone 122: base area 122B: Bottom 124: source area 124B: Bottom 126: well area 126B: Bottom 127: first junction field effect transistor region 127B: Bottom 128: second junction field effect transistor region 128B: bottom 129: The third junction field effect transistor area 130:Sacrificial stack 132: The first sublayer 134: second sublayer 134S: side wall 136: The third sublayer 136S: side wall 138: spacer 140: gate dielectric layer 142: dielectric layer 150: gate layer 152: Conductive layer 160: dielectric layer 170: source contact 180: Drain electrode C: arrow L1: length L2: length PR: photoresist layer W1: width W2: width

FIG. 1 shows a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. 2 to 19 illustrate cross-sectional views of manufacturing methods of semiconductor devices according to some embodiments of the present disclosure. FIG. 20 shows a cross-sectional view of semiconductor devices according to other embodiments of the present disclosure.

100: Semiconductor device

110: Substrate

120: epitaxial layer

121: Drift zone

122: base area

124: source area

126: well area

127: first junction field effect transistor area

128: second junction field effect transistor region

140: gate dielectric layer

150: gate layer

160: dielectric layer

170: source contact

180: Drain electrode

C: arrow

Claims (10)

A semiconductor device comprising: a substrate; an epitaxial layer on one side of the substrate; a well region in the epitaxial layer; a source region in the well region; a base region in the well region and adjacent to the source region; a first junction field effect transistor region, adjacent to the well region; A second junction field effect transistor region, in the first junction field effect transistor region, the first junction field effect transistor region and the second junction field effect transistor region include a first a plurality of dopants of semiconductor type, wherein a doping concentration of the second junction field effect transistor region is higher than a doping concentration of the first junction field effect transistor region; a gate dielectric layer on the side of the epitaxial layer away from the substrate; and A gate layer is on the side of the gate dielectric layer away from the epitaxial layer. The semiconductor device as claimed in claim 1, wherein the well region includes a plurality of dopants having a second semiconductor type, and the second semiconductor type is different from the first semiconductor type. The semiconductor device according to any one of claims 1 to 2, wherein the well region covers a bottom of the source region and a bottom of the base region. The semiconductor device according to any one of claim 1 to claim 2, wherein a bottom of the first junction field effect transistor region and a bottom of the second junction field effect transistor region are more than that of the well region A bottom is also proximate to the substrate. The semiconductor device according to any one of claim 1 to claim 2, further comprising a third junction field effect transistor region adjacent to the second junction field effect transistor region, the third junction field effect transistor region The junction field effect transistor region includes the dopants having the first semiconductor type, wherein a doping concentration of the third junction field effect transistor region is higher than the doping concentration of the second junction field effect transistor region Still high. The semiconductor device according to any one of claim 1 to claim 2, further comprising a source contact contacting the source region. The semiconductor device according to any one of claim 1 to claim 2, further comprising a drain electrode on the other side of the substrate. The semiconductor device according to any one of claim 1 to claim 2, wherein a doping concentration of the well region is lower than a doping concentration of the base region. The semiconductor device according to any one of claim 1 to claim 2, wherein the epitaxial layer includes a drift region, and the doping concentration of the first junction field effect transistor region is the same as that of the second junction field The doping concentration of the effective transistor region is higher than a doping concentration of the drift region. The semiconductor device as claimed in claim 9, wherein a doping concentration of the source region is higher than the doping concentration of the drift region.

Images