TWM607067U - Byte stuffing circuit - Google Patents

Abstract

A byte stuffing circuit is provided. An input gate receives a first data stream and generates a second data stream according to the first data stream, wherein a first size of the first data stream is N bytes, and a second size of the second data stream is 2N bytes. In response to a Xth byte of the second data stream matching a first flag byte, a Xth stage logic gate overwrites the Xth byte by a first stuffing byte, and inserts a second stuffing byte into a (X+1)th byte of the second data stream, wherein X is a positive integer between 1 and 2N-1. A remnant gate combines a remnant data stream and a first part of the second data stream to generate a third data stream, and configures a second part of the second data stream as the remnant data stream. An output gate outputs the third data stream.

Description

Byte fill circuit

The invention relates to a byte filling circuit.

The high-level data link control (HDLC) protocol is an Ethernet data format for wide area network (WAN) applications. Figure 1 is a schematic diagram of an HDLC data stream. The HDLC data stream can include several HDLC frames, and two HDLC frames can be separated by a flag byte. Generally speaking, the HDLC data stream uses the hexadecimal value "7E" as the flag byte. In order for the receiving end of the HDLC data stream to correctly recognize the difference between the payload and the flag in the HDLC frame, the hexadecimal value "7E" in the HDLC frame needs to be replaced with other hexadecimal values .

Figure 2 is a schematic diagram of using byte padding to convert a data stream into an HDLC data stream. The flag byte containing the hexadecimal value "7E" will be added to both ends of the data stream, and the hexadecimal value "7E" in the data stream will be replaced with the hexadecimal value "7D5E", and The hexadecimal value "7D" in the data stream will be replaced with the hexadecimal value "7D5D". Therefore, after byte filling, the size of the payload of the HDLC data stream will be larger than the size of the original data stream.

On the other hand, as the carrier frequency of Ethernet increases, many common field programmable gate array (FPGA) or very large scale integrated circuit (VLSI) technologies have gradually been unable to support B The carrier frequency of the Ethernet network. For example, common FPGA or VLSI technologies may not be able to support operating frequencies of more than 500 megahertz (MHz), but the current carrier frequency of Ethernet may be as high as 10 gigahertz (GHz). In order to reduce the operating frequency, the serial data of Ethernet can be changed to parallel data. For example, converting the 64-bit serial data of 10GHz into 64-bit parallel data can reduce the operating frequency from 10GHz to 156.25MHz.

However, if the parallel data is filled with bytes to convert the parallel data into HDLC data, the size of the HDLC data may increase, thereby exceeding the size supported by the data bus of the parallel data.

The invention provides a byte filling circuit, which is suitable for byte filling parallel data.

The new type of byte filling circuit includes an input gate, a logic circuit, a residual register, a residual gate and an output gate. The input gate receives the first data stream and generates a second data stream according to the first data stream, wherein the first size of the first data stream is N bytes, and the second size of the second data stream is 2N bytes , Where N is a positive integer. The logic circuit is coupled to the input gate and includes an X-th order logic gate. In response to the match between the Xth byte of the second data stream and the first flag byte, the Xth level logic gate overwrites the Xth byte with the first stuffing byte, and inserts the second stuffing byte To the (X+1)th byte of the second data stream, where X is a positive integer between 1 and 2N-1. The residual register stores residual data streams. The residual gate is coupled to the logic circuit and the residual register. The residual gate combines the residual data stream and the first part of the second data stream to generate a third data stream, and configures the second part of the second data stream as a residual data stream. The output gate is coupled to the residual gate and outputs the third data stream.

In an embodiment of the present invention, the above-mentioned X-th level logic gate inserts the third stuffing byte into the (X+1)th bit in response to the match between the Xth byte and the second flag byte group.

In an embodiment of the present invention, the third size of the third data stream is N bytes, and the residual gate determines the first part of the second data stream according to the fourth size and the third size of the residual data stream .

In an embodiment of the present invention, the above-mentioned byte filling circuit further includes a residual counter and a controller. The residual counter stores the residual count value corresponding to the fourth size of the residual data stream. The controller is coupled to the input gate, the X-level logic gate and the residual gate, wherein the controller stops the operation of the input gate and the X-level logic gate in response to the residual count value being greater than or equal to N until the updated residual count value Less than N.

In an embodiment of the present invention, the above-mentioned X-level logic gate increments the counter value by one in response to the X-th byte matching one of the first flag byte and the second flag byte , Wherein the residual gate generates an updated residual count value according to the count value and the residual count value.

In an embodiment of the present invention, the above-mentioned first flag byte is the hexadecimal value "7E", the first stuffing byte is the hexadecimal value "7D", and the second stuffing byte is The hexadecimal value "5E", where the second flag byte is the hexadecimal value "7D", and the third padding byte is the hexadecimal value "5D".

In an embodiment of the present invention, the aforementioned third data stream is parallel data.

In an embodiment of the present invention, the aforementioned input gate fills the first data stream with zeros to generate the second data stream.

In an embodiment of the present invention, the aforementioned X-level logic gate shifts the (X+1)th byte to the (2N)th byte in the second data stream to insert the second stuffing byte into The (X+1)th byte.

Based on the above, the present invention can perform byte filling on parallel data, and the bit width of the parallel data after byte filling will not increase.

FIG. 3 illustrates a schematic diagram of a byte filling circuit 100 according to an embodiment of the present invention. The byte filling circuit 100 may include a controller 110, an input register 120, an input gate 130, a counter 141, a register 142, a logic circuit 300, a remnant gate 170, a residual counter 181, and a residual register 182. The output gate 190 and the output register 200. The byte filling circuit 100 can receive the data stream S1, perform byte filling on the data stream S1 to generate the data stream S3, and output the data stream S3, where the data stream S1 can be serial data (serial data) or parallel data ( parallel data), and the data stream S3 can be parallel data. Each register in the byte filling circuit 1005 may be a first in first out (FIFO) register.

The controller 110 can be coupled to and control the input register 120, input gate 130, counter 141, register 142, logic circuit 300, residual gate 170, residual counter 181, residual register 182, output gate 190, and output temporary存器200. In detail, the controller 110 is, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose micro control unit (MCU), microprocessor (microprocessor) , Digital signal processor (DSP), programmable controller, application specific integrated circuit (ASIC), graphics processing unit (GPU), image signal processor (image signal processor, ISP, image processing unit (IPU), arithmetic logic unit (ALU), complex programmable logic device (CPLD), FPGA or other similar components or the above components The combination.

The input register 120 can be used to receive and store the data stream S1, where the data stream S1 can be serial data, and the size of the data stream S1 can be N bytes. In this embodiment, N may be 8, but the present invention is not limited to this. For example, N can be any positive integer.

The input gate 130 can be coupled to the input register 120, receives the data stream S1 from the input register 120, and generates the data stream S2 according to the data stream S1, wherein the size of the data stream S2 can be 2N bytes. In this embodiment, 2N may be 16, but the present invention is not limited to this. The input gate 130 can zero-fill the data stream S1 to generate the data stream S2. Specifically, the data stream S1 may include N bytes such as the first byte to the Nth byte, where the first byte is, for example, the most significant bit of the data stream S1. , MSB) or one of the least significant bit (LSB), and the Nth bit group is, for example, the other of the MSB or LSB of the data stream S1. The input gate 130 may add N bytes after the Nth byte of the data stream S1 to generate the data stream S2, and the value of each newly added byte may be zero. In other words, the first byte to the Nth byte of the data stream S2 can be used to store the data stream S1, and the (N+1)th byte to (2N)th byte of the data stream S2 can be used to store Store the value "zero".

The input gate 130 can be coupled to the register 142 and input the data stream S2 to the register 142 for storage. The size of the register 142 can be 2N bytes. The count value C0 in the counter 141 may be zero. The counter 141 and the register 142 can be coupled to the logic circuit 300.

The logic circuit 300 may include (2N-1) levels, and each level may include a logic gate, a counter, and a register coupled to the controller 110, wherein the size of the register may be 2N bytes. For example, the first level of the logic circuit 300 may include a first level logic gate 150-1, a first level counter 161-1, and a first level register 162-1, where the first level register 162-1 The size can be 2N bytes. Similarly, the X-th level (X is a positive integer between 1 and (2N-1)) of the logic circuit 300 may include the X-level logic gate 150-X, the X-level counter 161-X, and the X-level The register 162-X, wherein the size of the X-level register 162-X can be 2N bytes. The (2N-1)th level of the logic circuit 300 may include the (2N-1)th level logic gate 150-(2N-1), the (2N-1)th level counter 161-(2N-1), and the (2N-th level). 1) Level register 162-(2N-1), where the size of the (2N-1)th level register 162-(2N-1) can be 2N bytes.

The first-level logic gate 150-1 can be coupled to the counter 141 and the register 142, and can be coupled to the first-level counter 161-1 and the first-level register 162-1. The first-level logic gate 150-1 can receive the count value C0 from the counter 141, and can receive the data stream S2 from the register 142. The first-level logic gate 150-1 can be used to determine whether the first byte of the data stream S2 (for example, one of the MSB or the LSB of the data stream S2) is the same as the first flag byte or the second flag bit The tuples are matched to determine whether to perform byte filling on the first byte of the data stream S2. If the first byte of the data stream S2 matches one of the first flag byte or the second flag byte, then the first-level logic gate 150-1 can set the first bit of the data stream S2 The tuple is filled with bytes, and the count value C0 can be increased by one. If the first byte of the data stream S2 does not match the first or second flag byte, the first-level logic gate 150-1 may not perform the first byte of the data stream S2. The byte is filled and the count value C0 may not be increased by one.

FIG. 4 illustrates a schematic diagram of performing byte filling on the first byte of the data stream S2 according to an embodiment of the present invention. The first-level logic gate 150-1 can rewrite the first byte of the data stream S2 with the first padding byte in response to the matching of the first byte of the data stream S2 with the first flag byte, and the first byte of the data stream S2 Two stuffing bytes are inserted into the second byte of the data stream S2, and the counter value C0 is increased by one. The first-level logic gate 150-1 can translate the second byte to the (2N)th byte to insert the second stuffing byte into the second byte of the data stream S2.

In one embodiment, the first flag byte may be the hexadecimal value "7E", the first padding byte may be the hexadecimal value "7D", and the second padding byte may be sixteen. Carry the value "5E". Accordingly, if the first-level logic gate 150-1 determines that the first byte of the data stream S2 in the register 142 is a hexadecimal value "7E", the first-level logic gate 150-1 can The first byte is filled with bytes. In detail, the first-level logic gate 150-1 can use the hexadecimal value "7D" to rewrite the first byte of the data stream S2, and shift the second byte to the (2N)th byte of the data stream S2 . After translation, the data originally located in the i-th byte of data stream S2 will be moved to the (i+1)-th byte of data stream S2, where i is a positive value between 2 and (2N-1). Integer. For example, the data originally located in the second byte of the data stream S2 will be moved to the third byte of the data stream S2, and the data originally located in the (2N-1)th byte of the data stream S2 will be Move to the (2N)th byte of the data stream S2, and the data originally located in the (2N)th byte of the data stream S2 will be deleted. After the translation is completed, the first-level logic gate 150-1 can write the hexadecimal value "5E" into the second byte of the data stream S2 to complete the byte filling of the second byte. After completing the byte filling of the first byte of the data stream S2, the first-level logic gate 150-1 can input the data stream S2 to the first-level register 162-1 for storage. The size of the register 162-1 may be 2N bytes. On the other hand, if the first-level logic gate 150-1 determines that the first byte of the data stream S2 is a hexadecimal value "7E", the first-level logic gate 150-1 can increase the count value C0 by one to generate Count the value C1, and input the count value C1 to the first-stage counter 161-1 for storage.

On the other hand, the first-level logic gate 150-1 can insert the third stuffing byte into the second bit of the data stream S2 in response to the match between the first byte of the data stream S2 and the second flag byte. Tuple. The first-level logic gate 150-1 can translate the second byte to the (2N)th byte to insert the third stuffing byte into the second byte of the data stream S2.

In one embodiment, the second flag byte can be a hexadecimal value "7D", and the third padding byte can be a hexadecimal value "5D". Accordingly, if the first-level logic gate 150-1 determines that the first byte of the data stream S2 is a hexadecimal value "7D", then the first-level logic gate 150-1 can perform processing on the first byte Byte padding. In detail, the first-level logic gate 150-1 can shift the second byte to the (2N)th byte of the data stream S2. After translation, the data originally located in the i-th byte of data stream S2 will be moved to the (i+1)-th byte of data stream S2, where i is a positive value between 2 and (2N-1). Integer. After the translation is completed, the first-level logic gate 150-1 can write the hexadecimal value "5D" into the second byte of the data stream S2 to complete the byte filling of the second byte. After completing the byte filling of the first byte of the data stream S2, the first-level logic gate 150-1 can input the data stream S2 to the first-level register 162-1 for storage. On the other hand, if the first-level logic gate 150-1 determines that the first byte of the data stream S2 is a hexadecimal value "7D", the first-level logic gate 150-1 can increase the count value C0 by one to generate Count the value C1, and input the count value C1 to the first-stage counter 161-1 for storage.

Returning to FIG. 3, the controller 110 can input the count value C1 in the first-level counter 161-1 and the data stream S2 in the first-level register 162-1 to the second level of the logic circuit 300, so that the The second level decides whether to perform byte filling on the second byte of the data stream S2. By analogy, the X-level logic gate 150-X of the X-level of the logic circuit 300 can receive the count value C(X-1) and the data stream S2 from the (X-1)-level of the logic circuit 300, and can determine Whether to perform byte filling on the Xth byte of the data stream S2. If the Xth byte of the data stream S2 matches one of the first flag byte or the second flag byte, then the X-level logic gate 150-X can set the Xth bit of the data stream S2 The tuple is filled with bytes, and the count value C(X-1) can be increased by one. If the Xth byte of the data stream S2 does not match the first flag byte or the second flag byte, the X-level logic gate 150-X may not perform the Xth byte of the data stream S2. The byte is filled, and the count value C(X-1) may not be increased by one.

FIG. 5 illustrates a schematic diagram of performing byte filling on the Xth byte of the data stream S2 according to an embodiment of the present invention. The (X-1)th level of the logic circuit 300 may include the (X-1)th level logic gate 150-(X-1), the (X-1)th level counter 161-(X-1), and the (X-1)th level. 1) Stage register 162-(X-1). The X level logic gate 150-X can be coupled to the (X-1) level counter 161-(X-1) and the (X-1) level register 162-(X-1), and can be coupled To the X-level counter 161-X and the X-level register 162-X. The X-level logic gate 150-X can obtain the first byte to the (X-1)-th byte of the data stream S2 from the (X-1)-th stage register 162-(X-1), and store The first byte to the (X-1)th byte of the data stream S2 are input to the X-th level register 162-X for storage. In addition, the X-level logic gate 150-X can overwrite the X-th byte of the data stream S2 with the first padding byte in response to the match between the X-th byte of the data stream S2 and the first flag byte. The second stuffing byte is inserted into the (X+1)th byte of the data stream S2, and the counter value C(X-1) is increased by one. The X-level logic gate 150-X can shift the Xth byte to the (2N)th byte to insert the second stuffing byte into the Xth byte of the data stream S2.

In one embodiment, the first flag byte may be the hexadecimal value "7E", the first padding byte may be the hexadecimal value "7D", and the second padding byte may be sixteen. Carry the value "5E". Accordingly, if the X-level logic gate 150-X determines that the X-th byte of the data stream S2 in the (X-1)-level register 162-(X-1) is the hexadecimal value "7E", Then, the X-th level logic gate 150-X can perform byte filling on the X-th byte.

In detail, the X-level logic gate 150-X can use the hexadecimal value "7D" to rewrite the Xth byte of the data stream S2, and shift the (X+1)th byte of the data stream S2 to the (2N)th byte. ) Bytes. After translation, the data originally located in the i-th byte of the data stream S2 will be moved to the (i+1)-th byte of the data stream S2, where i is between X+1 and (2N-1) A positive integer. For example, the data originally located in the (X+1)th byte of data stream S2 will be moved to the (X+2)th byte of data stream S2, and originally located in the (2N)th byte of data stream S2 The byte data will be deleted. After the translation is completed, the X-level logic gate 150-X can write the hexadecimal value "5E" to the (X+1)th byte of the data stream S2 to complete the Xth byte Group fill. After filling the bytes of the Xth byte of the data stream S2, the X-level logic gate 150-X can input the Xth byte to the 2Nth byte of the data stream S2 to the Xth level temporary The memory 162-X is used for storage, and the size of the X-level register 162-X can be 2N bytes. On the other hand, if the X-level logic gate 150-X determines that the X-th byte of the data stream S2 is a hexadecimal value "7E", then the first-level logic gate 150-1 can change the count value C(X-1 ) Add one to generate a count value CX, and input the count value CX to the X-stage counter 161-X for storage.

On the other hand, the X-level logic gate 150-X can insert the third stuffing byte into the (Xth) bit of the data stream S2 in response to the match between the Xth byte of the data stream S2 and the second flag byte. +1) Bytes. The X-level logic gate 150-X can shift the (X+1)th byte to the (2N)th byte to insert the third stuffing byte into the (X+1)th bit of the data stream S2 group.

In one embodiment, the second flag byte can be a hexadecimal value "7D", and the third padding byte can be a hexadecimal value "5D". Accordingly, if the X-level logic gate 150-X determines that the X-th byte of the data stream S2 is a hexadecimal value "7D", then the X-level logic gate 150-X can perform processing on the X-th byte Byte padding. In detail, the X-level logic gate 150-X can shift the (X+1)th byte to the (2N)th byte of the data stream S2. After translation, the data originally located in the i-th byte of the data stream S2 will be moved to the (i+1)-th byte of the data stream S2, where i is between X+1 and (2N-1) A positive integer. For example, the data originally located in the (X+1)th byte of data stream S2 will be moved to the (X+2)th byte of data stream S2, and originally located in the (2N)th byte of data stream S2 The byte data will be deleted. After the translation is completed, the X-level logic gate 150-X can write the hexadecimal value "5D" to the (X+1)th byte of the data stream S2 to complete the Xth byte Group fill. After filling the bytes of the Xth byte of the data stream S2, the X-level logic gate 150-X can input the Xth byte to the 2Nth byte of the data stream S2 to the Xth level temporary Memory 162-X for storage. On the other hand, if the X-level logic gate 150-X determines that the X-th byte of the data stream S2 is a hexadecimal value "7D", then the X-level logic gate 150-X can change the count value C(X-1 ) Add one to generate a count value CX, and input the count value CX to the X-stage counter 161-X for storage.

Returning to FIG. 3, similar to the first level or the Xth level of the logic circuit 300 described above, the last level of the logic circuit 300, the (2N-1)th level, can determine whether to compare the data stream S2 to the (2N-1)th level. ) Bytes are filled with bytes. The (2N-1)th level logic gate 151-1(2N-1) can be coupled to the (2N-1)th level counter 161-(2N-1) and the (2N-1)th level register 162-(2N -1). After performing steps similar to the first-level logic gate 151-1 or the X-level logic gate 151-X, the (2N-1)-level logic gate 151-(2N-1) can change the count value C(2N- 1) Input to the (2N-1)th stage counter 161-(2N-1) for storage, and input the data stream S2 to the (2N-1)th stage register 162-(2N-1) for storage, The size of the (2N-1)th level register 162-(2N-1) can be 2N bytes.

The residual gate 170 can be coupled to the (2N-1)th stage counter 161-(2N-1) and the (2N-1)th stage register 162-(2N-1), and can be coupled to the residual counter 181 and Residual register 182. The residual counter 181 and the residual register 182 can be coupled to the output gate 190. The output gate 190 can be coupled to the output register 200. The size of the residual register 182 can be 2N bytes, and can be used to store residual data streams. The residual counter 181 can store a residual count value R, where the residual count value R corresponds to the size of the residual data stream. For example, if the size of the residual data stream is K bytes, the residual count value R can be equal to K, where K is a positive integer between 0 and 2N.

The residual gate 170 can determine the size of the residual data stream in the residual register 182 according to the residual count value R in the residual counter 181. If the size of the residual data stream (or the residual count value R in the residual counter 181) is smaller than the size of the data stream S3 (for example: N bytes), the residual gate 170 can remove the residual data stream in the residual register 182 Combine with the first part of the data stream S2 in the (2N-1)th stage register 161-(2N-1) to generate the data stream S3. The residual gate 170 can determine the size of the first part of the data stream S2 according to the size of the data stream S3 and the residual count value R. The size of the first part of the data stream S2 may be the size of the data stream S3 minus the residual count value R. After the data stream S3 is generated, the residual gate 170 can output the data stream S3 to the output gate 190, and the output gate 190 can use the output register 200 to store and output the data stream S3. Then, the residual gate 170 can configure the second part of the data stream S2 (that is, the remaining part except the first part) as a new residual data stream, and can configure it according to the (2N-1)th counter 161-(2N-1). ) In the count value C(2N-1) and the residual count value R to update the residual count value R, where the updated residual count value R is equal to the sum of the count value C(2N-1) and the original residual count value R ( That is: the updated R=R+C(2N-1)). The new residual data stream can be stored in the residual register 182.

FIG. 6 illustrates a schematic diagram of the operation of the residual gate 170 and the output gate 190 in the clock cycles T1 and T2 according to an embodiment of the present invention. In this embodiment, it is assumed that the logic circuit 300 performs a total of three byte fillings on the data stream S2, so that the data contained in the data stream S2 is expanded from the N bytes of the data stream S1 to (N+3 ) Bytes, and make the count value C(2N-1) equal to 3, where N equals 8. In addition, it is assumed that the size of the residual data stream contained in the residual register 182 is 6 bytes, and the residual count value R in the residual counter 181 is equal to 6.

During the clock period T1, the residual gate 170 may combine the first part of the data stream S2 and the residual data stream in response to the residual count value R (R=6) being less than N (N=8) to generate the data stream S3. The residual gate 170 can determine the second data stream S2 based on the difference between the size of the data stream S3 (ie: N=8) and the residual count value R (ie: R=6) (ie: 8-6=2) The size of one part is equal to 2 bytes. The residual gate 170 can combine the residual data stream in the residual register 182 with the 2 bytes (e.g., the first bit) of the data stream S2 in the (2N-1)th stage register 162-(2N-1). The tuple and the second byte) are combined to generate the data stream S3. After the data stream S3 is output to the output register 200, the residual register 182 can be cleared. The residual gate 170 can configure the second part of the data stream S2 (ie, the remaining 9 bytes) as a new residual data stream, and use the residual register 182 to store the new residual data stream. The residual gate 170 can count the residual in the residual counter 181 according to the sum of the original residual count value R (ie: R=6) and the count value C(2N-1) (ie: C(2N-1)=3) The value R is updated to 9 (ie: 6+3=9).

On the other hand, if the size of the residual data stream (or the residual count value R in the residual counter 181) is greater than or equal to the size of the data stream S3 (for example: N bytes), the residual gate 170 may notify the controller 110 to stop The input gate 130 and the logic circuit 300 operate until the updated residual count value R is less than N. The residual gate 170 can configure the N bytes in the residual data stream S2 as the data stream S3. After the data stream S3 is generated, the residual gate 170 can output the data stream S3 to the output gate 190, and the output gate 190 can use the output register 200 to store and output the data stream S3. Then, the residual gate 170 can update the residual count value R according to the size of the data stream S3 and the residual count value R, where the updated residual count value R is equal to the difference between the original residual count value R and N (ie: the updated R=RN).

FIG. 7 illustrates a schematic diagram of the operation of the residual gate 170 and the output gate 190 during the clock cycles T2 and T3 according to an embodiment of the present invention. In this embodiment, it is assumed that N is equal to 8, and the size of the residual data stream contained in the residual register 182 is 9 bytes, and the residual count value R in the residual counter 181 is equal to 9.

During the clock period T2, the residual gate 170 can notify the controller 110 to stop the operation of the input gate 130 and the logic circuit 300 in response to the residual count value R (ie: R=9) being greater than or equal to N (ie: N=8) . When the input gate 130 and the logic circuit 300 stop operating, no new data stream will be input to the residual register 182. The residual gate 170 can configure the data stream of 8 bytes in the residual data stream S2 as the data stream S3. After the data stream S3 is generated, the residual gate 170 can output the data stream S3 to the output gate 190, and the output gate 190 can use the output register 200 to store and output the data stream S3. Then, the residual gate 170 can update the residual count value R in the residual counter 181 to 1 according to the difference between the original residual count value R (ie: R=9) and the size of the data stream S3 (ie: N=8) (Ie: 9-8=1).

Then, during the clock period T3, the residual gate 170 can determine that the updated residual count value R (ie: R=1) is less than N (ie: N=8). Accordingly, the residual gate 170 can notify the controller 110 to resume the operation of the input gate 130 and the logic circuit 300.

FIG. 8 shows a flowchart of a byte filling method according to an embodiment of the present invention, wherein the byte filling method can be implemented by the byte filling circuit 100 shown in FIG. 3. In step S801, a first data stream is received, wherein the size of the first data stream is N bytes. N can be a positive integer. In step S802, zero-filling is performed on the first data stream to generate a second data stream, wherein the size of the second data stream is 2N bytes. In step S803, check the byte [i] of the second data stream (that is, the i-th byte of the second data stream), where the initial value of i is 1, and i is between 1 and (2N -1) A positive integer. In step S804, it is determined whether the byte [i] of the second data stream matches the hexadecimal value "7E". If yes, go to step S805. If not, go to step S808. In step S805, the byte [i] is overwritten with the hexadecimal value "7D". In step S806, the hexadecimal value "5E" is inserted into the byte group [i+1]. In step S807, i is made equal to (i+1). In step S808, it is determined whether the byte [i] of the second data stream matches the hexadecimal value "7D". If yes, go to step S809. If not, go to step S810. In step S809, the hexadecimal value "5D" is inserted into the byte group [i+1]. In step S810, it is determined whether i is equal to (2N-1). If yes, go to step S811. If not, go to step S807. In step S811, the residual data stream and the first part of the second data stream are combined to generate a third data stream, the second part of the second data stream is configured as a residual data stream, and the third data stream is output.

In summary, the logic circuit of the present invention can perform byte-filling on the data stream and store the byte-filled data stream with an increased size register. If the size of the residual data stream in the residual register is smaller than the preset value, the residual gate may combine a part of the byte-filled data stream with the residual data stream in the residual register to generate an output data stream. If the size of the residual data stream in the residual register is greater than or equal to the preset value, the controller can stop the operation of the logic circuit and the residual gate, so that the controller clears part of the data in the residual register. After some data in the residual register is cleared, the controller can resume the operation of the logic circuit and the residual gate. The logic circuit can continue to perform byte filling for the data stream, and the residual gate can continue to combine a part of the byte filled data stream with the residual data stream in the residual register to generate an output data stream. Therefore, the present invention can perform byte filling on the parallel data, and the byte-filled parallel data can be output correctly.

100: Byte fill circuit 110: Controller 120: Input register 130: input gate 141: Counter 142: Register 150-1: First-order logic gate 150-X: X-level logic gate 150-(2N-1): (2N-1) logic gate 161-1: First-order counter 161-(X-1): (X-1) order counter 161-X: X-order counter 161-(2N-1): (2N-1) level counter 162-1: First-level register 162-(X-1): (X-1) stage register 162-X: X-level register 162-(2N-1): (2N-1) stage register 170: Residual Gate 181: Residual counter 182: Residual register 190: output gate 200: output register 300: logic circuit S1, S2, S3: data flow S801, S802, S803, S804, S805, S806, S807, S808, S809, S810, S811: steps T1, T2, T3: clock cycle

Figure 1 is a schematic diagram of an HDLC data stream. Figure 2 is a schematic diagram of using byte padding to convert a data stream into an HDLC data stream. FIG. 3 illustrates a schematic diagram of a byte filling circuit according to an embodiment of the present invention. FIG. 4 illustrates a schematic diagram of performing byte filling on the first byte of a data stream according to an embodiment of the present invention. FIG. 5 illustrates a schematic diagram of performing byte filling on the Xth byte of a data stream according to an embodiment of the present invention. FIG. 6 illustrates a schematic diagram of the operation of the residual gate and the output gate in the clock cycles T1 and T2 according to an embodiment of the present invention. FIG. 7 illustrates a schematic diagram of the operation of the residual gate and the output gate in the clock cycles T2 and T3 according to an embodiment of the present invention. FIG. 8 shows a flowchart of a method for filling bytes according to an embodiment of the present invention.

100: Byte fill circuit

110: Controller

120: Input register

130: input gate

141: Counter

142: Register

150-1: First-order logic gate

150-X: X-level logic gate

150-(2N-1): (2N-1) logic gate

161-1: First-order counter

161-X: X-order counter

161-(2N-1): (2N-1) level counter

162-1: First-level register

162-X: X-level register

162-(2N-1): (2N-1) stage register

170: Residual Gate

181: Residual counter

182: Residual register

190: output gate

200: output register

300: logic circuit

S1, S2, S3: data flow

Claims (9)

A byte filling circuit includes: The input gate receives a first data stream and generates a second data stream according to the first data stream, wherein the first size of the first data stream is N bytes, and the second data stream is The size is 2N bytes, where N is a positive integer; The logic circuit, coupled to the input gate, includes: The X-level logic gate, in response to the X-th byte of the second data stream being matched with the first flag byte, overwrites the X-th byte with the first padding byte, and replaces the second The padding byte is inserted into the (X+1)th byte of the second data stream, where X is a positive integer between 1 and 2N-1; Residual register to store residual data stream; The residual gate is coupled to the logic circuit and the residual register, wherein the residual gate combines the residual data stream and the first part of the second data stream to generate a third data stream, and the second data stream The second part of the two data streams is configured as the residual data stream; and The output gate is coupled to the residual gate and outputs the third data stream. The byte stuffing circuit according to claim 1, wherein the X-th level logic gate inserts a third stuffing byte in the Xth byte in response to a match between the Xth byte and the second flag byte The (X+1)th byte is described. The byte filling circuit according to claim 1, wherein the third size of the third data stream is N bytes, and the residual gate is based on the fourth size of the residual data stream and the first Three sizes are used to determine the first part of the second data stream. The byte filling circuit described in claim 1, further including: A residual counter, storing a residual count value corresponding to the fourth size of the residual data stream; and A controller coupled to the input gate, the X-th order logic gate, and the residual gate, wherein the controller stops the input gate and the residual gate in response to the first residual count value being greater than or equal to N Operation of the X-level logic gate until the updated residual count value is less than N. The byte filling circuit according to claim 1, wherein the X-th level logic gate is responsive to the X-th byte and the first flag byte and the second flag byte One of the matches increases the count value by one, wherein the residual gate generates the updated residual count value according to the count value and the residual count value. The byte stuffing circuit according to claim 2, wherein the first flag byte is a hexadecimal value "7E", the first stuffing byte is a hexadecimal value "7D", and The second padding byte is a hexadecimal value "5E", wherein the second flag byte is a hexadecimal value "7D", and the third padding byte is a hexadecimal value "5D". The byte filling circuit according to claim 1, wherein the third data stream is parallel data. The byte filling circuit according to claim 1, wherein the input gate zero-fills the first data stream to generate the second data stream. The byte filling circuit according to claim 8, wherein the X-th level logic gate shifts the (X+1)th byte to (2N)th byte in the second data stream by The second stuffing byte is inserted into the (X+1)th byte.

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