TWM558389U - Computer power supply featuring determination of output mode - Google Patents

Abstract

A computer power supply with output mode judgment includes a differential pressure amplifying circuit, a comparing circuit, a linear voltage stabilizing circuit, a driving circuit, and a clamping circuit, and the first and second input ends of the differential pressure amplifying circuit a diode is disposed between the voltage difference amplifying circuit and the first voltage level is output according to whether the diode generates an on-bias voltage, and the comparison circuit outputs a voltage according to the first voltage level and the voltage level of the constant voltage. The second voltage level, the driving circuit drives or does not drive the clamping circuit according to the level of the second voltage level, thereby determining the output mode of the power supply.

Description

Computer power supply with output mode judgment

This creation is about a power supply, especially a computer power supply with output mode judgment.

Refer to Figure 1 for a schematic diagram of the power coupling for a dual power supply. If the ATX power supply provides an unstable power supply or a low wattage power supply, it can cause system instability or errors. Therefore, most of the users face the output power of the old ATX power supply is not enough to provide enough wattage to the upgraded computer system. For this reason, two power supplies with lower output power have been coupled to the power supply. Power supply technology to overcome the above problems.

Please refer to Figure 2 for the schematic diagram of the use of a single power supply to two computer systems. Currently, there is a high-power power supply output to two computer systems. When any one of the computer systems is started, the power supply is Will start, the power supply will be turned off when both computer systems are turned off.

At present, there is no power supply that can cope with the above two situations, and there is no judgment mechanism for judging the above two situations. How to solve the above problems and lacks, that is, the creator of this case and the related manufacturers engaged in this industry Those who want to study the direction of improvement.

In order to improve the above problems, the main purpose of the present invention is to provide a computer power supply having a coupled working mode and a tapping working mode.

Another primary purpose of this creation is to provide a computer power supply with automatic determination of the current output mode.

In order to achieve the above purpose, the present invention provides a computer power supply with an output mode judgment, comprising: a differential pressure amplifying circuit having a first input end, a second input end and an output end, the first A diode is disposed between the input end and the second input end; a comparison circuit has a first input end, a second input end, and an output end, and the second input end of the comparison circuit is connected to the differential pressure to amplify An output terminal of the circuit; a linear regulator circuit having a first end and a second end, wherein the first end of the linear regulator circuit is connected to the first input end of the differential pressure amplifying circuit, and the first of the linear regulator circuits The second end is connected to the first input end of the comparison circuit and outputs a constant voltage; a driving circuit has a first input end, a second input end and an output end, and the first input end of the driving circuit is connected to the comparison circuit And an clamping circuit having an input end, a first output end and a second output end, the input end of the clamping circuit being connected to the output end of the driving circuit.

Through the above structure, the differential pressure amplifying circuit outputs a first voltage level according to whether the diode generates an on-bias voltage, and the comparison circuit outputs a second voltage according to the first voltage level and the voltage level of the constant voltage. At the level, the driving circuit drives or does not drive the clamping circuit according to the level of the second voltage level, thereby determining the output mode of the power supply.

1‧‧‧First power supply

101‧‧‧ differential pressure amplifier circuit

101a‧‧‧ first input

101b‧‧‧ second input

101c‧‧‧output

1011‧‧‧First resistance

1012‧‧‧second resistance

1013‧‧‧ Third resistor

1014‧‧‧fourth resistor

1015‧‧‧Amplifier

1016‧‧‧ Diode

102‧‧‧Comparative circuit

102a‧‧‧ first input

102b‧‧‧second input

102c‧‧‧output

1021‧‧‧First resistance

1022‧‧‧second resistance

1023‧‧‧ Third resistor

1024‧‧ amp amplifier

103‧‧‧Linear regulator circuit

103a‧‧‧ first end

103b‧‧‧second end

1031‧‧‧First resistance

1032‧‧‧Regulator components

1033‧‧‧first capacitor

104‧‧‧ drive circuit

104a‧‧‧ first input

104b‧‧‧second input

104c‧‧‧output

1041‧‧‧dipole

1042‧‧‧First resistance

1043‧‧‧second resistance

1044‧‧‧3rd resistor

1045‧‧‧Optoelectronics

105‧‧‧Clamping circuit

105a‧‧‧ input

105b‧‧‧ first output

105c‧‧‧second output

1051‧‧‧First resistance

1052‧‧‧Optoelectronics

1053‧‧ ‧ diode

106‧‧‧Display circuit

106a‧‧‧ first input

106b‧‧‧second input

1061‧‧‧First resistance

1062‧‧‧second resistance

1063‧‧‧ Third resistor

1064‧‧‧dipole

1065‧‧‧Lighting diode

1066‧‧‧Optoelectronics

107‧‧‧First drive trigger circuit

107a‧‧‧ first input

107b‧‧‧second input

107c‧‧‧output

1071‧‧‧First resistance

1072‧‧‧second resistance

1073‧‧‧ Third resistor

1074‧‧‧fourth resistor

1075‧‧‧first capacitor

1076‧‧‧second capacitor

1077‧‧‧Optoelectronics

108‧‧‧Second drive trigger circuit

108a‧‧‧ first input

108b‧‧‧second input

108c‧‧‧output

1081‧‧‧First resistance

1082‧‧‧second resistance

1083‧‧‧ Third resistor

1084‧‧‧fourth resistor

1085‧‧‧first capacitor

1086‧‧‧second capacitor

1087‧‧‧Optoelectronics

109‧‧‧Drive connection circuit

109a‧‧‧ first input

109b‧‧‧ second input

109c‧‧‧ third input

109d‧‧‧output

1091‧‧‧First Diode

1092‧‧‧Secondary

1093‧‧‧First resistance

1094‧‧‧second resistance

1095‧‧‧Optoelectronics

110‧‧‧Boost circuit

110a‧‧‧ input

110b‧‧‧output

1101‧‧‧Boost unit

1102‧‧‧first capacitor

1103‧‧‧second capacitor

111‧‧‧First output voltage switching control circuit

111a‧‧‧First drive signal input

111b‧‧‧First drive voltage input

111c‧‧‧second drive signal input

111d‧‧‧second drive voltage input

111e‧‧‧First load connection

111f‧‧‧second load connection

112‧‧‧Second output voltage switching control circuit

112a‧‧‧First drive signal input

112b‧‧‧First drive voltage input

112c‧‧‧second drive signal input

112d‧‧‧second drive voltage input

112e‧‧‧First load connection

112f‧‧‧second load connection

113‧‧‧ Third output voltage switching control circuit

113a‧‧‧First drive signal input

113b‧‧‧First drive voltage input

113c‧‧‧second drive signal input

113d‧‧‧second drive voltage input

1136‧‧‧First load connection

113f‧‧‧second load connection

114‧‧‧First power good signal generation circuit

114a‧‧‧ first input

114b‧‧‧second input

114c‧‧‧ third input

114d‧‧‧output

115‧‧‧Second power good signal generation circuit

115a‧‧‧ first input

115b‧‧‧second input

115c‧‧‧ third input

115d‧‧‧output

2‧‧‧Second power supply

3‧‧‧First computer system

4‧‧‧Second computer system

5VSB_1‧‧‧Standby power reference level

5VSB_2‧‧‧Virtual standby power reference level

5‧‧‧Selection switch

51‧‧‧First contact

52‧‧‧second junction

53‧‧‧Common joints

Figure 1 is a schematic diagram of the use of the power supply coupling of the dual power supply; Figure 2 is a schematic diagram of the use of the single power supply to the two computer systems; Figure 3A is the structural block of the first embodiment of the creative power supply FIG. 3B is a circuit diagram of the first embodiment of the authoring power supply device; FIG. 4 is a circuit diagram of the first driving trigger circuit and the second driving trigger circuit; FIG. 5 is a schematic diagram of the creative driving connection circuit Circuit diagram; Figure 6 is a schematic circuit diagram of the creation of the boost circuit; 7 is a circuit diagram of the first output voltage switching control circuit of the creation; FIG. 8 is a circuit diagram of the second output voltage switching control circuit; FIG. 9 is a circuit diagram of the third output voltage switching control circuit. FIG. 10 is a circuit diagram of the first power good signal generating circuit and the second power good signal generating circuit; FIG. 11 is a circuit diagram of the second embodiment of the authoring power supply.

The above object of the present invention, as well as its structural and functional features, will be described in accordance with the preferred embodiments of the drawings.

Please refer to FIG. 3A and FIG. 3B , which are structural block diagrams and circuit diagrams of the first embodiment of the present invention, and with reference to FIG. 1 and FIG. 2 , the first power supply 1 of the present invention is based on The power supply coupling mode of FIG. 1 can be selected, and the power of the second power supply 2 is supplied to the first power supply 1 and then output to the first power supply 1 by the first power supply 1 The computer system 3, or the power tapping operation mode as shown in FIG. 2, is provided by the first power supply 1 to the first computer system 3 or the second computer system 4, and the circuit architecture disclosed in FIGS. 3A and 3B And being disposed in the first power supply 1 and performing a judgment output operation mode.

First defined here, the resistors and capacitors mentioned later have no polarity or directionality. In the figure, the upward or left end is called the first end, and the downward or right end is called the second. The anode of the terminal, the diode or the light-emitting diode is called the first end, and the cathode is called the second end. The PS-on_1 and the PS-on_2 are the start signals transmitted by the computer system to the power supply.

The differential amplifier circuit 101 includes a first resistor 1011, a second resistor 1012, a third resistor 1013, a fourth resistor 1014, and an amplifier 1015. The second end of the first resistor 1011 and the second The first end of the resistor 1012 and the non-inverting input end of the amplifier 1015 are connected in common. The first end of the first resistor 1011 is the first input end 101a of the differential pressure amplifying circuit 101, and the second end of the second resistor 1012. The second end of the third resistor 1013, the first end of the fourth resistor 1014, and the inverting input end of the amplifier 1015 are connected in common. The first end of the third resistor 1013 is the differential pressure amplifying circuit 101. The second input end 101b of the fourth resistor 1014 is connected to the output end of the amplifier 1015. The output end of the amplifier 1015 is the output end 101c of the differential pressure amplifying circuit 101.

The comparison circuit 102 includes a first resistor 1021, a second resistor 1022, a third resistor 1023, and an amplifier 1024. The second terminal of the first resistor 1021, the first terminal of the second resistor 1022, and the amplifier 1024 The non-inverting input terminal is connected in common, the first end of the first resistor 1021 is the first input end 102a of the comparison circuit 102, and the second end of the second resistor 1022 is connected to the output end of the amplifier 1024, the third resistor The second end of the amplifier 1024 is connected to the inverting input terminal of the amplifier 1024. The first end of the third resistor 1023 is the second input terminal 102b of the comparison circuit 102. The output terminal of the amplifier 1024 is the comparison circuit 102. Output 102c.

The linear regulator circuit 103 includes a first resistor 1031, a voltage stabilizing component 1032, and a first capacitor 1033. The second terminal of the first resistor 1031 and the second terminal of the voltage stabilizing component 1032 are connected. The first capacitor The first end of the first capacitor 1033 is commonly connected to the first end of the voltage stabilizing element 1032, and the first end of the first resistor 1031 is connected to the third end of the voltage stabilizing element 1032. That is, the first end 103a of the linear regulator circuit 103, the first end of the first capacitor 1033 and the third end of the voltage stabilizing element 1032 are connected to each other to be the second end of the linear regulator circuit 103.

The driving circuit 104 includes a diode 1041, a first resistor 1042, a second resistor 1043, a third resistor 1044, and a transistor 1045. The second end of the diode 1041 and the first resistor 1042 Connected at one end, the second end of the first resistor 1042, the first end of the second resistor 1043, and the electronic crystal The gate end of the body 1045 is connected in common, the second end of the second resistor 1043 and the second end of the third resistor 1044 are commonly grounded, and the first end of the third resistor 1044 and the source terminal of the transistor 1045 are connected in common. The drain terminal of the transistor 1045 is the second input terminal 104b of the driver circuit 104, and the source terminal of the transistor 1045 is the output terminal 104c of the driver circuit 104.

The clamping circuit 105 includes a first resistor 1051, a transistor 1052 and a diode 1053. The second end of the first resistor 1051 is connected to the gate terminal of the transistor 1052. The first end of the diode 1053 is connected. The second terminal of the diode 1053 and the second terminal of the first resistor 1051 are connected in common, and the gate terminal of the transistor 1052 is the input end of the clamping circuit 105. 105a, the second end of the diode 1053 is the first output end 105b of the clamping circuit 105, and the 汲 terminal of the transistor 1052 is the second output end 105c of the clamping circuit 105.

The display circuit 106 includes a first resistor 1061, a second resistor 1062, a third resistor 1063, a diode 1064, a light emitting diode 1065 and a transistor 1066. The second end of the first resistor 1061 is The second end of the light emitting diode 1065 is connected to the first end of the light emitting diode 1065, and the second end of the light emitting diode 1066 is connected to the second end of the diode 1064 and the second resistor 1062. The first end is connected in common, the second end of the second resistor 1062, the first end of the third resistor 1063 and the gate end of the transistor 1066 are connected together, the source terminal of the transistor 1066 and the third resistor 1063 The first end of the first resistor 1061 is the second input end 106b of the display circuit 106. The first end of the diode 1064 is the first input end 106a of the display circuit 106.

The first input end 101a of the differential pressure amplifying circuit 101, the second input end 104b of the driving circuit 104, and the second input end 106b of the display circuit 106 are connected to a standby power reference level 5VSB_1, and the differential pressure amplifying circuit 101 The second input 101b is connected to a virtual standby power reference The resistance of the first resistor 1011 and the third resistor 1013 is the same, and the resistance values of the second resistor 1012 and the fourth resistor 1014 are the same.

The standby power reference level 5VSB_1 is the standby power of the first power supply 1. In the power coupling operation mode, the virtual standby power reference level 5VSB_2 is the standby power of the second power supply 2, because the first power supply 1 The standby power supply and the standby voltage of the second power supply 2 have a very small difference (for example, the standby power reference level 5VSB_1 is 5.2v, and the virtual standby power reference level 5VSB_2 is 5.1v), which cannot satisfy the bias voltage of the diode 1016. After the voltage difference (for example, 0.1v) between the inverting input terminal and the non-inverting input terminal of the input amplifier 1015 is amplified (for example, 10 times), the amplified voltage (0.1v*10=1v) is outputted from the output terminal of the amplifier 1015 to the amplifier. The inverting input of 1024, the non-inverting input of the amplifier 1024 is output by the linear regulator circuit 103 by a fixed voltage (for example, 2.5v), and the amplifier 1024 is based on the inverting input terminal (1v) and the non-inverting input terminal (2.5). v) the input voltage is high and low outputting a high voltage level, and the diode 1064 in the display circuit 106 thus passes through the transistor 1066, so that the light emitting diode 1065 is turned on and emits light to know that the current power coupling operation mode is the same. Drive The diode 1041 in the driving circuit 104 outputs a high level signal (MD) to the clamping circuit 105 to turn on the transistor 1052 in the clamping circuit 105 when the first computer system 3 sends a power on command. When the PS-on_1 of the first output terminal 105b is pulled to the low voltage level, regardless of whether the PS-on_2 of the second output terminal 105c is at a high level or a ground level, the transistor 1052 is turned on and pulled. At the low level, the second power supply 2 is activated because PS-on_2 is at a low level, and the effect of starting the first power supply 1 and the second power supply 2 by a control command is reached.

When the virtual standby power reference level 5VSB_2 is connected to the second computer system 4 in the power tapping mode, the virtual standby power reference level 6VSB_2 is not connected to the active load, because the standby power of the first power supply 1 and The voltage between the two computer systems 4 is very different (standby power supply) The reference level 5VSB_1 is 5.2v, and the second computer system 4 virtual standby power reference level 5VSB_2 is 0v), which satisfies the bias voltage of the diode 1016 (about 0.35 voltage drop), and the input amplifier 1015 has an inverting input terminal and The voltage difference (5.2v-4.85v=0.35v) of the non-inverting input terminal is amplified (for example, 10 times), and the amplified voltage (0.35v*10=3.5v) is output from the output terminal of the amplifier 1015 to the amplifier 1024. On the inverting input, the non-inverting input of the amplifier 1024 is outputted by the linear regulator circuit 103 by a fixed voltage (for example, 2.5v), and the amplifier 1024 is based on the non-inverting input terminal (2.5v) and the inverting input terminal (3.5v). The input voltage is high and low, and the low voltage level is output. The diode 1041 and the diode 1064 cannot be turned on. The LEDs 1065 in the display circuit 106 are not lit to know that the current power tap mode is driving. The diode 1041 in the circuit 104 does not turn on the transistor 1045, and the clamp circuit 105 does not cause mutual clamping of PS-on_1 and PS-on_2.

The main function of the display circuit 106 is to indicate the current operating mode of the first power supply 1 through the change of the light-emitting diodes 1065. The overall output mode determination has no substantial influence, so the display circuit 106 can be omitted. In order to reduce the cost, the light-emitting diodes 1065 can also be changed to other different types of components such as speakers, and sounds can be used to achieve different working modes.

Please refer to FIG. 4 , which is a circuit diagram of the first driving trigger circuit and the second driving trigger circuit. The first driving trigger circuit 107 has a first input end 107 a , a second input end 107 b , and an output end 107 c . The second driving trigger circuit 108 has a first input terminal 108a, a second input terminal 108b, and an output terminal 108c. The first input terminal 107a of the first driving trigger circuit 107 and the clamping circuit 105 The first output terminal 105b is connected to the second input terminal 107b of the first driving trigger circuit 107, and the standby power reference level 5VSB_1 is connected to the second driving trigger circuit 108. The first input end 108a is connected to the second output end 105c of the clamp circuit 105. The second input end 108b of the second drive trigger circuit 108 is connected to the standby power reference level 5VSB_1.

The first driving trigger circuit 107 includes a first resistor 1071, a second resistor 1072, a third resistor 1073, a fourth resistor 1074, a first capacitor 1075, a second capacitor 1076, and a transistor 1077. The first end of the first resistor 1071 and the first end of the second resistor 1072 are connected in common, and the second end of the second resistor 1072, the first end of the third resistor 1073, and the source terminal of the transistor 1077 are connected together. The second end of the first resistor 1071, the second end of the third resistor 1073, the first end of the first capacitor 1075, and the gate terminal of the transistor 1077 are connected together, and the second end of the first capacitor 1075 The first end of the third resistor 1073 and the first end of the second capacitor 1076 are connected in common, the second end of the third resistor 1073 and the second end of the second capacitor 1076 are connected. The first terminal 107a of the first driving trigger circuit 107 is the first terminal 107a of the first driving trigger circuit 107. The first terminal of the first resistor 1071 is the first terminal of the first driving trigger circuit 107. The second input terminal 107b, the 汲 terminal of the transistor 1077 is the output terminal 107c of the first driving trigger circuit 107 .

The second driving trigger circuit 108 includes a first resistor 1081, a second resistor 1082, a third resistor 1083, a fourth resistor 1084, a first capacitor 1085, a second capacitor 1086, and a transistor 1087. The first end of the first resistor 1081 and the first end of the second resistor 1082 are connected in common, and the second end of the second resistor 1082, the first end of the third resistor 1083, and the source terminal of the transistor 1087 are connected The second end of the first resistor 1081, the second end of the third resistor 1083, the first end of the first capacitor 1085, and the gate terminal of the transistor 1087 are connected together, and the second end of the first capacitor 1085 Grounding, the 汲 terminal of the transistor 1085, the first end of the third resistor 1083 and the first end of the second capacitor 1086 are connected in common, the second end of the third resistor 1083 and the second end of the second capacitor 1086 The terminal is commonly grounded, and the gate terminal of the transistor 1087 is the first input terminal 108a of the second driving trigger circuit 108, the first The first end of the resistor 1081 is the second input terminal 108b of the second driving trigger circuit 108. The drain terminal of the transistor 1087 is the output terminal 108c of the second driving trigger circuit 108.

Referring to FIG. 3A and FIG. 3B together, the first end of the first resistors 1071 and 1081 is connected to the standby power reference level 5VSB_1, the second end of the first resistor 1071 is coupled to PS-on_1, and the second resistor is first. The end coupling PS-on_2, PS-on_1 and PS-on_2 before the first computer system 3 or the second computer system 4 has not been started, as long as the first power supply 1 is powered, PS-on_1 and PS-on_2 are Will be a high standard.

In the coupled mode of operation, since the gate terminal of the transistor 1052 is at a high level and is in a conducting state, and is only connected to the first computer system 3, the power-on command issued when the first computer system 3 is started will pull the PS-on_1 At the low level, PS-on_2 also turns on the transistor 1052 to become a low level, so that the second power supply 2 is started together, and the VG1 of the output terminal 107c and the VG2 of the output terminal 108c become the high level.

In the tap mode, since the gate terminal of the transistor 1052 is at a low level and is in a non-conducting state, there is no mutual influence between PS-on_1 and PS-on_2, and the booting when the first computer system 3 is started The command will only pull PS-on_1 to the low level, making VG1 high. When the second computer system 4 starts, the power-on command will only pull PS-on_2 to the low level, making VG2 high. .

Please refer to FIG. 5 , which is a circuit diagram of the driving circuit of the present invention. Referring to FIG. 4 , the driving connection circuit 109 has a first input end 109 a , a second input end 109 b , and a third input end 109 c . And an output end 109d, the first input end 109a of the drive connection circuit 109 is connected to the output end 107c of the first drive trigger circuit 107, the second input end 109b of the drive connection circuit 109 and the second The output terminal 108c of the driving trigger circuit 108 is connected, and the third input terminal 109c of the driving connection circuit 109 is connected to the standby power reference level 5VSB_1.

The driving connection circuit 109 includes a first diode 1091, a second diode 1092, a first resistor 1093, a second resistor 1094, and a transistor 1095. The second end of the first diode 1091 The second end of the second diode 1092 and the first end of the first resistor 1093 are connected in common. The second end of the first resistor 1093 is connected to the base end of the transistor 1095. The second resistor 1094 The second end is connected to the collector terminal of the transistor 1095. The emitter terminal of the transistor 1095 is grounded. The first end of the first diode 1091 is the first input terminal 109 of the driving connection circuit 109. The first end of the second diode 1092 is the second input end 109b of the driving connection circuit, and the first end of the first resistor 1091 is the third input end 109c of the driving connection circuit 109. The collector terminal of the crystal 1095 is the output terminal 109d of the drive connection circuit 109.

In the coupled mode of operation, since the transistor 1045 is turned on, the PS-on_1 of the first computer system 3 will cause PS-on_2 to become a low level, and VG1 and VG2 become a high level to turn on the transistor 1095. The PS_ON of the output terminal 109d will become a low level, thereby achieving the effect of starting the first power supply 1 and the second power supply 2 through a power-on command, but actually the first computer system 3 supplies the first power supply. When the power-on command of the device 1 causes the PS-on_1 to become the low level, the PS-on_2 becomes the low level due to the clamp circuit 105 and directly outputs the VG2 through the second drive trigger circuit 108, so the second power supply 2 will be the first. The power supply 1 starts up faster, and the time difference between the two sides of the power supply is compensated.

In the tap mode, the level changes of VG1 and VG2 are changed according to whether PS-on_1 and PS-on_2 are different. When either of VG1 or VG2 becomes high level, transistor 1095 turns on to make PS_ON of output 109d. Will become a low level, thereby causing the first power supply 1 to be activated, and when either or both of the first computer system 3 or the second computer system 4 are in the power-on state, the first power supply 1 is Will remain in the working state, when the first computer system 3 and the second computer system 4 are in the off state, the first power supply 1 will stop working.

Please refer to FIG. 6 , which is a circuit diagram of the boost circuit of the present invention. The boost circuit 110 has an input terminal 110 a and an output terminal 110 b. The boost circuit 110 includes a boosting unit 1101 and a first a first end of the boosting unit 1101 is connected to the first end of the first capacitor 1102, and a second end of the boosting unit 1101 is connected to the first end of the second capacitor 1103. The second ends of the first and second capacitors 1102 and 1103 are grounded, the first end of the boosting unit 1101 is the input end 110a, and the second end of the boosting unit 1101 is the output end 110b. The input terminal 110a of the boosting circuit 110 is connected to the standby power reference level 5VSB_1, and the voltage is boosted by the boosting unit 1101 to drive the subsequent circuit and the fully conductive crystal element, and is supplied to the subsequent circuit by the output terminal 110b.

Please refer to FIG. 7 , which is a circuit diagram of the first output voltage switching control circuit for controlling the 12V output of the first power supply 1 . The first output voltage switching control circuit 111 has a first driving signal input end. 111a, a first driving voltage input terminal 111b, a second driving signal input terminal 111c, a second driving voltage input terminal 111d, a first load connecting end 111e and a second load connecting end 111f, the first driving signal The input end 111a is connected to the output end 107c of the first driving trigger circuit 107, and the second driving signal input end 111c is connected to the output end 108c of the second driving trigger circuit 108, the first driving voltage input end 111b and the second driving The voltage input terminal 111d is connected to the output terminal 110b of the booster circuit 110, respectively.

In Fig. 7, power transistors Q12 and Q33 are main switching switches, 12V_A of the first load connection end 111e is the output/input voltage of the first power supply 1, and 12V_B of the second load connection end 111f is the first The output/input voltage of the two power supply 2, ZD3, D9 is the power of the power transistor Q12 Pressure clamp, ZD4, D10 is the voltage clamp of power transistor Q33, to protect the Vgs voltage of power transistors Q12, Q33 will not be greater than the rated withstand voltage, C10, R33 and C13, R39 is slow start damping, with R34, C11 and R63, C12 constitute the fine-tuning on-time of power transistors Q12 and Q33, Q13, Q14 and Q17, Q18 are drive circuits, providing power transistors Q12, Q33 with sufficient driving time for conduction and discharge, Q15, Q16 and Q19, Q20 determine whether to provide drive loop energy according to the commands of VG1 and VG2.

The first driving voltage input terminal 111b and the second driving voltage input terminal 111d receive the voltage outputted from the output terminal 110b of the boosting circuit 110, in order to provide a complete driving voltage (about 8V) of the power transistors Q12 and Q33 (N-MOSFET). Therefore, the boosting circuit 110 needs to raise the 5V provided by the standby power reference level 5VSB_1 to 20V (about 4 times), and has provided a driving subsequent circuit (12V) and a fully conductive crystal element (8V), depending on the selected Different types of power transistors Q12 and Q33 or breakthroughs in future technologies. When the complete driving voltage of power transistors Q12 and Q33 changes, the boosting ratio of booster circuit 110 can also be changed to cope with changes in actual use. .

Please refer to FIG. 8 , which is a circuit diagram of the second output voltage switching control circuit for controlling the 5V output of the first power supply 1 . The second output voltage switching control circuit 112 has a first driving signal input end. 112a, a first driving voltage input terminal 112b, a second driving signal input terminal 112c, a second driving voltage input terminal 112d, a first load connecting end 112e and a second load connecting end 112f, the first driving signal The input end 112a is connected to the output end 107c of the first driving trigger circuit 107, and the second driving signal input end 112c is connected to the output end 108c of the second driving trigger circuit 108. The second output voltage switches the first driving of the control circuit 112. The voltage input terminal 112b is connected to the first load connection end 111e of the first output voltage switching control circuit 111, and the second output voltage is switched. The second driving voltage input terminal 112d of the control circuit 112 is connected to the second load connection terminal 111f of the first output voltage switching control circuit 111.

In Fig. 8, the internal structure is similar to the composition of Fig. 7, and its working principle is also substantially the same, so it will not be described again here, and the difference lies in the first driving voltage input terminal 112b and the second driving voltage input terminal 112d. The required driving voltage is provided by the first load connection end 111e of the first output voltage switching control circuit 111 and the second load connection end 111f outputting 12V, the purpose of which is to determine that the first output voltage switching control circuit 111 is the first power supply. The main energy of the supplier 1 is not necessary for the second output voltage switching control circuit 112 if the first output voltage switching control circuit 111 is not operating.

Please refer to FIG. 9 , which is a circuit diagram of the third output voltage switching control circuit for controlling the 3.3V output of the first power supply 1 . The third output voltage switching control circuit 113 has a first driving signal input. The first driving voltage input terminal 113b, a second driving signal input terminal 113c, a second driving voltage input terminal 113d, a first load connecting end 113e and a second load connecting end 113f, the first driving The signal input terminal 113a is connected to the output terminal 107c of the first driving trigger circuit 107, and the second driving signal input terminal 113c is connected to the output terminal 108c of the second driving trigger circuit 108. The third output voltage switching control circuit 113 is first. The driving voltage input end 113b is connected to the first load connection end 111e of the first output voltage switching control circuit 111, and the second driving voltage input end 113d of the third output voltage switching control circuit 113 is connected to the first output voltage switching control. The second load connection terminal 111f of the circuit 111.

In the ninth figure, the internal structure is similar to that of the seventh figure, and the working principle thereof is also substantially the same, so it will not be described again here, and the difference lies in the first driving voltage input terminal 113b and the second driving voltage input terminal 113d. The required driving voltage is provided by the first load connection end 111e of the first output voltage switching control circuit 111 and the second load connection end 111f outputting 12V, the purpose of which is to determine that the first output voltage is cut. The switching control circuit 111 is the main energy of the first power supply 1. If the first output voltage switching control circuit 111 does not operate, the third output voltage switching control circuit 113 does not have an output.

The control commands of the power transistors Q21 and Q22 in FIG. 8 and the power transistors Q31 and Q32 in FIG. 9 can be provided by VT_A and VT_B while retaining the on-times of the power transistors Q21 and Q22 and the power transistors Q31 and Q32. Fine-tuning needs.

In the coupled mode of operation, the PS-on_2 signal is pinned by the PS-on_1 signal, so when the first computer system 3 starts up and the PS-on_1 signal is lowered to the low level, the first power supply 1 and the second power supply The device 2 is activated, and both VG1 and VG2 are high-level, and the switching switches Q12 and Q33 of the first output voltage switching control circuit 111, the switching switches Q21 and Q22 of the second output voltage switching control circuit 112, and the third output voltage are known. The switching switches Q31 and Q32 of the switching control circuit 113 are all driven to be turned on. At this time, the power supplies 12V_B, 5V_B, 3.3V_B generated by the second power supply 2 are coupled to the power sources 12V_A, 5V_A generated by the first power supply 1. , 3.3V_A, to achieve the power coupling effect.

In the tap mode, the PS-on_1 signal and the PS-on_2 signal are independently controlled by the first computer system 3 and the second computer system 4. When any computer system starts and issues a power-on command, the first power supply 1 The VG1 or VG2 signal becomes high level and PS_ON is issued to start the first power supply 1 and provide three sets of output voltages such as 12V, 5V, and 3.3V. For example, when the first computer system 3 is turned on, VG1 becomes high. Level, switch Q12, Q21, Q31 turn on 12V, 5V, 3.3V to 12V_A, 5V_A, 3.3V_A to provide the working energy required by the first computer system 3, when the second computer system 4 is also turned on, VG2 When it becomes high level, the switches Q33, Q22, and Q32 are turned on to send 12V, 5V, and 3.3V to 12V_B, 5V_B, and 3.3V_B to provide the working energy required by the second computer system 4.

Please refer to FIG. 10, which is a circuit diagram of the first power good signal generating circuit and the second power good signal generating circuit for generating a power good signal. The first power source is good. The signal generating circuit 114 has a first input end 114a, a second input end 114b, a third input end 114c and an output end 114d. The first input end 114a of the first power good signal generating circuit 114 is connected to the clamp. The first output end 105b of the circuit 105 is connected, and the second input end 114b of the first power good signal generating circuit 114 is connected to the first load connection end 112 of the second output voltage switching control circuit 112. The first power supply is good. The third input end 114c of the signal generating circuit 114 is connected to the standby power reference level 5VSB_1, and the output end 114d of the first power good signal generating circuit 114 outputs a first power good signal PG_1, and the second power good signal is generated. The circuit 115 has a first input terminal 115a, a second input terminal 115b, a third input terminal 115c and an output terminal 115d. The first input terminal 115a of the second power good signal generating circuit 115 is connected to the clamping circuit 105. The second output terminal 105c is connected to the second input terminal 115b of the second power good signal generating circuit 115 and the second load terminal 1 of the second output voltage switching control circuit 112. 11f is connected, the third input end 115c of the second power good signal generating circuit 115 is connected to the standby power reference level 5VSB_1, and the output end 115d of the second power good signal generating circuit 1115 outputs a second power good signal PG_2 .

Before the host system corresponding to PS-on_1 and PS-on_2 has not issued the power-on command, regardless of the current working mode, the first power good signal PG_1 and the second power good signal PG_2 will be maintained by R26, Q9 and R29, Q10. At low level, when either PS-on_1 or PS-on_2 becomes low level, Q7 and Q8 turn on to pull 5V_A or 5V_B to ZD1 or ZD2 respectively. If the voltage is higher than ZD1 or ZD2, the corresponding Q9 Q10 will be turned on and pull up PG_1 or PG_2.

In the coupled mode of operation, since PG_2 is not actually connected to the load (for example, the second computer system 4), PG_2 is regarded as an invalid signal.

In the tap mode, PG_1 or PG_2 correctly determines whether the output voltages 5V_A and 5V_B reach the recess voltage of ZD1 or ZD2, and receive the first computer system 3 and the second computer system 4 at PS-on_1 and PS-on_2. When the shutdown command (position is pulled high), Q7 and Q10 will be turned off immediately, and PG_1 or PG_2 will immediately return to the low level. At this time, VG1 and VG2 will be maintained because the second capacitors 1076 and 1086 are electrolytic capacitors. A little time is at a high level, and driving three sets of voltage output switches, to achieve the need for the PG signal to be pulled lower than the power signal when the ATX power is turned off.

Please refer to FIG. 11 , which is a schematic circuit diagram of a second embodiment of the present invention. Referring to FIG. 3A and FIG. 3B , the present embodiment is substantially the same as the first embodiment, so the details are not described again. The difference is that the differential pressure amplifying circuit 101 is connected to a selection switch 5 having a first contact 51, a second contact 52 and a common contact 53, the first contact 5 and the The second input terminal 101b of the differential pressure amplifying circuit 101 is connected to the output terminal 101c of the differential pressure amplifying circuit 101, and the common contact 53 and the first input end of the differential pressure amplifying circuit 101 101a connection.

When the operation button of the selection switch 5 is slid to the left side, the first contact 51 and the common contact 53 are short-circuited to force the first power supply 1 into the coupling operation mode, and the light-emitting diode 1065 is illuminated. When the operation button of the selection switch 5 slides to the right side, the second contact 52 is short-circuited with the common contact 53 to force the first power supply 1 to enter the tapping operation mode, and the differential pressure amplifying circuit 101 is disabled by the selection switch 5. Force the power supply into the coupled mode or tap mode.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of protection is subject to the definition of the scope of the attached patent application.

Claims (20)

A computer power supply with an output mode determination, comprising: a differential pressure amplifying circuit having a first input end, a second input end and an output end, the first input end and the second input end a diode is disposed between the first input terminal, a second input terminal and an output terminal, and the second input end of the comparison circuit is connected to the output end of the differential pressure amplifying circuit; The circuit has a first end and a second end, the first end of the linear regulator circuit is connected to the first input end of the differential pressure amplifying circuit, and the second end of the linear voltage stabilizing circuit is connected to the first end of the comparison circuit The input terminal outputs a constant voltage; a driving circuit has a first input end, a second input end and an output end, the first input end of the driving circuit is connected to the output end of the comparing circuit; and a clamping circuit has An input end, a first output end and a second output end, the input end of the clamp circuit is connected to the output end of the driving circuit; the differential pressure amplifying circuit outputs a first turn according to whether the diode generates a conduction bias Electricity a comparison circuit, the comparison circuit outputs a second voltage level according to the first voltage level and the voltage level of the constant voltage, and the driving circuit drives or does not drive the clamping circuit according to the level of the second voltage level, thereby determining The output mode of the power supply. The computer power supply device with the output mode determination according to the first aspect of the invention, wherein the comparison circuit is connected to a display circuit, the display circuit has a first input end and a second input end, the display A first input of the circuit is coupled to the output of the comparison circuit. The computer power supply device with the output mode determination as described in claim 2, wherein the display circuit comprises a first resistor, a second resistor, a third resistor, a diode, and a light emitting diode. a second body of the first resistor is coupled to the first end of the light emitting diode, and a second end of the light emitting diode is coupled to the anode end of the transistor, the pole The second end of the body is coupled to the first end of the second resistor, the second end of the second resistor, the first end of the third resistor and the gate terminal of the transistor are connected together, the source terminal of the transistor Cooperating with the second end of the third resistor, the first end of the first resistor is a second input end of the display circuit, and the first end of the diode is a first input end of the display circuit. The computer power supply with output mode determination according to claim 2, wherein the first input end of the differential pressure amplifying circuit, the second input end of the driving circuit, and the second input of the display circuit The terminal is connected to a standby power reference level. The power supply for a computer having an output mode determination according to the first aspect of the invention, wherein the differential pressure amplifying circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, and a An amplifier, the second end of the first resistor, the first end of the second resistor, and the non-inverting input end of the amplifier are connected in common, and the first end of the first resistor is the first input end of the differential pressure amplifying circuit The second end of the second resistor is grounded, the second end of the third resistor, the first end of the fourth resistor, and the inverting input end of the amplifier are connected in common, and the first end of the third resistor is a voltage The second input end of the differential amplifier circuit is connected to the output end of the amplifier, and the output end of the amplifier is the output end of the differential pressure amplifying circuit. The computer power supply with output mode determination according to the first aspect of the invention, wherein the comparison circuit comprises a first resistor, a second resistor, a third resistor and an amplifier, the first resistor The second end, the first end of the second resistor and the non-inverting input end of the amplifier are connected in common, the first end of the first resistor is a first input end of the comparison circuit, and the second end of the second resistor Connecting the output end of the amplifier, the second end of the third resistor is serially connected to the inverting input end of the amplifier, and the first end of the third resistor is the second input end of the comparison circuit, and the output end of the amplifier This is the output of the comparison circuit. The power supply for a computer having an output mode determination according to the first aspect of the invention, wherein the linear regulator circuit comprises a first resistor, a voltage stabilizing component and a first capacitor, the first resistor The second end is connected to the second end of the voltage stabilizing component, and the first end of the first capacitor is connected to the third end of the voltage stabilizing component, and the second end of the first capacitor and the first end of the voltage stabilizing component The first end of the first resistor is the first end of the linear voltage stabilizing circuit, and the first end of the first capacitor and the third end of the voltage stabilizing component are connected to each other The second end of the voltage circuit. The power supply for a computer having an output mode determination according to the first aspect of the invention, wherein the driving circuit comprises a diode, a first resistor, a second resistor, a third resistor, and a transistor. The second end of the diode is connected to the first end of the first resistor, and the second end of the first resistor, the first end of the second resistor, and the gate terminal of the transistor are connected together. The second end of the second resistor and the second end of the third resistor are commonly grounded, the first end of the third resistor is connected to the source terminal of the transistor, and the drain of the transistor The terminal is the second input of the driving circuit, and the source terminal of the transistor is the output of the driving circuit. The power supply for a computer having an output mode determination according to the first aspect of the invention, wherein the clamping circuit comprises a first resistor, a transistor and a diode, and the second end of the first resistor is The gate end of the transistor is connected in common, the first end of the diode is connected to the source terminal of the transistor, and the second end of the diode is connected to the second end of the first resistor. The gate terminal of the crystal is the input end of the clamp circuit, the second end of the diode is the first output end of the clamp circuit, and the drain terminal of the transistor is the second output end of the clamp circuit. The power supply for a computer having an output mode determination according to the fourth aspect of the invention, wherein the clamp circuit is coupled to a first drive trigger circuit and a second drive trigger circuit, the first drive trigger circuit having a first An input terminal, a second input terminal and an output terminal, the second driving trigger circuit has a first input end, a second input end and an output end, the first input end of the first driving trigger circuit Connected to the first output end of the clamping circuit, the second input end of the first driving trigger circuit is connected to the standby power reference level, the first input end of the second driving trigger circuit and the clamping circuit The second output terminal is connected, and the second input terminal of the second driving trigger circuit is connected to the standby power reference level. The power supply for a computer having an output mode determination according to claim 10, wherein the first driving trigger circuit comprises a first resistor, a second resistor, a third resistor, and a fourth resistor. a first capacitor, a second capacitor, and a transistor, the first end of the first resistor and the first end of the second resistor are connected in common, and the second resistor is a second end, a first end of the third resistor and a source terminal of the transistor, the second end of the first resistor, the second end of the third resistor, the first end of the first capacitor, and the The gate end of the crystal is connected in common, the second end of the first capacitor is grounded, the first end of the third resistor and the first end of the second capacitor are connected in common, and the third resistor is connected The second end of the second capacitor and the second end of the second capacitor are commonly grounded, and the gate terminal of the transistor is the first input end of the first driving trigger circuit, and the first end of the first resistor is the first driving The second input end of the trigger circuit, the drain terminal of the transistor is the output end of the first driving trigger circuit. The power supply for a computer having an output mode determination according to claim 10, wherein the second driving trigger circuit comprises a first resistor, a second resistor, a third resistor, and a fourth resistor. a first capacitor, a second capacitor, and a transistor, the first end of the first resistor and the first end of the second resistor are connected in common, the second end of the second resistor, the first end of the third resistor The terminal and the source terminal of the transistor are connected in common, the second end of the first resistor, the second end of the third resistor, the first end of the first capacitor, and the gate terminal of the transistor are connected together, the first The second end of the capacitor is grounded, the first end of the third resistor and the first end of the second capacitor are connected together, the second end of the third resistor and the second end of the second capacitor The terminal is commonly grounded, the gate terminal of the transistor is the first input end of the second driving trigger circuit, and the first end of the first resistor is the second input end of the second driving trigger circuit, The 汲 terminal of the transistor is the output of the second drive trigger circuit. The computer power supply with output mode determination according to claim 10, wherein the first driving trigger circuit and the second driving trigger circuit are connected in common a driving connection circuit having a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal of the driving connection circuit and the first driving trigger circuit The output end of the driving connection circuit is connected to the output end of the second driving trigger circuit, and the third input end of the driving connection circuit is connected to the standby power reference level. The power supply for a computer having an output mode determination according to claim 13 , wherein the driving connection circuit comprises a first diode, a second diode, a first resistor, and a second a resistor and a transistor, the second end of the first diode, the second end of the second diode, and the first end of the first resistor are connected together, and the second end of the first resistor and the electric The base end of the crystal is connected in common, the second end of the second resistor is connected to the collector terminal of the transistor, the emitter end of the transistor is grounded, and the first end of the first diode is the driving connection a first input end of the circuit, the first end of the second diode is a second input end of the driving connection circuit, and the first end of the first resistor is a third input end of the driving connection circuit, The collector terminal of the transistor is the output of the drive connection circuit. The power supply for a computer having an output mode determination according to claim 10, wherein the standby power reference is connected to a booster circuit, and the booster circuit has an input end and an output end. The boosting circuit includes a boosting unit, a first capacitor and a second capacitor, the first end of the boosting unit is connected to the first end of the first capacitor, and the second end of the boosting unit is The first end of the second capacitor is connected, the second end of the first and second capacitors is grounded, the first end of the boosting unit is the input end, and the second end of the boosting unit is the output end. The computer power supply with output mode determination according to claim 15, wherein the first driving trigger circuit, the second driving trigger circuit and the boosting circuit are connected to a first output voltage switching control The first output voltage switching control circuit has a first driving signal input terminal, a first driving voltage input terminal, a second driving signal input terminal, a second driving voltage input terminal, and a first load connecting terminal. a second load connection end, the first drive signal input end is connected to the output end of the first drive trigger circuit, and the second drive signal input end is connected to the output end of the second drive trigger circuit, the first drive voltage input end And the second driving voltage input end is respectively connected to the output end of the boosting circuit. The computer power supply with output mode determination according to claim 16, wherein the first driving trigger circuit, the second driving trigger circuit and the first output voltage switching control circuit are connected to a second output. a voltage switching control circuit, the second output voltage switching control circuit has a first driving signal input terminal, a first driving voltage input terminal, a second driving signal input terminal, a second driving voltage input terminal, and a first load a first driving signal input end connected to the output end of the first driving trigger circuit, and a second driving signal input end connected to the output end of the second driving trigger circuit, the second output a first driving voltage input end of the voltage switching control circuit is connected to the first load connection end of the first output voltage switching control circuit, and a second driving voltage input end of the second output voltage switching control circuit is connected to the first output voltage Switching the second load connection of the control circuit. The computer power supply with output mode determination according to claim 16, wherein the first driving trigger circuit, the second driving trigger circuit, and the first The output voltage switching control circuit is connected to a third output voltage switching control circuit. The third output voltage switching control circuit has a first driving signal input end, a first driving voltage input end, a second driving signal input end, and a first output voltage switching control circuit. a driving voltage input end, a first load connecting end and a second load connecting end, wherein the first driving signal input end is connected to the output end of the first driving trigger circuit, and the second driving signal input end is connected to the second driving end An output end of the trigger circuit, the first driving voltage input end of the third output voltage switching control circuit is connected to the first load connection end of the first output voltage switching control circuit, and the second output voltage is switched to the second driving of the control circuit The voltage input terminal is coupled to the second load connection end of the first output voltage switching control circuit. The power supply for a computer having an output mode determination according to claim 17, wherein the clamp circuit, the standby power reference level, and the second output voltage switching control circuit are connected to generate a first power good signal. The circuit and a second power good signal generating circuit are connected. The first power good signal generating circuit has a first input end, a second input end, a third input end and an output end, and the first power good signal is generated. a first input end of the circuit is connected to the first output end of the clamp circuit, and a second input end of the first power good signal generating circuit is connected to the first load connection end of the second output voltage switching control circuit, the first a third input end of the power good signal generating circuit is connected to the standby power reference level, and an output of the first power good signal generating circuit outputs a first power good signal, and the second power good signal generating circuit has a a first input end, a second input end, a third input end, and an output end, the second power good signal generating circuit The second output terminal connected to the input terminal of a clamping circuit is connected to a second input terminal of the second power good signal generating circuit and a second load connection end of the second output voltage switching control circuit is connected, a third input end of the second power good signal generating circuit is connected to the standby power reference level, and an output end of the second power good signal generating circuit A second power good signal is output. The power supply for a computer having an output mode determination according to the first aspect of the invention, wherein the differential pressure amplifying circuit is connected to a selection switch having a first contact, a second contact, and a a common contact, the first contact is connected to the second input end of the differential pressure amplifying circuit, and the second contact is connected to the output end of the differential pressure amplifying circuit, the common contact and the differential pressure amplifying circuit The first input is connected.