TWM557448U - Semiconductor process equipment - Google Patents

Semiconductor process equipment Download PDF

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Publication number
TWM557448U
TWM557448U TW106216107U TW106216107U TWM557448U TW M557448 U TWM557448 U TW M557448U TW 106216107 U TW106216107 U TW 106216107U TW 106216107 U TW106216107 U TW 106216107U TW M557448 U TWM557448 U TW M557448U
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TW
Taiwan
Prior art keywords
semiconductor process
component
extension
elastomer
sidewall surface
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TW106216107U
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Chinese (zh)
Inventor
張祐語
黃俊堯
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麥豐密封科技股份有限公司
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Application filed by 麥豐密封科技股份有限公司 filed Critical 麥豐密封科技股份有限公司
Priority to TW106216107U priority Critical patent/TWM557448U/en
Publication of TWM557448U publication Critical patent/TWM557448U/en
Priority to DE202018106098.8U priority patent/DE202018106098U1/en
Priority to JP2018004178U priority patent/JP3219636U/en
Priority to FR1859962A priority patent/FR3073084B3/en
Priority to CN201821778556.3U priority patent/CN208938918U/en
Priority to KR2020180004871U priority patent/KR200493938Y1/en
Priority to FR1912926A priority patent/FR3091954B3/en

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Abstract

Semiconductor process equipment is provided, including an upper element, a lower element, an annular recess and an elastomer. The upper element is configured to hold a wafer, and has a first sidewall surface. The lower element is configured to hold the upper element, and has a second sidewall surface. The annular recess is between the lower element and the upper element, and adjacent to the first and second sidewall surfaces. The elastomer is disposed in the annular recess, and has a main body and a first extending portion connected to the main body. The first extending portion protrudes from the main body and the first sidewall surface, and extends along the first sidewall surface.

Description

半導體製程設備 Semiconductor process equipment

本創作是有關於一種半導體製程設備,特別是有關於一種具有彈性體的半導體製程設備。 The present invention relates to a semiconductor process device, and more particularly to a semiconductor process device having an elastomer.

在現今的半導體製程中,往往會對晶圓進行蝕刻製程以在半導體上形成電路圖案。電漿蝕刻為蝕刻製程的一種,其以高速的離子氣流射向晶圓以蝕刻晶圓表面,形成電路圖案。為了在電漿蝕刻製程中的高速離子氣流下保持晶圓的位置,目前多半使用靜電吸附承盤(electrostatic chuck;ESC),產生靜電力以固定晶圓的位置。然而,在蝕刻氣體的作用下,靜電吸附承盤亦可能受到蝕刻氣體侵蝕而損壞,影響製程良率。因此,需要一種較不易損壞的半導體製程設備,以克服前述問題。 In today's semiconductor processes, wafers are often etched to form circuit patterns on the semiconductor. Plasma etching is a type of etching process that directs a high-speed ion current to a wafer to etch the surface of the wafer to form a circuit pattern. In order to maintain the position of the wafer under the high-speed ion current in the plasma etching process, an electrostatic chuck (ESC) is often used to generate an electrostatic force to fix the position of the wafer. However, under the action of the etching gas, the electrostatic adsorption retainer may also be damaged by the etching gas, which affects the process yield. Therefore, there is a need for a semiconductor process equipment that is less susceptible to damage to overcome the aforementioned problems.

為解決前述習知問題,本創作之一實施例提供一種半導體製程設備,用以承載一晶圓,包含一上部元件、一下部元件、一環狀之凹口、以及一彈性體。上部元件是用以承載一晶圓且具有一第一側壁表面。下部元件是用以承載上部元件且具有一第二側壁表面。環狀之凹口是位於下部元件及上部元件之間,且鄰接該第一、第二側壁表面。 彈性體具有相互連接之本體以及第一延伸部,其中本體設置於凹口內,第一延伸部凸出於本體以及第一側壁表面,且沿第一側壁表面延伸。 In order to solve the aforementioned problems, an embodiment of the present invention provides a semiconductor processing apparatus for carrying a wafer including an upper component, a lower component, an annular recess, and an elastomer. The upper component is for carrying a wafer and has a first sidewall surface. The lower element is for carrying the upper element and has a second side wall surface. The annular recess is located between the lower member and the upper member and abuts the first and second side wall surfaces. The elastomer has a body connected to each other and a first extension, wherein the body is disposed in the recess, the first extension protruding from the body and the first sidewall surface and extending along the first sidewall surface.

於一實施例中,其中彈性體更具有第二延伸部,第二延伸部凸出於本體以及第二側壁表面,且沿第二側壁表面延伸。 In an embodiment, wherein the elastic body further has a second extension, the second extension protrudes from the body and the second sidewall surface and extends along the second sidewall surface.

於一實施例中,其中半導體製程設備更包括一連接層,位於上部元件及下部元件之間,用以連接上部元件及下部元件。 In one embodiment, the semiconductor process device further includes a connection layer between the upper component and the lower component for connecting the upper component and the lower component.

於一實施例中,其中半導體製程設備更具有一外側元件,環繞上部元件及下部元件,且對應於上部元件的第一側壁表面及下部元件的第二側壁表面設置,其中外側元件與第一延伸部之間相隔一距離。 In one embodiment, wherein the semiconductor processing device further has an outer member surrounding the upper member and the lower member, and corresponding to the first sidewall surface of the upper member and the second sidewall surface of the lower member, wherein the outer member and the first extension There is a distance between the parts.

於一實施例中,其中彈性體更具有一凸塊,抵接外側元件。 In an embodiment, the elastic body further has a protrusion that abuts the outer member.

於一實施例中,其中第一延伸部的頂面低於上部元件的頂面。 In an embodiment, wherein the top surface of the first extension is lower than the top surface of the upper component.

於一實施例中,其中第一延伸部於彈性體之一徑向方向上具有一寬度,且第一延伸部的寬度的範圍介於0.05mm~1.0mm之間。 In one embodiment, the first extension has a width in a radial direction of one of the elastic bodies, and the width of the first extension ranges between 0.05 mm and 1.0 mm.

於一實施例中,其中彈性體具有一斜面,斜面與下部元件的第二側壁表面之間夾有一角度,且角度為鈍角。 In one embodiment, wherein the elastomer has a bevel, the bevel is angled with the second sidewall surface of the lower member and the angle is an obtuse angle.

於一實施例中,其中彈性體更具有一階梯狀表 面,且階梯狀表面鄰接斜面。 In an embodiment, wherein the elastic body has a stepped table Face, and the stepped surface abuts the slope.

於一實施例中,其中彈性體更具有一導角面,形成於第一延伸部之一外緣,且導角面為斜角或圓角。 In an embodiment, the elastic body further has an angled surface formed on one of the outer edges of the first extension, and the angled surface is beveled or rounded.

於一實施例中,其中彈性體具有氟化橡膠(Fluoro-elastomer)、全氟化橡膠(Perfluoro-elastomer)或氟矽橡膠(Fluorosilicone)材質。 In one embodiment, the elastomer has a Fluoro-elastomer, a Perfluoro-elastomer or a Fluorosilicone material.

為讓本創作之上述和其他目的、特徵和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,做詳細說明如下。 The above and other objects, features and advantages of the present invention will become more apparent and understood.

1‧‧‧半導體製程設備 1‧‧‧Semiconductor process equipment

10‧‧‧上部元件 10‧‧‧Upper components

10A‧‧‧第一側壁表面 10A‧‧‧First side wall surface

10B‧‧‧頂面 10B‧‧‧ top surface

11‧‧‧電極 11‧‧‧Electrode

20‧‧‧下部元件 20‧‧‧lower components

20A‧‧‧第二側壁表面 20A‧‧‧Second side wall surface

22‧‧‧加熱單元 22‧‧‧heating unit

24‧‧‧冷卻系統 24‧‧‧Cooling system

241‧‧‧冷卻流體 241‧‧‧Cooling fluid

26‧‧‧流體供應系統 26‧‧‧Fluid Supply System

261‧‧‧流體 261‧‧‧ fluid

30‧‧‧連接層 30‧‧‧Connection layer

40‧‧‧環狀凹口 40‧‧‧ annular notch

45‧‧‧環氧樹脂 45‧‧‧Epoxy resin

50‧‧‧彈性體 50‧‧‧ Elastomers

51‧‧‧本體 51‧‧‧Ontology

52‧‧‧第一延伸部 52‧‧‧First Extension

52B‧‧‧頂面 52B‧‧‧ top surface

521‧‧‧導角面 521‧‧‧guide angle

53‧‧‧第二延伸部 53‧‧‧Second extension

54‧‧‧凸塊 54‧‧‧Bumps

55、57‧‧‧斜面 55, 57‧‧‧ slope

56‧‧‧階梯狀表面 56‧‧‧stepped surface

60‧‧‧晶圓 60‧‧‧ wafer

70‧‧‧外側元件 70‧‧‧Outer components

80‧‧‧蝕刻氣體 80‧‧‧etching gas

A、B‧‧‧區域 A, B‧‧‧ area

D‧‧‧距離 D‧‧‧Distance

θ‧‧‧角度 Θ‧‧‧ angle

W1‧‧‧第一寬度 W 1 ‧‧‧first width

W2‧‧‧第二寬度 W 2 ‧‧‧second width

第1圖顯示根據一比較例之半導體製程設備之剖視示意圖。 Fig. 1 is a cross-sectional view showing a semiconductor process apparatus according to a comparative example.

第2圖顯示第1圖中A區域之放大示意圖。 Fig. 2 is an enlarged schematic view showing the area A in Fig. 1.

第3A圖顯示根據本創作一實施例之半導體製程設備之剖視示意圖。 3A is a cross-sectional view showing a semiconductor process apparatus according to an embodiment of the present invention.

第3B圖顯示第3A圖中B區域之放大示意圖。 Fig. 3B is an enlarged schematic view showing a region B in Fig. 3A.

第4圖顯示根據本創作另一實施例之半導體製程設備之局部示意圖。 Figure 4 is a partial schematic view showing a semiconductor process apparatus according to another embodiment of the present invention.

第5圖顯示根據本創作另一實施例之半導體製程設備之局部示意圖。 Fig. 5 is a partial schematic view showing a semiconductor process apparatus according to another embodiment of the present creation.

第6圖顯示根據本創作另一實施例之半導體製程設備之局部示意圖。 Figure 6 is a partial schematic view showing a semiconductor process apparatus according to another embodiment of the present creation.

第7圖顯示根據本創作另一實施例之半導體製程設備之 局部示意圖。 Figure 7 shows a semiconductor process device according to another embodiment of the present creation Partial schematic.

第8圖顯示根據本創作另一實施例之半導體製程設備之局部示意圖。 Figure 8 is a partial schematic view showing a semiconductor process apparatus according to another embodiment of the present creation.

以下說明本創作實施例之半導體製程設備。然而,可輕易了解本創作實施例提供許多合適的創作概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法使用本創作,並非用以侷限本創作的範圍。 The semiconductor process equipment of the present embodiment will be described below. However, it will be readily appreciated that the present creative embodiment provides many suitable creative concepts and can be implemented in a wide variety of specific contexts. The specific embodiments disclosed are merely illustrative of the use of the present invention in a particular way, and are not intended to limit the scope of the present invention.

除非另外定義,在此使用的全部用語(包括技術及科學用語)具有與此篇揭露所屬之一般技藝者所通常理解的相同涵義。能理解的是這些用語,例如在通常使用的字典中定義的用語,應被解讀成具有一與相關技術及本揭露的背景或上下文一致的意思,而不應以一理想化或過度正式的方式解讀,除非在此特別定義。 Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning It will be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the context or context of the present disclosure, and should not be in an idealized or overly formal manner. Interpretation, unless specifically defined herein.

請參照第1圖,第1圖顯示根據一比較例之半導體製程設備之剖視示意圖。前述半導體製程設備其可用以承載一晶圓60以進行蝕刻或其他製程,其主要包含一上部元件10、一下部元件20及一外側元件70。如第1圖所示,下部元件20可承載上部元件10,且外側元件70設置於上部元件10與下部元件20的周圍。上部元件10與下部元件20之間則可設置一連接層30,用以連接上部元件10及下部元件20。一環狀凹口40形成於上部元件10與下部元件20的交界處。此外,在上部元件10內部設有一電極11,用以接收電 壓並作為電極,其中電極11包含一導電材料,例如銅、鎢。由於晶圓的蝕刻速率受到晶圓溫度的影響,可在下部元件20內部設置加熱單元22及冷卻系統24,用以控制下部元件20的溫度。加熱單元22例如可包含一電阻材料,透過電力供應加熱前述電阻材料,以對下部元件20提供熱能。在冷卻系統24中導入一冷卻流體241,用以冷卻下部元件20,藉由加熱單元22與冷卻系統24的配合,可穩定地控制下部元件20的溫度,使得下部元件20的溫度不會影響晶圓60的溫度,進而避免影響晶圓60的蝕刻速率。另可在下部元件20設置一流體供應系統26,用以將一流體261(如氦氣)通過連接層30及上部元件10而注入晶圓60的背面,藉此可轉移晶圓的熱能,進而調節晶圓的溫度並控制蝕刻速率。因此,可將一環氧樹脂45或可更換之O形環填入環狀凹口40中,以避免前述流體通過連接層30時由環狀凹口40漏出而造成汙染。 Please refer to FIG. 1. FIG. 1 is a cross-sectional view showing a semiconductor processing apparatus according to a comparative example. The semiconductor processing apparatus described above can be used to carry a wafer 60 for etching or other processes, and includes primarily an upper component 10, a lower component 20, and an outer component 70. As shown in FIG. 1, the lower member 20 can carry the upper member 10, and the outer member 70 can be disposed around the upper member 10 and the lower member 20. A connecting layer 30 may be disposed between the upper member 10 and the lower member 20 for connecting the upper member 10 and the lower member 20. An annular recess 40 is formed at the interface of the upper element 10 and the lower element 20. In addition, an electrode 11 is disposed inside the upper component 10 for receiving electricity. Pressed and acted as an electrode, wherein the electrode 11 comprises a conductive material such as copper or tungsten. Since the etch rate of the wafer is affected by the wafer temperature, a heating unit 22 and a cooling system 24 may be disposed inside the lower member 20 to control the temperature of the lower member 20. The heating unit 22 may, for example, comprise a resistive material that heats the aforementioned resistive material through a power supply to provide thermal energy to the lower element 20. A cooling fluid 241 is introduced into the cooling system 24 for cooling the lower member 20. By the cooperation of the heating unit 22 and the cooling system 24, the temperature of the lower member 20 can be stably controlled so that the temperature of the lower member 20 does not affect the crystal. The temperature of the circle 60, in turn, avoids affecting the etch rate of the wafer 60. A fluid supply system 26 can be disposed on the lower member 20 for injecting a fluid 261 (such as helium) into the back surface of the wafer 60 through the connection layer 30 and the upper member 10, thereby transferring the thermal energy of the wafer. Adjust the temperature of the wafer and control the etch rate. Therefore, an epoxy resin 45 or a replaceable O-ring can be filled into the annular recess 40 to prevent contamination of the fluid from leaking through the annular recess 40 as it passes through the connecting layer 30.

然而,請參照第2圖,第2圖顯示第1圖中A區域之放大示意圖。環氧樹脂45在蝕刻製程中往往會容易受到蝕刻氣體80的侵蝕而損耗,使得前述流體漏出。此外,如第2圖所示,蝕刻氣體80同時也有可能侵蝕上部元件10及下部元件20,使得位在上部元件10內部的電極11或下部元件20內部的結構暴露出來,而產生漏電或電壓異常的現象。 However, please refer to Fig. 2, which shows an enlarged schematic view of the area A in Fig. 1. The epoxy resin 45 tends to be easily damaged by the etching of the etching gas 80 during the etching process, so that the aforementioned fluid leaks out. Further, as shown in Fig. 2, the etching gas 80 may also erode the upper member 10 and the lower member 20 at the same time, so that the structure inside the electrode 11 or the lower member 20 located inside the upper member 10 is exposed, and leakage or voltage abnormality is generated. The phenomenon.

請參照第3A-3B圖,第3A圖顯示根據本創作一實施例之半導體製程設備1之剖視示意圖,其能解決上述比較例的問題。第3B圖顯示第3A圖中B區域之放大示意圖。 應先說明的是,在本實施例中,前述半導體製程設備1可用以承載晶圓60,例如可在蝕刻製程中用以承載晶圓60,並利用蝕刻氣體80對晶圓60進行乾式蝕刻或電漿蝕刻。 Please refer to FIG. 3A-3B. FIG. 3A is a cross-sectional view showing the semiconductor processing apparatus 1 according to an embodiment of the present invention, which can solve the problems of the above comparative example. Fig. 3B is an enlarged schematic view showing a region B in Fig. 3A. It should be noted that, in this embodiment, the semiconductor processing device 1 can be used to carry the wafer 60, for example, to carry the wafer 60 in an etching process, and dry etch the wafer 60 by using the etching gas 80 or Plasma etching.

如第3A圖所示,半導體製程設備1主要包含一上部元件10、一下部元件20、一連接層30、一環狀凹口40、一具彈性且可更換之彈性體50以及一外側元件70。此外,在第3A圖中的半導體製程設備1具有與第1圖相同之內部構造(即前述電極11、加熱單元22、冷卻系統24以及流體供應系統26),以下將不再贅述。 As shown in FIG. 3A, the semiconductor processing apparatus 1 mainly includes an upper component 10, a lower component 20, a connecting layer 30, an annular recess 40, an elastic and replaceable elastic body 50, and an outer component 70. . Further, the semiconductor processing apparatus 1 in Fig. 3A has the same internal configuration as that of Fig. 1 (i.e., the foregoing electrode 11, heating unit 22, cooling system 24, and fluid supply system 26), which will not be described below.

前述上部元件10是用以承載晶圓60且具有一頂面10B及一第一側壁表面10A,前述下部元件20位於上部元件10下方,用以承載上部元件10且具有一第二側壁表面20A。前述環狀凹口40形成在上部元件10及下部元件20的接合處,且鄰接第一、第二側壁表面10A、20A。此外,在上部元件10與下部元件20之間設有連接層30,用以連接上部元件10與下部元件20。 The upper component 10 is used to carry the wafer 60 and has a top surface 10B and a first sidewall surface 10A. The lower component 20 is located below the upper component 10 for carrying the upper component 10 and has a second sidewall surface 20A. The aforementioned annular recess 40 is formed at the junction of the upper member 10 and the lower member 20, and abuts the first and second side wall surfaces 10A, 20A. Furthermore, a connection layer 30 is provided between the upper element 10 and the lower element 20 for connecting the upper element 10 and the lower element 20.

如第3B圖所示,前述彈性體50具有一本體51及與本體51相互連接的一第一延伸部52。本體51可套設於環狀凹口40中,且其在彈性體50的徑向方向(X軸方向)上具有一第一寬度W1。此外,第一延伸部52凸出於本體50及環狀凹口40,且沿上部元件10的第一側壁表面10A而朝彈性體50的軸向方向(Y軸方向)延伸。另外,第一延伸部52於彈性體50的徑向方向(X軸方向)上具有一第二寬度W2,其範圍大致介於0.05mm~1.0mm之間,其中本體51的第一寬度W1大 於第一延伸部52的第二寬度W2。在本實施例中,彈性體50可具有氟化橡膠(Fluoro-elastomer)、全氟化橡膠(Perfluoro-elastomer)或氟矽橡膠(Fluorosilicone)材質,以提升對蝕刻氣體的抗腐蝕性。 As shown in FIG. 3B, the elastic body 50 has a body 51 and a first extension 52 connected to the body 51. The body 51 can be sleeved in the annular recess 40 and has a first width W 1 in the radial direction (X-axis direction) of the elastic body 50. Further, the first extension portion 52 protrudes from the body 50 and the annular recess 40, and extends along the first side wall surface 10A of the upper member 10 toward the axial direction (Y-axis direction) of the elastic body 50. In addition, the first extending portion 52 has a second width W 2 in the radial direction (X-axis direction) of the elastic body 50, and the range is substantially between 0.05 mm and 1.0 mm, wherein the first width W of the body 51 1 is greater than the second width W 2 of the first extension 52. In this embodiment, the elastomer 50 may have a Fluoro-elastomer, a Perfluoro-elastomer or a Fluorosilicone material to improve the corrosion resistance to the etching gas.

此外,如第3B圖所示,第一延伸部52具有一頂面52B,其中第一延伸部52的頂面52B係低於上部元件10的頂面10B。透過前述第一延伸部52與上部元件10的設置方式,可確保第一延伸部52的頂面52B不會與上部元件10所承載的晶圓60接觸,以避免影響晶圓60的定位。 Further, as shown in FIG. 3B, the first extension 52 has a top surface 52B in which the top surface 52B of the first extension 52 is lower than the top surface 10B of the upper member 10. Through the arrangement of the first extension portion 52 and the upper member 10, it can be ensured that the top surface 52B of the first extension portion 52 does not contact the wafer 60 carried by the upper member 10 to avoid affecting the positioning of the wafer 60.

應了解的是,由於本實施例之彈性體50可在受蝕刻氣體侵蝕而失效前進行定期更換,故可強化保護半導體製程設備以及提升製程良率的功效。另外,藉由自本體51向上延伸的第一延伸部52,更可保護上部元件10之第一側壁表面10A,以避免第一側壁表面10A因受到蝕刻氣體80侵蝕而暴露出上部元件10內部的電極11所導致的電弧放電(arcing)或漏電異常(leakage current failure)。 It should be understood that since the elastomer 50 of the present embodiment can be periodically replaced before being eroded by the etching gas, the effect of protecting the semiconductor process equipment and improving the process yield can be enhanced. In addition, the first side wall surface 10A of the upper member 10 is further protected by the first extending portion 52 extending upward from the body 51 to prevent the first side wall surface 10A from being exposed to the inside of the upper member 10 due to the etching of the etching gas 80. Arcing or leakage current failure caused by the electrode 11.

前述外側元件70設置於下部元件20的外側且環繞上部元件10及下部元件20。由第3B圖可以看出,外側元件70與上部元件10的第一側壁表面10A及下部元件20的第二側壁表面20A之間相隔一距離D,其範圍大致介於0.1至2.0mm之間。應注意的是,距離D可以大於第一延伸部52的第二寬度W2,使得外側元件70與第一延伸部52之間形成有一間隙。 The aforementioned outer member 70 is disposed outside the lower member 20 and surrounds the upper member 10 and the lower member 20. As can be seen from Fig. 3B, the outer member 70 is spaced from the first side wall surface 10A of the upper member 10 and the second side wall surface 20A of the lower member 20 by a distance D ranging between approximately 0.1 and 2.0 mm. It should be noted that the distance D may be greater than the second width W 2 of the first extension 52 such that a gap is formed between the outer element 70 and the first extension 52.

第4圖顯示根據本創作另一實施例之半導體製 程設備1之局部示意圖。本實施例與第3A-3B圖之實施例不同之處在於:彈性體50另具有與本體51相互連接的一第二延伸部53,第二延伸部53凸出於本體50及環狀凹口40,且沿下部元件20的第二側壁表面20A而朝彈性體50的軸向方向(Y軸方向)延伸。另外,第二延伸部53於彈性體50的徑向方向(X軸方向)上的寬度大致等於前述第一延伸部52之第二寬度W2。藉由自本體51向下延伸的第二延伸部53,更可同時保護下部元件20之第二側壁表面20A,以避免第二側壁表面20A因受到蝕刻氣體80侵蝕而暴露出下部元件20的內部結構所導致的電弧放電(arcing)或漏電異常(leakage current failure)。 Fig. 4 is a partial schematic view showing a semiconductor process apparatus 1 according to another embodiment of the present creation. The embodiment is different from the embodiment of FIG. 3A-3B in that the elastic body 50 further has a second extension portion 53 connected to the body 51. The second extension portion 53 protrudes from the body 50 and the annular recess. 40 and extending along the second side wall surface 20A of the lower member 20 toward the axial direction (Y-axis direction) of the elastic body 50. In addition, the width of the second extending portion 53 in the radial direction (X-axis direction) of the elastic body 50 is substantially equal to the second width W 2 of the first extending portion 52. The second side wall surface 20A of the lower member 20 can be simultaneously protected by the second extending portion 53 extending downward from the body 51 to prevent the second side wall surface 20A from being exposed by the etching gas 80 to expose the inside of the lower member 20. Arcing or leakage current failure caused by the structure.

第5圖顯示根據本創作另一實施例之半導體製程設備1之局部示意圖。本實施例與第4圖之實施例不同之處在於:第一延伸部52的外緣形成有一導角面521,藉此可將蝕刻氣體80更加順利地導入外側元件70與第一延伸部52及第二延伸部53之間的間隙。此外,導角面521可以是斜角或圓角。 Fig. 5 is a partial schematic view showing a semiconductor process apparatus 1 according to another embodiment of the present creation. The difference between the embodiment and the embodiment of FIG. 4 is that the outer edge of the first extending portion 52 is formed with a guiding surface 521, whereby the etching gas 80 can be more smoothly introduced into the outer member 70 and the first extending portion 52. And a gap between the second extensions 53. Further, the guide surface 521 may be beveled or rounded.

第6圖顯示根據本創作另一實施例之半導體製程設備1之局部示意圖。本實施例與第5圖之實施例不同之處在於:彈性體50更具有至少一凸塊54,形成於彈性體50的外側表面上,並抵接外側元件70對應於上部元件10及下部元件20的一側壁。透過前述凸塊54的設置,可固定彈性體50的位置,使其不會因蝕刻氣體的流動或是製程溫度的變化而產生位移,以避免彈性體50失去保護上部元件10或 下部元件20的作用。 Fig. 6 is a partial schematic view showing a semiconductor process apparatus 1 according to another embodiment of the present creation. The embodiment is different from the embodiment of FIG. 5 in that the elastic body 50 further has at least one protrusion 54 formed on the outer surface of the elastic body 50, and the abutting outer member 70 corresponds to the upper member 10 and the lower member. One side wall of 20. Through the arrangement of the aforementioned bumps 54, the position of the elastic body 50 can be fixed so as not to be displaced by the flow of the etching gas or the change of the process temperature, so as to prevent the elastic body 50 from losing the protection of the upper component 10 or The role of the lower element 20.

第7圖顯示根據本創作另一實施例之半導體製程設備1之局部示意圖。本實施例與第6圖之實施例不同之處在於:環狀凹口40具有一多邊形結構,對應於O型環50,其中彈性體50具有兩斜面55、57,斜面55與下部元件20的第二側壁表面20A之間夾有一角度θ,且角度θ為一鈍角,斜面57則鄰接上部元件10。此外,彈性體50另具有一L字形之階梯狀表面56,鄰接於斜面55及57。透過斜面55、57及階梯狀表面56的設置,彈性體50可向下部元件20的內部延伸,藉此可有助於在安裝彈性體50時順利地排除環狀凹口40內部的空氣,以保持彈性體50和下部元件20之間的密合。 Fig. 7 is a partial schematic view showing a semiconductor processing apparatus 1 according to another embodiment of the present creation. The embodiment is different from the embodiment of FIG. 6 in that the annular recess 40 has a polygonal structure corresponding to the O-ring 50, wherein the elastic body 50 has two inclined faces 55, 57, a slope 55 and a lower member 20. An angle θ is sandwiched between the second side wall surfaces 20A, and the angle θ is an obtuse angle, and the inclined surface 57 abuts the upper member 10. Further, the elastic body 50 further has an L-shaped stepped surface 56 adjacent to the inclined faces 55 and 57. The elastic body 50 can extend through the interior of the lower member 20 through the arrangement of the slopes 55, 57 and the stepped surface 56, thereby facilitating the smooth removal of air inside the annular recess 40 when the elastomer 50 is mounted. The adhesion between the elastomer 50 and the lower member 20 is maintained.

第8圖顯示根據本創作另一實施例之半導體製程設備1之局部示意圖。本實施例與第7圖之實施例不同之處在於:彈性體50的階梯狀表面56包含兩個L字形結構且抵接上部元件10,藉此可增加彈性體50與下部元件20的接觸面積,以強化彈性體50與下部元件20和上部元件10之間的固定效果。 Figure 8 is a partial schematic view showing a semiconductor processing apparatus 1 according to another embodiment of the present invention. This embodiment differs from the embodiment of Fig. 7 in that the stepped surface 56 of the elastomer 50 comprises two L-shaped structures and abuts the upper element 10, whereby the contact area of the elastomer 50 with the lower element 20 can be increased. To reinforce the fixing effect between the elastic body 50 and the lower member 20 and the upper member 10.

雖然本創作的實施例及其優點已揭露如上,但應該瞭解的是,任何所屬技術領域中具有通常知識者,在不脫離本創作之精神和範圍內,當可作更動、替代與潤飾。此外,本創作之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟,任何所屬技術領域中具有通常知識者可從本創作揭示內容中理解現行或未來所發展出的製程、機器、製造、物 質組成、裝置、方法及步驟,只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本創作使用。因此,本創作之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外,每一申請專利範圍構成個別的實施例,且本創作之保護範圍也包括各個申請專利範圍及實施例的組合。 Although the embodiments of the present invention and its advantages have been disclosed as above, it should be understood that those skilled in the art can make changes, substitutions and refinements without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the processes, machines, manufacturing, material compositions, devices, methods, and steps in the specific embodiments described in the specification, and any one of ordinary skill in the art may disclose the present disclosure. Understand current processes, machines, manufacturing, and materials developed in the future The composition, the device, the method and the steps can be used according to the present invention as long as they can perform the same function or obtain substantially the same result in the embodiments described herein. Therefore, the scope of protection of the present invention includes the above processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each patent application scope constitutes an individual embodiment, and the scope of protection of the present invention also includes the combination of each patent application scope and embodiment.

雖然本創作以前述數個較佳實施例揭露如上,然其並非用以限定本創作。本創作所屬技術領域中具有通常知識者,在不脫離本創作之精神和範圍內,當可做些許之更動與潤飾。因此本創作之保護範圍當視後附之申請專利範圍所界定者為準。此外,每個申請專利範圍建構成一獨立的實施例,且各種申請專利範圍及實施例之組合皆介於本創作之範圍內。 Although the present invention has been disclosed above in the foregoing several preferred embodiments, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field of the present invention can make some changes and refinements without departing from the spirit and scope of the present creation. Therefore, the scope of protection of this creation is subject to the definition of the scope of the patent application attached. In addition, each of the patent application scopes constitutes a separate embodiment, and the scope of the various patent applications and combinations of the embodiments are all within the scope of the present invention.

Claims (11)

一種半導體製程設備,用以承載一晶圓,包括:一上部元件,用以承載一晶圓且具有一第一側壁表面;一下部元件,用以承載該上部元件且具有一第二側壁表面;一環狀之凹口,位於該下部元件及該上部元件之間,且鄰接該第一、第二側壁表面;以及一彈性體,具有相互連接之一本體以及一第一延伸部,其中該本體設置於該凹口內,該第一延伸部凸出於該本體以及該第一側壁表面,且沿該第一側壁表面延伸。 A semiconductor processing device for carrying a wafer, comprising: an upper component for carrying a wafer and having a first sidewall surface; a lower component for carrying the upper component and having a second sidewall surface; An annular recess between the lower member and the upper member and adjacent to the first and second side wall surfaces; and an elastic body having a body connected to each other and a first extension, wherein the body The first extension protrudes from the body and the first sidewall surface and extends along the first sidewall surface. 如申請專利範圍第1項所述之半導體製程設備,其中該彈性體更具有一第二延伸部,該第二延伸部凸出於該本體以及該第二側壁表面,且沿該第二側壁表面延伸。 The semiconductor process device of claim 1, wherein the elastomer further has a second extension protruding from the body and the second sidewall surface and along the second sidewall surface extend. 如申請專利範圍第1項所述之半導體製程設備,其中該半導體製程設備更包括一連接層,位於該上部元件及該下部元件之間,用以連接該上部元件及該下部元件。 The semiconductor process device of claim 1, wherein the semiconductor process device further comprises a connection layer between the upper component and the lower component for connecting the upper component and the lower component. 如申請專利範圍第1項所述之半導體製程設備,其中該半導體製程設備更具有一外側元件,環繞該上部元件及該下部元件,且對應於該上部元件的該第一側壁表面及該下部元件的該第二側壁表面設置,其中該外側元件與該第一延伸部之間相隔一距離。 The semiconductor process device of claim 1, wherein the semiconductor process device further has an outer component surrounding the upper component and the lower component, and corresponding to the first sidewall surface and the lower component of the upper component The second side wall surface is disposed with the outer element spaced from the first extension by a distance. 如申請專利範圍第4項所述之半導體製程設備,其中該彈性體更具有一凸塊,抵接該外側元件。 The semiconductor process apparatus of claim 4, wherein the elastomer further has a bump that abuts the outer component. 如申請專利範圍第1至5項中任一項所述之半導體製程設 備,其中該第一延伸部的頂面低於該上部元件的頂面。 The semiconductor process set according to any one of claims 1 to 5 The top surface of the first extension is lower than the top surface of the upper component. 如申請專利範圍第1至5項所述之半導體製程設備,其中該第一延伸部於該彈性體之一徑向方向上具有一寬度,且該第一延伸部的該寬度的範圍介於0.05mm~1.0mm之間。 The semiconductor process apparatus of claim 1 to 5, wherein the first extension has a width in a radial direction of one of the elastic bodies, and the width of the first extension ranges from 0.05 Between mm~1.0mm. 如申請專利範圍第1至5項中任一項所述之半導體製程設備,其中該彈性體具有一斜面,該斜面與該下部元件的該第二側壁表面之間夾有一角度,且該角度為鈍角。 The semiconductor process apparatus according to any one of claims 1 to 5, wherein the elastic body has a slope, the slope is at an angle with the second side wall surface of the lower member, and the angle is Obtuse angle. 如申請專利範圍第8項所述之半導體製程設備,其中該彈性體更具有一階梯狀表面,且該階梯狀表面鄰接該斜面。 The semiconductor process apparatus of claim 8, wherein the elastomer further has a stepped surface, and the stepped surface abuts the slope. 如申請專利範圍第1至5項中任一項所述之半導體製程設備,其中該彈性體更具有一導角面,形成於該第一延伸部之一外緣,且該導角面為斜角或圓角。 The semiconductor processing apparatus according to any one of claims 1 to 5, wherein the elastic body further has an angled surface formed on an outer edge of the first extending portion, and the guiding surface is inclined Corner or rounded corners. 如申請專利範圍第1至5項所述之半導體製程設備,其中該彈性體具有氟化橡膠(Fluoro-elastomer)、全氟化橡膠(Perfluoro-elastomer)或氟矽橡膠(Fluorosilicone)材質。 The semiconductor process apparatus according to any one of claims 1 to 5, wherein the elastomer has a material of a Fluoro-elastomer, a Perfluoro-elastomer or a Fluorosilicone.
TW106216107U 2017-10-31 2017-10-31 Semiconductor process equipment TWM557448U (en)

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DE202018106098.8U DE202018106098U1 (en) 2017-10-31 2018-10-25 Semiconductor processing device
JP2018004178U JP3219636U (en) 2017-10-31 2018-10-26 Semiconductor processing equipment
FR1859962A FR3073084B3 (en) 2017-10-31 2018-10-26 SEMICONDUCTOR PROCESSING DEVICE
CN201821778556.3U CN208938918U (en) 2017-10-31 2018-10-26 Semiconductor processing equipment
KR2020180004871U KR200493938Y1 (en) 2017-10-31 2018-10-26 Semiconductor processing device
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