TWM524503U - Electronic device - Google Patents

Abstract

An electronic device comprising: a CPU; and a controller, for: when receiving a command of the CPU, determining whether a plurality of logical block addresses are randomly distributed and whether capacity of data which the logical block address correspond is less than a first specific value according to the command; determining that a plurality of physical addresses corresponding to the logical block addresses are in an acceleration region and accessing the data from the acceleration region when the logical block addresses are randomly distributed and the capacity of the data is less than the first specific value; and determining that the physical address are in an non-acceleration region, and accessing the data from the non-acceleration region when the logical block address are not randomly distributed or the capacity of the data is not less than the first specific value.

Description

Electronic device

The present invention relates to a hard disk access technology, and more particularly to an electronic device corresponding to a solid state hard disk (SSD) access technology.

Intel has proposed a revolutionary 3D XPoint memory that is much faster than NAND flash memory (even beyond DRAM) and will not have the limit of write erase times compared to NAND flash memory. The only fly in the ointment is that the yield of 3D XPoint memory and the amount of data that can be stored per unit area are still beyond the NAND flash memory. Moreover, the past computer architecture and operating system are based on the communication between the volatile memory and the central processing unit. The current architecture has to be modified to communicate with the central processing unit and non-volatile memory.

The new model believes that the best way to use this type of memory is to use the Cache of the solid state hard disk. If the solid state hard disk uses 3D XPoint memory as the Cache of the controller. The new model can even store commonly used data in 3D XPoint memory, because the access time of small data volume of NAND flash memory is still not comparable with 3D XPoint memory, so we can put random small data into 3D XPoint. Memory, as a result, the overall SSD access speed can be increased by a factor of seven (according to Intel's current claims).

When the new 3D XPoint memory is used as the Cache of the solid state hard disk, the data to be put into the 3D XPoint memory becomes a new problem. This new model can of course directly emulate the previous SSHD (the architecture accelerated by NAND flash memory for hard disk (HDD)), which is mainly based on the access frequency to determine which data is placed in the acceleration zone. However, this approach only ensures that frequently used data is accelerated, but some data systems may only be accessed once a day, and these data cannot be accelerated because they are accessed too slowly.

In view of this, the present invention proposes an electronic device using a new memory 3D XPoint, the electronic device having a time stamp, so that the electronic device can put random small data into the 3D XPoint new storage memory to make the solid state The hard disk keeps the recently accessed data in the acceleration zone for access, thereby increasing the access speed of these random small data several times.

The present invention provides an electronic device comprising: a central processing unit; and a controller for determining whether a plurality of logical block addresses are randomly distributed according to the instruction when receiving an instruction from the central processing unit And whether the capacity of the data corresponding to the logical block address is less than a first specific value; when the logical block address is randomly distributed and the capacity of the data is less than the first specific value, it is determined to correspond to the logic a plurality of physical addresses of the block address in an acceleration zone, wherein the data is accessed in the acceleration zone; and when the logical block address is not the random distribution or the capacity of the data is not less than the first The specific value is determined to be that the physical address corresponding to the logical block address is in a non-acceleration area, and the data is accessed in the non-acceleration area.

To enable the above and other objects, features, and advantages of the present invention It is more obvious and easy to understand. The preferred embodiments are described below, and the detailed description is as follows with the accompanying drawings:

100‧‧‧Electronic devices

102‧‧‧Central Processing Unit

104‧‧‧Advanced Host Controller Interface

106‧‧‧ Solid State Drive

108‧‧‧ Controller

110‧‧‧ memory

112‧‧‧ acceleration zone

114‧‧‧Non-acceleration zone

LBA1, LBA2, LBA3, LBA4, LBA7, LBA10, LBA23, LBA37, LBA49‧‧‧ logical block addresses

Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10‧‧‧ physical addresses

S10, S20, S30, S40‧‧‧ steps

Figure 1 shows the main architecture of one of the electronic devices of the present invention; Figure 2 shows the first correspondence table of logical block addresses and physical addresses; Figure 3A shows the logical block addresses and physical addresses. And a second correspondence table of time labels; FIG. 3B shows a second correspondence table of logical block addresses, physical addresses, and time tags; FIG. 3C shows logical block addresses, physical addresses, and times One of the labels is a second correspondence table; and FIG. 4 is a flow chart showing a method of operating the electronic device according to the present invention.

The methods of making and using the various embodiments of the present invention are discussed in detail below. It is to be noted, however, that many of the possible novel concepts provided by the present invention can be implemented in a variety of specific ranges. These specific examples are merely illustrative of the methods of manufacture and use of the present invention, but are not intended to limit the scope of the present invention.

FIG. 1 shows a main architectural diagram of an electronic device 100 of the present invention. As shown in FIG. 1, the electronic device 100 includes a central processing unit 102, an advanced host controller interface (AHCI) 104, and a solid state drive 106. The solid state drive 106 includes a controller 108, a memory 110, an acceleration zone 112, and a non-acceleration zone 114. The central processing unit 102 is one of the main devices of the electronic device 100 (for example, a computer), and the function mainly explains computer instructions and processing in the computer software. data. The central processing unit 102 is configured to transmit an instruction to the controller 108 via the advanced host controller interface 104.

The advanced host controller interface 104 is used to regulate the manner in which data or instructions are transferred between the central processing unit 102 and a storage device (eg, solid state drive 106). In an embodiment of the present invention, the advanced host controller interface 104 has the function of transmitting SATA commands from the central processing unit 102 to the controller 108. In another embodiment of the present invention, the advanced host controller interface 104 has the function of transmitting PCIe instructions from the central processing unit 102 to the controller 108. The controller 108 is configured to, when receiving an instruction from the central processing unit 102, determine whether a plurality of physical addresses corresponding to the plurality of logical block addresses in the instruction are in the acceleration area 112, and the details of the remaining related controllers 108 The action will be described later. The memory 110 is configured to store a first correspondence table and a second correspondence table. The details of the first correspondence table and the second correspondence table are described in FIG. 2 and FIG. In some embodiments of the present invention, the memory 110 may also be in the acceleration zone 112 or the non-acceleration zone 114, and the present invention is not limited thereto. In one embodiment of the present invention, the acceleration region 112 can be a 3D XPoint memory, and the non-acceleration region 114 can be a NAND flash memory. The present invention is not limited thereto.

Figure 2 shows a first correspondence table of logical block addresses and physical addresses. The first correspondence table is a logical block address and a physical address included in the non-acceleration area 114. As shown in Figure 2, each logical block address is connected to a physical address. In an embodiment of the present invention, the logical block address LBA1 corresponds to the physical address Y1, the logical block address LBA10 corresponds to the physical address Y2, and the logical block address LBA23 corresponds to the physical address Y3, the logical area The block address LBA37 corresponds to the physical address Y4, and the logical block address LBA49 corresponds to the physical address Y5.

Figure 3A shows a second correspondence table of logical block addresses, physical addresses, time stamps, current access times, and last access time. In an embodiment of the present invention, the logical block address LBA1 corresponds to the physical address Y6, the logical block address LBA10 corresponds to the physical address Y7, and the logical block address LBA23 corresponds to the physical address Y8, the logical area The block address LBA37 corresponds to the physical address Y9, the logical block address LBA49 corresponds to the physical address Y10, the time tag has a second specific value (for example: 10), and the current access time is 13:05, last time The access time is 13:00. The time difference between this access time and the last access time is an access interval. When the access interval is larger, the value of the time stamp is smaller. In one embodiment of the present invention, each time the data is accessed in the acceleration zone 112, both the current access time and the last access time are updated. For example, when the data is accessed in the acceleration zone 112 at 13:06, the access time is changed from 13:05 to 13:06, and the last access time is changed from 13:00 to 13:05. Controller 108 performs an operation on the value of the time stamp. In one embodiment of the present invention, when the physical address is in the acceleration zone 112, the controller 108 sets the value of the time stamp to a second specific value (eg, 10). In another embodiment of the present invention, as shown in FIG. 3B, when the data accessed in the acceleration zone 112 is not accessed every access interval (eg, 30 minutes), the controller 108 sets the time stamp. The value is decremented by one. For example, the last access time is 13:05, the current access time is 13:35, and the time interval between the last access time and the current access time is greater than or equal to 30 minutes, and the controller 108 sets the time stamp. The value is reduced to 9. In addition, when the value of the time stamp is zero, the data is moved from the acceleration zone 112 to the non-acceleration zone 114 for access. In another embodiment of the present invention, as shown in FIG. 3C, the data accessed in the acceleration zone 112 is not received in a plurality of access intervals (eg, 10*30 minutes=5 hours). access. For example, once the access time is after 18:05 (meaning that the time interval between the current access time and the last access time is greater than or equal to 10*30 minutes = 5 hours), the controller 108 will time. The value of the label is reduced to zero. As a result, the data is moved from the acceleration zone 112 to the non-acceleration zone 114 for access. That is to say, the correspondence between the logical block address and the physical address changes. It should be noted that in one embodiment of the present invention, if the data is accessed at any point in time within the plurality of access intervals, the controller 108 sets the value of the time stamp back to a second specific value (eg, 10). ).

Figure 4 is a flow chart showing one of the methods of operation of the electronic device 100 in accordance with the present invention. First, in step S10, when the controller 108 receives an instruction from the central processing unit 102, it is determined according to the above instruction whether the plurality of logical block addresses are randomly distributed and the capacity of the data corresponding to the logical block address is less than A first specific value. That is, the controller 108 can determine whether the data is accessed in the acceleration zone 112 or the non-acceleration zone 114 according to whether the content included in the instruction and the logical block address are randomly distributed. When the logical block address is not randomly distributed or the capacity of the data corresponding to the logical block address is not less than a first specific value, the process proceeds to step S20. In step S20, the controller 108 determines that the physical address corresponding to the logical block address is in the non-acceleration area 114, so the corresponding data is accessed in the non-acceleration area 114, and the logical block address and the physical bit are accessed. The address is mapped according to the first correspondence table (see Figure 2). In an embodiment of the present invention, whether the logical block address is a continuous distribution is used as a criterion for judging whether the logical block address is a random distribution. For example, logical block addresses are continuously distributed and are not randomly distributed. In an embodiment of the present invention, the plurality of logical block addresses LBA1, LBA2, LBA3, LBA4, and LBA5 belong to a continuous distribution. in In another embodiment of the present invention, the data corresponding to the logical block address has a capacity of 100 kb, and the first specific value is 64 kb. That is to say, the capacity of the data corresponding to the logical block address is not less than a first specific value. When the logical block address is randomly distributed and the capacity of the data corresponding to the logical block address is smaller than the first specific value, the process proceeds to step S30. In step S30, the controller 108 determines that the physical address corresponding to the logical block address is in the acceleration area 112, so the corresponding data is accessed in the acceleration area 112, and the logical block address, the physical address, The time stamp, the current access time, and the last access time are corresponding according to the second correspondence table (see Figures 3A-3C). In an embodiment of the present invention, the logical block locations LBA1, LBA2, LBA3, LBA4, and LBA7 do not belong to a continuous distribution (ie, randomly distributed), and the capacity of the data corresponding to the logical block address is 30 kb. A specific value is 64 kb. That is to say, the capacity of the data corresponding to the logical block address is smaller than the first specific value. Next, the process proceeds to step S40. In step S40, the controller 108 determines whether to return to the non-acceleration area 114 to access the data according to whether the value of the time stamp is zero. For example, if the data is not accessed during the access interval, the value of the time stamp will be decremented. When the value of the time stamp is decremented to zero, it returns to step S20. For example, if the data is not accessed during an access interval (eg, 30 minutes, 1 hour, or the like), the controller 108 decrements the value of the time stamp by one, and then passes the access interval (eg, 30). The data is not accessed within minutes, hours, and the like, and the controller 108 decrements the value of the time stamp by one, and so on. If the data is not accessed after a certain number of specific times, the value will drop to zero. It is worth noting that once the data is accessed, the value of the time stamp is returned to the second specific value. In one embodiment of the present invention, the second specific value is 10. If the value of the time stamp is not decremented to zero, then Proceed to step S30.

Therefore, the electronic device disclosed in the present invention and the application method thereof can make part of the data of the solid state hard disk access in the 3D XPoint memory (ie, the acceleration area 112), instead of all the data in the NAND flash memory ( That is, access is made in the non-acceleration area 114), so that the NAND flash memory can obtain more Over Provisioning, so that the NAND flash memory can more efficiently process the loss of the NAND flash memory. Work such as Wear Leveling, Garbage Collection, Bad Block Management, etc., can even use 3D XPoint memory to reduce the write amplification factor of SSDs, and make SSDs last longer. At the same time, the processing speed of the solid state hard disk in processing specific data is greatly improved.

Although the present invention has been described above in terms of several preferred embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the present invention. And the scope of protection of this new type is subject to the definition of the scope of the patent application.

100‧‧‧Electronic devices

102‧‧‧Central Processing Unit

104‧‧‧Advanced Host Controller Interface

106‧‧‧ Solid State Drive

108‧‧‧ Controller

110‧‧‧ memory

112‧‧‧ acceleration zone

114‧‧‧Non-acceleration zone

Claims (10)

An electronic device comprising: a central processing unit; and a controller for: determining, when the instruction from one of the central processing units is received, determining, according to the instruction, whether the plurality of logical block addresses are a random distribution and the logic Whether the capacity of the data corresponding to the block address is less than a first specific value; when the logical block address is randomly distributed and the capacity of the data is less than the first specific value, it is determined to correspond to the logical block bit The plurality of physical addresses of the address are in an acceleration zone, and the data is accessed in the acceleration zone; and when the logical block address is not the random distribution or the capacity of the data is not less than the first specific value, It is determined that the physical address corresponding to the logical block address is in a non-acceleration area, and the data is accessed in the non-acceleration area. The electronic device of claim 1, wherein the electronic device further comprises a memory for storing a first correspondence table and a second correspondence table. The electronic device of claim 2, wherein the first correspondence table includes the logical block address and the physical address in the non-acceleration area, and the second correspondence table is included in the foregoing The logical block address in the acceleration zone and the physical address, the second correspondence table further includes a time tag, and the time tag is generated according to a current access time and a last access time. The access interval is determined. The electronic device of claim 3, wherein the time stamp has a value, and when the physical address is in the acceleration zone, the controller sets the value to a second specific value. The electronic device of claim 4, wherein the controller accesses the data in the acceleration zone without accessing the access interval, and the controller decrements the second specific value by one. The electronic device of claim 4, wherein when the value is zero, the data is moved from the acceleration zone to the non-acceleration zone for access. The electronic device of claim 1, wherein the instruction is a SATA command. The electronic device of claim 1, wherein the instruction is a PCIe instruction. The electronic device of claim 1, wherein the acceleration zone is a 3D XPoint memory. The electronic device of claim 1, wherein the non-acceleration zone is a NAND flash memory.