TWM521775U - Video signal conversion apparatus - Google Patents

Abstract

A video signal conversion apparatus includes a receiver, a splitter, a scaling down circuit and a transmitter. The receiver is used to receive a first frame data; the splitter is used to split the first frame data into two parts; the scaling down circuit is used to scaling down the two parts of the first frame data, respectively, to generate two scaled down data, and the scaling down circuit transmits the two scaled down data to a memory; and the transmitter is used to read the two scaled down data from the memory to obtain a second frame data, and to transmit the second frame data to a display panel to be displayed thereon.

Description

Video signal conversion device

This creation is about video signal processing, especially a video signal conversion device.

Since the display panels currently using the V-By-One standard are large-sized panels, for example, display panels of 50 inches or more, there is a problem that the developer may cause insufficient indoor space and environmental inconvenience. In addition, because the office or factory may not be able to place many large-sized panels, it is impossible to allow multiple developers to test different products at the same time, thus reducing development efficiency.

Therefore, one of the purposes of the present invention is to provide a video signal conversion device that can convert the original high-resolution frame data into lower-resolution frame data for development testing on a small-sized panel to solve Prior art issues.

According to an embodiment of the present invention, a video signal conversion apparatus includes a receiver, a divider, a reduction circuit, and a transmitter, wherein the receiver is configured to receive a first frame data; the divider is configured to use the first The frame data is divided into two parts; the reduction circuit is configured to respectively reduce the size of the two parts of the first frame data to obtain two sets of reduced data respectively, and transmit the two sets of reduced data to one And the transmitter reads the two sets of reduced data from the memory and forms a second frame data, and the second frame data is transmitted to a display panel for display.

Please refer to FIG. 1 , which is a block diagram of a video signal conversion apparatus 100 according to an embodiment of the present invention. As shown in FIG. 1 , the video signal conversion apparatus 100 includes a receiver 110 , a divider 120 , and a reduction circuit . A transmitter 140, a controller 150, and a memory management unit 160, wherein the reduction circuit 130 includes a vertical reduction circuit 132 and a horizontal reduction circuit 134. In addition, the video signal conversion device 100 is coupled to a flash memory 102, a memory 104, and a display panel 106. In this embodiment, the video signal conversion device 100 converts display data conforming to the Ultra High Definition (UHD) and V-By-One standards into a full HD image resolution panel (full HD). a printed circuit board with display data of a Low-Voltage Differential Signaling (LVDS) standard, and a receiver 110, a divider 120, a vertical reduction circuit 132, a horizontal reduction circuit 134, a transmitter 140, a controller 150, and The memory management unit 160 is disposed on the printed circuit board, but the present invention is not limited thereto.

On the other hand, the flash memory 102 stores a plurality of setting parameters of the receiver 110, the divider 120, the vertical reduction circuit 132, the horizontal reduction circuit 134, and the transmitter 140, and the controller 150 reads the flash memory 102. The plurality of setting parameters control the operations of the receiver 110, the divider 120, the vertical reduction circuit 132, the horizontal reduction circuit 134, and the transmitter 140.

In the operation of the video signal conversion apparatus 100, first, the receiver 110 receives a first frame data Din conforming to the ultra-high resolution panel, and the resolution may be 3840*2160 or 4096*2160 (4K2K) or other. Any similar resolution; afterwards, the splitter 120 divides the first frame data into two parts with a resolution of 2K2K, that is, each part contains 1920*2160 or 2048*2160. Then, the reduction circuit 130 respectively reduces the size of the two portions of the first frame data to obtain two sets of reduced data with a resolution of 1K1K, respectively. In detail, the vertical reduction circuit 132 first reduces the first frame data separately. The vertical dimension of the two parts is to generate two sets of vertical size reduction data with a resolution of 2K1K, that is, the number of pixels included in each set of vertical size reduction is 1920*1080 or 2048*1080; Next, the horizontal reduction circuit 134 respectively reduces the horizontal size of the two sets of vertical size reduced data to generate two sets of reduced data with a resolution of 1K1K. In this embodiment, the vertical reduction circuit 132 and the horizontal reduction circuit 134 may use a pixel deletion/pixel capture method to achieve a size reduction operation, such as deleting odd rows/columns or even rows/columns, or two The pixels are combined into a single pixel to achieve the size reduction operation, or any other suitable size reduction operation.

Next, the horizontal reduction circuit 134 stores two sets of reduced data with a resolution of 1K1K into the memory 104, and the transmitter 140 then reads the two sets of reduced data to obtain a second frame data with a resolution of 2K1K ( That is, the number of pixels included is 1920*1080 or 2048*1080), and the second frame data is transmitted to the display panel 106 as an output signal Dout for display. In one embodiment of the present invention, the controller 150 controls the horizontal reduction circuit 134 to sequentially store the two sets of reduced data in the memory 104 through the memory management unit 160 to establish the second resolution of 2K1K. The frame data is read, and the transmitter 140 directly reads the second frame data stored in the memory 104 and transmits the data to the display panel 106 by using an LVDS signal. In another embodiment of the present invention, the memory 104 includes two independent memory spaces, and the controller 150 controls the horizontal reduction circuit 134 through the memory management unit 160 to simultaneously store the two sets of reduced data separately. Going into the two independent memory spaces in the memory 104, and the transmitter interleaves the data in the two independent memory spaces, and combines the read two sets of reduced data into the first After the two frame data, the LVDS signal is transmitted to the display panel 106 for display.

Please refer to FIG. 2, which is a block diagram of a video signal conversion apparatus 200 according to another embodiment of the present invention. As shown in FIG. 1, the video signal conversion apparatus 200 includes a receiver 110, a splitter 120, and a zoom out. The circuit 230, a transmitter 140, a controller 150, and a memory management unit 160, wherein the reduction circuit 230 includes a horizontal reduction circuit 232 and a vertical reduction circuit 234. In addition, the video signal conversion device 200 is coupled to a flash memory 102, a memory 104, and a display panel 106. In this embodiment, the video signal conversion device 200 converts display data conforming to the Ultra High Definition (UHD) and V-By-One standards into a full HD image resolution panel (full HD). Printed circuit board with display data for the Low-Voltage Differential Signaling (LVDS) standard. Since the difference between the video signal conversion device 200 and the video signal conversion device 100 shown in FIG. 1 is only in the order of execution of the horizontal reduction circuit 232 and the vertical reduction circuit 234, the operation is the same, so that those skilled in the art have After reading the above disclosure, the operation of the video signal conversion apparatus 200 should be easily understood, so the relevant details are not described herein.

Briefly summarizing this creation, the video signal conversion device provided in this creation can simply convert 4K2K data into 2K1K data and display it on a smaller display panel, so that multiple developers can be indoors at the same time. Develop products in a small space environment to improve development efficiency; on the other hand, the use of splitter, vertical reduction circuit and horizontal reduction circuit can reduce the operation burden of the wafer and reduce the design complexity; in addition, due to vertical/horizontal The reduction operation requires more complicated calculations. Therefore, the splitter is used to divide the frame and then perform vertical/horizontal reduction operations, which can further reduce the burden on the wafer operation and improve the work efficiency.

100, 200‧‧‧ video signal conversion device
102‧‧‧Flash memory
104‧‧‧ memory
106‧‧‧ display panel
110‧‧‧ Receiver
120‧‧‧ splitter
130, 230‧‧‧ Reduced circuit
132, 234‧‧‧ vertical reduction circuit
134, 232‧‧‧ horizontal reduction circuit
140‧‧‧transmitter
150‧‧‧ Controller
160‧‧‧Memory Management Unit

FIG. 1 is a block diagram of a video signal conversion apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram of a video signal conversion apparatus according to another embodiment of the present invention.

100‧‧‧Video signal conversion device

102‧‧‧Flash memory

104‧‧‧ memory

106‧‧‧ display panel

110‧‧‧ Receiver

120‧‧‧ splitter

130‧‧‧Reducing the circuit

132‧‧‧Vertical reduction circuit

134‧‧‧Horizontal reduction circuit

140‧‧‧transmitter

150‧‧‧ Controller

160‧‧‧Memory Management Unit

Claims (9)

A video signal conversion device includes: a receiver for receiving a first frame data; a divider for dividing the first frame data into two parts; and a reduction circuit for respectively reducing The two portions of the first frame data are sized to obtain two sets of reduced data, and the two sets of reduced data are transferred to a memory; and a transmitter is used to read from the memory The two sets of reduced data are combined to form a second frame data, and the second frame data is transmitted to a display panel for display. The video signal conversion device of claim 1, wherein the first frame data is display data conforming to the Ultra High Definition (UHD) and V-By-One standards, and the first The second frame data is displayed in accordance with the full HD resolution panel (full HD) and Low-Voltage Differential Signaling (LVDS) standards. The video signal conversion device of claim 1, wherein the reduction circuit comprises: a vertical reduction circuit for performing vertical size reduction operations on the two portions of the first frame data to generate Two sets of vertical size reduction data; and a horizontal reduction circuit for performing horizontal size reduction operations on the two sets of vertical size reduction data to generate the two sets of reduced data. The video signal conversion device of claim 1, wherein the reduction circuit comprises: a horizontal reduction circuit for separately performing horizontal size reduction operations on the two portions of the first frame data to generate The two sets of horizontally reduced data; and a vertical reduction circuit for performing vertical dimension reduction operations on the two sets of horizontally reduced data to generate the two sets of reduced data. The video signal conversion device of claim 1, wherein the reduction circuit simultaneously stores the two sets of reduced data into the memory. The video signal conversion device of claim 5, wherein the reduction circuit simultaneously stores the two sets of reduced data into two independent memory spaces in the memory. The video signal conversion device of claim 6, wherein the transmitter interleaves the two sets of reduced data stored in the two independent memory spaces, and combines the second data accordingly Frame information. The video signal conversion device of claim 1, wherein the reduction circuit sequentially stores the two sets of reduced data in the memory to create the second frame data, and the transmitter The second frame data stored in the memory is directly read. The video signal conversion device of claim 1, further comprising: a controller coupled to a flash memory, the divider, and the reduction circuit for reading the flash memory A plurality of setting parameters are used to control the operation of the divider and the reduction circuit.