TWM516284U - Signal extending system and receiver thereof - Google Patents

Abstract

A signal extending system is provided. The signal extending system includes a transmitter, a plurality of cables, and a receiver. The transmitter receives and converts an original digital image signal into a plurality of digital image signals. The cables respectively transmit the corresponding digital image signals from the transmitter. The receiver receives the digital image signals from the cables, wherein the receiver includes a plurality of frame buffers, a control logic, and a signal synthesizer. The frame buffers receive and capture the corresponding digital image signals, respectively, and output a plurality of activating signals after capturing. The control logic outputs an enable signal to the frame buffers according to the activating signals to activate the frame buffers output the corresponding digital image signals simultaneously. The signal synthesizer receives and combines the digital image signals from the frame buffers into the original digital image signal.

Description

Signal extension system and its receiving end

The present invention relates to a signal extension system, and more particularly to a signal extension system capable of signal extension and a receiving end thereof.

In recent years, with the continuous evolution of technology, multimedia audio and video technology has developed quite rapidly. For example, a high-definition multimedia interface (HDMI) capable of integrating sound and video transmission, because it transmits uncompressed audio signals and high-resolution video signals through the same cable, The analog signal is converted into a digital signal (A/D) or the digital signal is converted into an analog signal (D/A), so that the target of distortion-free output can be achieved.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional signal extension system. The signal extension system 10 includes an image source 12, an HDMI transmission line 13, a transmission end 14, a network route 15, a receiving end 16, an HDMI transmission line 17, and a display device 18. The image source 12 is, for example, a set-top box, a DVD player, a personal computer, a video game instrument, etc., and is used to output a Transition Minimized Differential Signaling (TMDS), such as the HDMI 1.4 version, which is also known as TMDS. It is a 3G HDMI signal. After the transmitting end 14 receives the TMDS from the image source 12 via the HDMI transmission line 13, the transmitting end 14 converts the TMDS into a network packet. The material is delivered to the receiving end 16 via a network route 15, such as a CAT-5 cable. Then, the receiving end 16 converts the network packet data into TMDS and transmits it to the display device 18 through the HDMI transmission line 17 for display.

However, the conventional signal extension system 10 can only support 3G HDMI signals, and if it is to transmit a 6G HDMI signal equivalent to twice the bandwidth of the 3G HDMI signal, it will not operate. In other words, if the 3G bandwidth component of the signal extension system 10 of FIG. 1 is used, the extension of the 6G HDMI signal will not be realized.

Therefore, for the purpose of the present invention, a signal extension system and a receiving end thereof are provided, and the extension of the 6G, 12G or 3G multiple signal can be realized by directly using the 3G bandwidth component.

Another object of the present invention is to provide a signal extension system and a receiving end thereof, which can reduce a single 6G, 12G or 3G multiple bandwidth signal into several 3G bandwidth signals and perform signal extension with the existing 3G bandwidth component, except In addition to ensuring that the quality of audio and video is not affected, there is no additional cost.

In accordance with the purpose of the present invention, in order to achieve these and other advantages, the present invention provides a signal extension system including a transmission end, a plurality of network routes, and a receiving end. The transmitting end receives the original digital video signal and parses the original digital video signal into a plurality of digital video signals. A plurality of network routes are connected to the transmitting end to respectively transmit digital video signals. The receiving end receives the digital image signal from the network route, wherein the receiving end includes a plurality of frame buffers, a control logic and a signal synthesizing unit. The plurality of frame buffers respectively receive and capture the digital image signals, and respectively output a plurality of trigger signals after the digital image signals are captured. The control logic outputs a enable signal to the frame buffer according to the trigger signal to drive the frame buffer to simultaneously input Digital image signal. The signal synthesizing unit receives the digital video signal from the frame buffer and synthesizes the digital video signal into the original digital video signal.

According to another object of the present invention, the present invention provides a receiving end comprising a plurality of frame buffers, a control logic and a signal synthesizing unit. The plurality of frame buffers respectively receive and capture a plurality of digital image signals transmitted through the plurality of network routes, and respectively output a plurality of trigger signals after the digital image signals are captured, wherein the digital image signals are from the original digital bits. The image signal is resolved. The control logic outputs a enable signal to the frame buffer according to the trigger signal to drive the frame buffer to simultaneously output the digital image signal. The signal synthesizing unit receives the digital video signal from the frame buffer and synthesizes the digital video signal into the original digital video signal.

Additional features and advantages of the invention will be set forth in the description which follows. Other objects and advantages of the present invention will be realized and attained by the description of the appended claims.

10, 100‧‧‧ Signal Extension System

12, 110‧‧ ‧ image source

13, 17, 115, 195‧‧‧ HDMI transmission line

14, 120‧‧‧ transmit end

15, 125a~125n‧‧‧ network route

16, 130‧‧‧ Receiver

18,200‧‧‧ display device

140a~140n‧‧‧ signal equalizer

150a~150n‧‧‧ Receive signal conversion interface

160a~160n‧‧‧ frame buffer

161‧‧‧Image capture unit

162‧‧‧Memory Control Unit

163‧‧‧ memory unit

164‧‧‧ Frame detection unit

165‧‧‧Sequence Control Unit

170a~170n‧‧‧Transmission signal conversion interface

180‧‧‧Control logic

190‧‧‧Signal synthesis unit

1 is a schematic diagram of a conventional signal extension system; FIG. 2 is a schematic diagram of a transmission end of the preferred embodiment of the present invention; FIG. 3 is a schematic diagram of a signal extension system of the preferred embodiment of the present invention; 4 is a schematic diagram showing a frame buffer of the preferred embodiment of the present invention.

Please refer to FIG. 2 and FIG. 3 simultaneously. FIG. 2 illustrates the transmission of the preferred embodiment of the present invention. The schematic diagram of the end, and FIG. 3 is a schematic diagram of the signal extension system of the preferred embodiment of the present invention. The signal extension system 100 of the present invention includes an image source 110, a transmitting end 120, a plurality of net routes 125a-125n, a receiving end 130, and a display device 200. The image source 110 is, for example, a set-top box, a DVD player, a personal computer, a video game instrument, etc., and is used to output a raw digital image signal DS, which is preferably a minimum transmission differential signal (TMDS) specified by the HDMI version 2.0, the above-mentioned TMDS. Also known as 6G HDMI signal.

Preferably, the transmitting end 120 receives the original digital video signal DS via the HDMI transmission line 115, and parses the original digital video signal DS into a plurality of digital video signals DS ₁ ~DS _n , and then transmits the corresponding digital network routes 125 a - 125 _n respectively. To the receiving end 130, wherein the network routes 125a-125n comprise Category 5 twisted pair (CAT-5) or Category 6 twisted pair (CAT-6).

Specifically, as shown in FIG. 2, the image source 110 provides the original digital image signal DS to the signal analysis unit 122 of the transmitting end 120, and the signal analyzing unit 122 parses the original digital image signal DS into a plurality of digital image signals DS ₁ ~ DS _{n is} correspondingly transmitted to a plurality of signal boosters 124a-124n. Signal 124a ~ 124n enhancer for enhancing the signal strength DS _{n 1} to the digital image signal DS, and then through the corresponding Ethernet cable 125a ~ 125n transmitted to the receiving terminal 130.

As shown in FIG. 3, the receiving end 130 includes a plurality of signal equalizers 140a-140n, a plurality of receiving signal conversion interfaces 150a-150n, a plurality of frame buffers 160a-160n, and a plurality of transmission signal conversion interfaces 170a-170n. Control logic 180 and signal synthesis unit 190. The signal equalizers 140a-140n are configured to respectively receive the plurality of digital image signals DS ₁ to DS _n from the transmitting end 120 via the network routes 125a to 125n, and perform signal compensation on the digital image signals DS ₁ to DS _n , wherein the digital signals are compensated. The image signals DS ₁ ~DS _n have a first image format and are preferably TMDS.

Receiving a signal conversion interface 150a ~ 150n for receiving corresponding signals 140a ~ 140n and compensated by the digital image signal DS ₁ ~ DS _n signal from the equalizer, and having a first video format (TMDS) of the digital image signal DS ₁ The ~DS _{n is} converted into a digital image signal DS ₁₁ ~DS _nn having a second image format, wherein the second image format is preferably a low voltage differential signal (LVDS) or a transistor transistor logic signal (TTL).

The frame buffers 160a-160n are configured to respectively receive and capture the digital image signals DS ₁₁ ~DS _nn , and respectively output a plurality of trigger signals AS ₁ ~AS _n after the digital image signals DS ₁₁ ~DS _nn are captured. To the input of control logic 180. In addition, the frame buffers 160a-160n also perform de-skew adjustment on the digital image signals DS ₁₁ ~DS _nn and eliminate signal delay effects. The detailed architecture and operation of the frame buffers 160a-160n will be As explained below.

Please refer to FIG. 4. FIG. 4 is a schematic diagram of a frame buffer of the preferred embodiment of the present invention. As shown in FIG. 4, in the embodiment, the frame buffer 160a is taken as an example. The frame structure of the other frame buffers 160b-160n is the same as that of the frame buffer 160a, and therefore will not be described again.

The frame buffer 160a preferably includes an image capturing unit 161, a memory control unit 162, a memory unit 163, a frame detecting unit 164, and a timing control unit 165. The image capturing unit 161 is configured to receive and capture the digital image signal DS ₁₁ and output the digital image signal DS ₁₁ to the memory control unit 162 after the digital image signal DS _{11 is} captured. When the memory control unit 162 receives the digital video signal DS ₁₁ , the digital video signal DS _{11 is} stored in the memory unit 163 and the control signal is output to the frame detecting unit 164. When the frame detecting unit 164 receives the control signal, it outputs the trigger signal AS ₁ to the control logic 180. When the frame detecting unit 164 receives the enable signal ES from the control logic 180, the enable signal ES is transmitted to the memory control unit 162 and the timing control unit 165, and then the memory control unit 162 controls the memory unit 163 to store. The digital video signal DS ₁₁ therein is output to the transmission signal conversion interface 170a via the timing control unit 165.

Next, please refer to FIG. 3 again, the control logic 180 according to a trigger signal AS ₁ ~ AS _n output enable signal ES to the inquiry frame buffers 160a ~ 160n, information to drive the frame buffer 160a ~ 160n simultaneously output digital image signal DS ₁₁ ~DS _nn . For example, in the embodiment, the control logic 180 is preferably a gate and has a plurality of input terminals and an output terminal. When the input terminals of the gates and the gates respectively receive the trigger signal AS ₁ ~ with a high level. At AS _n , the output of the gate will output the high level enable signal ES to the frame buffers 160a - 160n to drive the frame buffers 160a - 160n to simultaneously output the digital image signals DS ₁₁ ~ DS _nn .

The signal conversion interfaces 170a-170n are configured to respectively receive the digital image signals DS ₁₁ ~DS _nn having the second image format from the frame buffers 160a-160n, and convert the digital image signals DS ₁₁ ~DS _nn into the first Digital image signals DS ₁ ~ DS _{n in} an image format.

The signal synthesizing unit 190 is configured to receive the digital image signals DS ₁ to DS _n from the transmission signal conversion interfaces 170a to 170n, and combine the digital image signals DS ₁ to DS _n into the original digital image signal DS, and then preferably via HDMI. The transmission line 195 is output to the display device 200 for display.

It should be noted that the above-mentioned analysis of the original digital image signal into a specific number of digital image signals having a 3G HDMI signal is only an example, and is not limited thereto.

In the preferred embodiment of the present invention, if the original digital video signal is a 6G HDMI signal, the signal resolution unit 122 preferably parses the original digital video signal into two digital video signals having a 3G HDMI signal, and the resolution method is better. Preferably, but not limited to, the original image frame is decomposed into a left picture and a right picture (or split into an upper picture and a lower picture), and finally, the left picture and the right picture are combined into a original picture picture by the signal synthesizing unit 190, and then output.

In another preferred embodiment of the present invention, if the original digital video signal is 12G Preferably, the HDMI signal is parsed by the signal parsing unit 122 into four digital video signals having 3G HDMI signals, and the parsing method preferably includes, but is not limited to, decomposing the original image into an upper left picture and a lower left picture. The upper right picture and the lower right picture (or the single image picture is divided into four pictures in parallel or perpendicular direction), and finally the left upper picture, the lower left picture, the upper right picture and the lower right picture are synthesized into the original image by the signal synthesizing unit 190. Output after the screen.

In summary, the present invention can directly extend the 6G, 12G or 3G multiple signal by directly using the 3G bandwidth component. In other words, the present invention converts a single 6G, 12G or 3G multiple bandwidth signal into (or down to) a plurality of 3G bandwidth signals and performs signal extension with the existing 3G bandwidth component, and finally synthesizes the original digital image signal for display. In addition to ensuring that audio and video quality is not affected, there is no additional cost.

Those skilled in the art can make various modifications and variations to the remote server management method and related devices of the present invention without departing from the spirit and scope of the present invention. Therefore, various modifications and changes are intended to be included within the scope of the invention.

100‧‧‧Signal extension system

110‧‧‧Image source

115, 195‧‧‧ HDMI transmission line

120‧‧‧Transport

125a~125n‧‧‧ network route

130‧‧‧ Receiver

140a~140n‧‧‧ signal equalizer

150a~150n‧‧‧ Receive signal conversion interface

160a~160n‧‧‧ frame buffer

170a~170n‧‧‧Transmission signal conversion interface

180‧‧‧Control logic

190‧‧‧Signal synthesis unit

200‧‧‧ display device

Claims (17)

A signal extension system includes: a transmitting end, receiving an original digital video signal, and parsing the original digital video signal into a plurality of digital video signals; and a plurality of network routes connected to the transmitting end to respectively transmit the digital digits The image signal; and a receiving end receiving the digital image signals from the network routes, wherein the receiving end comprises: a plurality of frame buffers respectively corresponding to receiving and capturing the digital image signals, and after completion After the digital image signals are received, a plurality of trigger signals are respectively outputted; a control logic outputs a consistent energy signal to the frame buffers according to the trigger signals to drive the frame buffers to simultaneously output the digital image signals. And a signal synthesizing unit that receives the digital image signals from the frame buffers and synthesizes the digital video signals into the original digital video signals. The signal extension system of claim 1, wherein the transmission end comprises: a signal analysis unit for parsing the original digital image signal into the digital image signals; and a plurality of signal enhancers respectively corresponding to Receiving the digital image signals and enhancing Its signal strength. The signal extension system of claim 1, wherein the network routes comprise Category 5 twisted pair (CAT-5) or Category 6 twisted pair (CAT-6). The signal extension system of claim 1, wherein the receiving end further comprises: a plurality of signal equalizers for respectively receiving the digital image signals via the network routes, and for receiving the digital image signals The signal is signal compensated. The signal extension system of claim 4, wherein the digital image signals have a first image format, and the receiving end further comprises: a plurality of receiving signal conversion interfaces respectively corresponding to receiving the signals from the equalizers And modulating the digital image signals by the signal, and converting the digital image signals having the first image format into the digital image signals having a second image format. The signal extension system of claim 5, wherein the receiving end further comprises: a plurality of transmission signal conversion interfaces respectively corresponding to receiving the digital image images from the frame buffers and having the second image format And converting the digital image signals into the digital image signals having the first image format. The signal extension system of claim 5, wherein the first image format comprises a minimized transmission differential signal (TMDS), and the second image format comprises a low voltage differential signal (LVDS) or a transistor transistor. Logical signal (TTL). For example, the signal extension system described in claim 1 of the patent scope, wherein the frame buffering Each of the devices includes: an image capturing unit for receiving and capturing one of the digital image signals, and outputting the digital image signal after the digital image signal is captured; a memory control unit, when the memory When receiving the digital image signal from the image capturing unit, the body control unit stores the digital image signal in a memory unit and outputs a control signal; and a frame detecting unit configured to output the trigger according to the control signal a signal to the control logic; and a timing control unit connected to the memory control unit and the frame detecting unit for outputting the digital image signal according to the enable signal; wherein, when the memory control unit receives the signal When the signal is enabled, the digital video signal stored in the memory unit is controlled to be output via the timing control unit. The signal extension system of claim 1, wherein the control logic comprises a gate and a plurality of input terminals and an output terminal, and the input terminals of the gate and the gate respectively receive a high level The output of the gate outputs the enable signal to the frame buffers to drive the frame buffers to simultaneously output the digital image signals. A receiving end includes: a plurality of frame buffers respectively corresponding to receiving and capturing a plurality of digital image signals transmitted through the plurality of network routes, and correspondingly outputting a plurality of trigger signals after completing the capturing of the digital image signals , where the digital image signals are A control signal is generated by the control signal, and a control signal is outputted according to the trigger signals to the frame buffers to drive the frame buffers to simultaneously output the digital image signals; and a signal The synthesizing unit receives the digital image signals from the frame buffers and synthesizes the digital image signals into the original digital image signals. The receiving end according to claim 10, wherein the network routes comprise a Category 5 twisted pair (CAT-5) or a Category 6 twisted pair (CAT-6). The receiving end, as described in claim 10, further includes: a plurality of signal equalizers for respectively receiving the digital image signals via the network routes, and performing signal compensation on the digital image signals. The receiving end of claim 12, wherein the digital image signals have a first image format, and the receiving end further comprises: a plurality of receiving signal conversion interfaces, respectively corresponding to receiving the signals from the equalizers The digital image signals compensated by the signal are converted into the digital image signals having the second image format by the digital image signals having the first image format. The receiving end of claim 13, wherein the receiving end further comprises: a plurality of transmitting signal conversion interfaces respectively corresponding to receiving the digital image signals from the frame buffers and having the second image format And converting the digital image signals into the digital image signals having the first image format. The receiving end according to claim 13 of the patent application, wherein the first image format package A minimized transmission differential signal (TMDS) is included, and the second image format includes a low voltage differential signal (LVDS) or a transistor transistor logic signal (TTL). The receiving end of the claim 10, wherein the frame buffers each include: an image capturing unit for receiving and capturing one of the digital image signals, and And outputting the digital image signal after the digital image signal; when the memory control unit receives the digital image signal from the image capturing unit, the digital image signal is stored in a memory unit and outputs a a control unit for outputting the trigger signal to the control logic according to the control signal; and a timing control unit for connecting the memory control unit and the frame detection unit for The digital signal is outputted by the signal control unit; wherein when the memory control unit receives the enable signal, the memory unit controls the memory unit to output the digital image signal stored therein via the timing control unit. The receiving end according to claim 10, wherein the control logic comprises a gate and a plurality of input terminals and an output terminal, and the input terminals of the gates respectively receive the high level When the trigger signals are received, the output terminal of the gate outputs the enable signal to the frame buffers to drive the frame buffers to simultaneously output the digital image signals.