TWM516221U - Wafer level semiconductor package having multi-side encapsulation - Google Patents

Description

Wafer-level semiconductor package structure with multi-sided cladding

This creation is about bumped semiconductor package construction, especially for a multi-sided wafer-level semiconductor package structure that can be applied to wafer level wafer scale packages (WLCSP) and fans. Fan-Out Wafer Level Package (FOWLP).

Wafer-level packaging completes the semiconductor package at the wafer stage. Usually, the wafer-level packaging process includes a bump fabrication and packaging process, and then the wafer is diced to form a wafer-level package structure with a wafer body.

In the wafer cutting step, since the material of the wafer is relatively brittle, the stress generated by the cutting is likely to cause wafer collapse. Although it is known that a primer encapsulation layer is formed on the active surface of the wafer, although the active surface and the conductive bump can be protected, the side edges and corners of the active surface of the wafer cannot be effectively protected, so the active surface of the wafer main body The side edges and corners may also be chipped. In particular, the chipping of the active surface of the wafer may cause delamination of the wafer protective layer, which may result in failure of the wafer function, thereby affecting the wafer yield. In addition, the laterally exposed surface of the wafer body is also susceptible to damage by moisture intrusion. Therefore, the wafer dicing stress and the wafer delamination caused by the pressure of the package layer and the wafer protective layer of the active surface angle of the wafer must be solved in the current wafer level package structure.

In order to solve the above problems, the main purpose of the present invention is to provide a multi-sided wafer-level semiconductor package structure for solving the problem of wafer protective layer peeling at the active face angle ,, thereby improving the package product. Reliability.

The second objective of the present invention is to provide a multi-sided wafer level semiconductor package structure for enhancing the surface bonding force of a wafer level semiconductor package structure.

A further object of the present invention is to provide a multi-sided wafer-level semiconductor package structure for improving the warpage of the package structure and avoiding wafer chipping when the wafer is diced.

The purpose of this creation and solving its technical problems are achieved by the following technical solutions. The present invention discloses a multi-sided wafer-level semiconductor package structure comprising a wafer body, a plurality of bumps, a stamper layer, and a backing layer. The wafer main system has an active surface, a back surface, and a plurality of pads on the active surface. The pads are connected by a reconfigurable circuit layer, and the active surface is formed with a wafer protection layer covering the reconfigured circuit layer. The wafer protection layer has a plurality of retractions at the active surface corner Corner cutting edge. The bumps are disposed on the pads. The stamper layer is formed on the protective layer of the wafer and covers the indented corners, and the stamper layer partially seals the bumps. The adhesive layer is formed on the back surface.

The purpose of this creation and solving its technical problems can be further realized by the following technical measures.

In the wafer level semiconductor package construction described above, the bumps may have a plurality of laser cleaning surfaces exposed to the mold layer.

In the wafer level semiconductor package construction described above, the wafer protection layer may comprise a low dielectric constant material layer.

In the above wafer level semiconductor package structure, the indentation angles can be formed in a plurality of stamper storage tanks of the active surface corner of the wafer body.

In the foregoing wafer level semiconductor package construction, the depth of the stamper reservoirs may be between 30 and 50 microns.

In the foregoing wafer level semiconductor package structure, the depth of the stamper storage tanks may be less than the thickness of the wafer body such that the mold layer and the backing layer are not connected to each other.

In the foregoing wafer level semiconductor package structure, the back surface of the wafer body may be ground to interconnect the mold layer and the backing layer to the mold storage tanks.

In the foregoing wafer level semiconductor package structure, the opening shapes of the stamper storage tanks may be L-shaped.

In the foregoing wafer level semiconductor package structure, the opening shapes of the stamper storage tanks may be fan-shaped.

In the foregoing wafer level semiconductor package structure, the opening shapes of the stamper storage tanks may be in the shape of a mouth.

In the foregoing wafer level semiconductor package structure, the adhesive layer can be packaged Includes an insulating patch.

In the aforementioned wafer level semiconductor package construction, the stamper layer may have a roughened surface.

H1‧‧‧Deep mold storage tank depth

H2‧‧‧ thickness of the wafer body

10‧‧‧ wafer

11‧‧‧Cut Tape

12‧‧‧ Wafer retaining ring

20‧‧‧ Laser device

30‧‧‧Molding mould

31‧‧‧Molded plastic

40‧‧‧Rolling bar

41‧‧‧Fitting tape

42‧‧‧Tear film fixture

43‧‧‧UV irradiation device

50‧‧‧ polishing head

60‧‧‧Single cutting tool

70‧‧‧ appearance inspection device

80‧‧‧ pick and place device

90‧‧‧Test board

91‧‧‧Test socket

100‧‧‧ Wafer-level semiconductor package construction

110‧‧‧ wafer body

111‧‧‧Active surface

112‧‧‧Back

113‧‧‧ pads

114‧‧‧Reconfigure the circuit layer

115‧‧‧ Wafer Cover

116‧‧‧Infinity angle

117‧‧‧Compression molding tank

118‧‧‧Under bump metal layer

120‧‧‧Bumps

121‧‧‧Laser cleaning surface

130‧‧‧Molded adhesive layer

131‧‧‧ roughened surface

140‧‧ ‧ adhesive layer

200‧‧‧ Wafer-level semiconductor package construction

1 is a cross-sectional view of a multi-sided wafer-level semiconductor package structure taken along a diagonal diagonal of two opposite sides of a wafer active surface according to a first embodiment of the present invention.

2A to 2M are diagrams showing the steps in the process of the wafer level semiconductor package structure according to the first embodiment of the present invention.

3 to 8 are schematic cross-sectional views of respective elements in the main steps of the process of the wafer level semiconductor package structure according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view showing another multi-sided wafer-level semiconductor package structure along a diagonal diagonal line of the active surface of the wafer according to the second embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the illustrations are simplified schematic diagrams, and only the schematic diagram is used to illustrate the basic architecture or implementation method of the present invention. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. Number, shape and size of actual implementation The ratio is an optional design, and the detailed component layout may be more complicated.

In accordance with a first embodiment of the present invention, a multi-sided wafer-level semiconductor package structure 100 is illustrated in cross-section along the diagonal of the wafer active surface in FIG. The wafer level semiconductor package structure 100 includes a wafer body 110, a plurality of bumps 120, a stamper layer 130, and a backing layer 140.

The wafer body 110 has an active surface 111, a back surface 112, and a plurality of pads 113 on the active surface 111. The material of the wafer body 110 is a semiconductor such as a germanium or a III-V semiconductor compound. The active surface 111 is formed with various integrated circuit components and electrically connected to the pads 113. The pads 113 are connected to external terminals of the integrated circuit. The pads 113 are connected by a re-distribution circuit layer 114. The material of the re-distribution circuit layer 114 may be selected from the group consisting of copper, aluminum, tin/copper/gold or tin/copper/nickel/gold alloys. The pads 113 can be electrically connected to the integrated circuits in the wafer body 110 by the re-wiring circuit layer 114. Alternatively, the pads 113 may be connected to each other by the reconfiguration circuit layer 114, such as the connection of the external pad to the test pad, the connection of the same function external pad, and the connection of the empty pad external pad.

As shown in FIG. 1 , a wafer protective layer 115 is formed on the active surface 111 to cover the reconfigured wiring layer 114 . The wafer protection layer 115 may comprise a low dielectric constant material layer. The wafer protection layer 115 can be, for example, a composite insulating material layer of an oxide layer/nitride layer. Traditionally, the fab defines the pattern opening of the wafer protection layer 115 in advance to form an opening that exposes the pad 113. In particular, the wafer protection layer 115 has a plurality of indentation angles and cut edges 116 at the corners of the active surface 111 to solve the problem that the wafer protection layer is easily peeled off at the active surface angle ,, thereby improving Package Product reliability. Preferably, the indented corner cutting edges 116 are arcuate, and the stamping forming manner and the coating pattern of the stamping layer 130 are combined to reduce the peeling and delamination of the wafer protective layer 115. The probability of occurrence.

Moreover, the bumps 120 are disposed on the pads 113. More specifically, but not necessarily, an under bump metal layer 118 may be formed on the pads 113 to enhance the bonding between the bumps 120 and the pads 113. The bumps 120 can be formed by, for example, evaporation, plating, printing, jetting, or wire bonding. In this embodiment, the bumps 120 are tin-lead solder balls or lead-free type tin-silver solder balls, and the appearance thereof is spherical. However, the appearance of the bumps 120 may also be columnar, finger-shaped, tower-shaped, dome-shaped or irregular. The reason why the appearance of the bumps 120 is not limited is that the compression molding method of the stamper layer 130 only has a one-way molding pressure to the active surface 111 of the wafer, and there is no side that causes the stress of the bumps. To the mold flow pressure.

The stamping layer 130 is formed on the wafer protective layer 115 and covers the indented corners 116, and the stamping layer 130 partially seals the bumps 120. The thickness of the stamping layer 130 on the wafer protection layer 115 should be greater than the thickness of the wafer protection layer 115 and less than three-quarters of the height of the bumps 120, so that the bumps 120 are partially Exposed to the molding compound layer 130. Specifically, as shown in FIGS. 1 and 4, the indented corner cutting edges 116 may be formed in a plurality of stamper launders 117 of the wafer body 110 at the corners of the active surface 111. As for the single wafer body 110, the shape of the opening of the stamping reservoir 117 toward the active surface 111 may be a partial pattern, which may be used as a positioning identification point for the single-cutting, for example, L-shaped or nearly four. Branch The fan shape of a circle, wherein the die-shaped glue storage groove of the L-shaped opening shape has a larger glue accommodating space, and the die-shaped glue storage groove of the fan-shaped opening shape has the effect of being easy to be drilled; or, the die-filling glue storage tanks 117 The shape of the opening may be a mouth shape to surround the side of the active surface 111. The pressure molding adhesive layer 130 can have a material change elasticity, and the mold molding fluid layer 130 can contain more inorganic filler to thermally expand the compression molding rubber layer 130. The coefficient is reduced to match the thermal expansion coefficient of the wafer body 110. In addition, when an external pressure is applied to the uncured precursor of the molding compound layer 130, the uncured precursor of the molding compound layer 130 can disperse external stress into the compression molding reservoirs 117 to prevent When the extrudate is compressed, local damage is caused to the wafer main body 110 or the bumps 120 thereon to improve impact resistance, and peeling of the wafer protective layer 115 can be further prevented.

Preferably, the bumps 120 can have a plurality of laser cleaning surfaces 121 exposed on the molding compound layer 130 for removing the residual glue of the molding compound layer 130 on the exposed surfaces of the bumps 120. And facilitate subsequent bump bonding to enhance the surface bonding force of the wafer level semiconductor package construction. In addition, the stamping layer 130 can have a roughened surface 131 for enhancing the adhesion of the bottom adhesive or the corner adhesive when the wafer level semiconductor package structure 100 is surface bonded.

The adhesive layer 140 is formed on the back surface 112. The material of the adhesive layer 140 can have high temperature resistance characteristics to avoid aging or embrittlement due to high temperature treatment in subsequent processes. Preferably, in order to provide a good thermal conductivity of the wafer body 110, the adhesive layer 140 can have heat dissipation characteristics, so that part of the thermal energy generated by the wafer body 110 during operation can be conducted to the via adhesive layer 140. outer boundary. Since the back surface 112 of the wafer main body 110 does not have a bump structure, the method for forming the backing layer 140 is not limited, and may be formed by tape attaching, transfer molding, and printing. Formed by spin coating or the like.

Therefore, the inner corners 116 are formed in the stamper 117 around the active surface 111 of the wafer main body 110, so that the mold layer 130 covers the wafer protective layer. In the corner of 115, the peeling and delamination of the wafer protection layer 115 can be prevented, and the wafer body 110 can be prevented from being damaged by external impact, so that the internal circuit of the wafer body 110 will not be affected by the collision and the original loss will be lost. Some features. In particular, when the shape of the opening of the stamper laminating tank 117 is a ring-shaped groove, the stamping layer 130 covers the side of the wafer-level semiconductor package structure 100, thereby preventing leakage current on the crystal side and enhancing moisture resistance. .

According to the first embodiment of the present invention, FIGS. 2A to 2M further illustrate schematic diagrams of steps in the process of the wafer level semiconductor package structure 100. 3 to 8 are schematic cross-sectional views of respective components in the main steps of the process of the wafer level semiconductor package structure 100.

First, as shown in Figs. 2A and 3, a wafer 10 is placed in a wafer holding ring 12 and fixed by a dicing tape 11. The dicing tape 11 can be a blue film or a light-sensitive adhesive tape, and the main function is to fix the wafer body so as not to be scattered when the wafer is diced. As shown in FIGS. 1 and 2A, the wafer 10 includes a plurality of the wafer bodies 110 described above, and the wafers 10 have a plurality of longitudinal and lateral dicing streets for defining the wafer bodies 110.

Thereafter, as shown in FIGS. 1, 2A and 4, the stamper reservoirs 117 are formed on the wafer 10 by a laser device 20. In the wafer grooving step, the wafer bodies 110 of the wafer 10 are integrally connected. The forming positions of the stamping lamination grooves 117 are aligned on the cutting path, may be formed at the intersection of the longitudinal and lateral cutting streets, or may be formed on the cutting path. As shown in FIGS. 1 and 4, in the present embodiment, the depth of the stamper storage tanks 117 may be between 30 and 50 microns. The depth H1 of the stamper 117 may be less than the thickness H2 of the wafer body 110 such that the stamper layer 130 and the backing layer 140 are not connected to each other. In this step, the shape of the compression molding tank 117 facing the active surface 111 may be a cross shape. However, in other embodiments, the shape of the openings of the stamper 117 may be circular or square. And in the same grooving step, the wafer protection layer 115 has a plurality of indentation angles and cutting edges 116 at the corners of the active surface 111, and the indentation angles and the cutting edges 116 are formed in the mold storages. Inside the glue tank 117.

Thereafter, as shown in FIGS. 1, 2B and 5, the above-mentioned stamper layer 130 is formed on the active surface 111 of the wafer 10. The stamper 31 can be formed on the active surface 111 of the wafer 10 by a stamper die 30, and the amount of the stamper plastic 31 can be controlled by the amount, the melting temperature and the time, and the appropriate temperature rise condition and pressure can be applied. Under pressure, the molded plastic 31 is melted in the stamper mold 30, and after being cooled, it can be taken out. The stamper layer 130 is formed after the molding compound 31 is cured. The stamping layer 130 is formed on the wafer protective layer 115 and covers the indented corners 116, and the stamping layer 130 partially seals the bumps 120. The number of the molding compounds 31 can be controlled such that the height of the molding compound layer 130 after the molding is not higher than the height of the bumps 120, so that the The upper end of the bumps 120 protrudes from the stamping layer 130. The stamping layer 130 has a good protective effect on the bonding interface between the bumps 120 and the wafer 10. The molding compound layer 130 is a pressure mode epoxy molding compound.

Then, as shown in FIG. 2C, a bonding tape 41 is pressure-bonded on the molding compound layer 130, and is flattened by a rolling bar 40, so that the bonding tape 41 is closely adhered to the molding compound. On layer 130. After that, as shown in FIG. 2D, the back surface 112 of the wafer 10 is polished by a polishing head 50 to thin the thickness of the wafer 10 to form a wafer state as shown in FIG. Thereafter, as shown in Fig. 2E, the bonding tape 41 is removed by a tear film jig 42 to be separated.

Thereafter, as shown in FIGS. 2F and 6, the adhesive layer 140 is formed on the back surface 112 of the wafer 10, and can be formed by a film bonding method. The adhesive layer 140 can comprise an insulating patch.

Thereafter, as shown in FIG. 2G, the wafer 10 is again placed on the wafer holding ring 12 with the active side facing up, and fixed by the dicing tape 11. Preferably, as shown in FIGS. 2H and 7, a laser cleaning surface 121 may be formed on the protruding surface of the bumps 120 by a laser device 20, and more preferably formed on the stamping layer 130. A roughened surface 131, so that the laser cleaning surface 121 and the roughened surface 131 of the molding compound layer 130 can be formed in the same step to save the process.

Thereafter, as shown in FIGS. 2I and 8, the wafer is cut through a single dicing cutter 60 to be separated into a plurality of wafer level semiconductor package structures 100 including the wafer body 110. Since the warpage is easily generated after the wafer is thinned, the formation of the stamper layer 130 and the backing layer 140 can be used to improve the warpage of the wafer level semiconductor package structure 100. The curve can also avoid wafer fragmentation when the wafer is diced.

Thereafter, as shown in FIG. 2J, the wafer level semiconductor package structure 100 can be automatically optically inspected by an appearance inspection device 70, and the laser cleaning surface 121 of the protrusion surface of the bumps 120 is bright. The metal surface is judged to be good or bad to find the defective product (NG).

Thereafter, as shown in FIG. 2K, light irradiation is performed by a UV irradiation device 43 to reduce or lose the viscosity of the dicing tape 11, and as shown in FIG. 2L, the wafer level is easily used by a pick-and-place device 80. The semiconductor package structure 100 is picked up from the wafer retaining ring 12. Thereafter, as shown in FIG. 2M, the wafer level semiconductor package structures 100 are mounted one by one on a test socket 91 of a test board 90 for electrical testing.

In accordance with a second embodiment of the present invention, another multi-sided wafer-level semiconductor package structure 200 is illustrated in cross-section along the diagonal of the wafer active surface in FIG. The components of the second embodiment that have the same names and functions as those of the first embodiment will be denoted by the same reference numerals, and the detailed description thereof will not be repeated. The wafer level semiconductor package structure 200 includes a wafer body 110, a plurality of bumps 120, a stamper layer 130, and a backing layer 140.

The wafer body 110 has an active surface 111, a back surface 112, and a plurality of pads 113 on the active surface 111. The pads 113 are connected by a re-distribution circuit layer 114. The active surface 111 is formed with a wafer protection layer 115 to cover the reconfiguration circuit layer 114. The wafer protection layer 115 is at the corner of the active surface 111. The system has a plurality of indented angles 隅 cutting edges 116. The bumps 120 are disposed on the pads 113. The molding compound layer 130 is formed on the wafer protection layer 115 and covers the indentations The corner cutting edge 116, and the molding compound layer 130 partially seals the bumps 120. The adhesive layer 140 is formed on the back surface 112.

In this embodiment, the back surface 112 of the wafer body 110 can be ground to connect the mold layer 130 and the backing layer 140 to the stamper 117, so that the wafer body 110 The upper edge to the lower edge of the corner are collectively covered by the molding compound layer 130 and the adhesive layer 140. In an embodiment, when the side surface of the wafer body 110 is also covered by the mold layer 130, leakage current on the side of the wafer-level semiconductor package structure 200 can be prevented and the moisture resistance of the side can be enhanced. Further, the side of the wafer body 110 can be reduced from damage.

In addition, the molding compound layer 130 formed on the active surface 111 of the wafer body 110 can provide better electrical isolation between the bumps 120. By covering the corners of the stamping layer 130 and the backing layer 140, the wafer body 110 can obtain a corner film sealing, which solves the problem that the wafer is peeled off at the active surface angle ,, thereby improving The reliability of the packaged product. Preferably, the surface of the bumps 120 protruding from the stamping layer 130 may be a laser cleaning surface 121 exposed on the stamping layer 130. The stamper layer 130 can have a roughened surface 131.

The above disclosure is only the preferred embodiment of the present invention, and it is of course not possible to limit the scope of the present invention. Therefore, equivalent changes made in accordance with the present invention are still within the scope of the present invention.

H1‧‧‧Deep mold storage tank depth

H2‧‧‧ thickness of the wafer body

100‧‧‧ Wafer-level semiconductor package construction

110‧‧‧ wafer body

111‧‧‧Active surface

112‧‧‧Back

113‧‧‧ pads

114‧‧‧Reconfigure the circuit layer

115‧‧‧ Wafer Cover

116‧‧‧Infinity angle

117‧‧‧Compression molding tank

118‧‧‧Under bump metal layer

120‧‧‧Bumps

121‧‧‧Laser cleaning surface

130‧‧‧Molded adhesive layer

131‧‧‧ roughened surface

140‧‧ ‧ adhesive layer

Claims (12)

A multi-sided wafer-level semiconductor package structure comprising: a wafer body having an active surface, a back surface, and a plurality of pads on the active surface, the pads being connected by a reconfigurable circuit layer a protective layer of the wafer is formed on the active surface to cover the reconfigured wiring layer. The protective layer of the wafer has a plurality of indented corners at the active surface corner; a plurality of bumps Provided on the pads; a mold layer is formed on the protective layer of the wafer and covers the inner corners, and the mold layer partially seals the bumps; A backing layer is formed on the back surface. The multi-sided coated wafer level semiconductor package structure of claim 1, wherein the bumps have a plurality of laser cleaning surfaces exposed to the mold layer. The multi-sided coated wafer level semiconductor package structure of claim 1, wherein the wafer protection layer comprises a low dielectric constant material layer. The multi-sided coated wafer-level semiconductor package structure of claim 1, wherein the indentation angles are formed in a plurality of stamper storages of the active surface corner of the wafer body. Inside the slot. The multi-sided coated wafer level semiconductor package structure of claim 4, wherein the stamper storage tanks have a depth of between 30 and 50 microns. The multi-sided wafer-level semiconductor package structure of claim 4, wherein the depth of the stamper is smaller than the thickness of the wafer body, so that the mold layer is The adhesive layers are not connected to each other. The multi-sided coated wafer-level semiconductor package structure of claim 4, wherein the back surface of the wafer body is ground to interconnect the mold layer and the adhesive layer. Some die storage tanks. The wafer-level semiconductor package structure of the multi-sided cladding according to claim 4 or 5, wherein the shape of the openings of the stamper storage tanks is L-shaped. The multi-sided wafer-level semiconductor package structure of claim 4, wherein the opening shape of the stamper storage tanks is a fan shape. The multi-sided coated wafer level semiconductor package structure of claim 4, wherein the opening shape of the stamper storage tanks is a mouth shape. The multi-sided coated wafer level semiconductor package structure of any one of claims 1 to 5, wherein the adhesive layer comprises an insulating patch. The multi-sided coated wafer level semiconductor package structure according to any one of claims 1 to 5, wherein the stamper layer has a roughened surface.