TWM494965U - Electronic device - Google Patents
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- TWM494965U TWM494965U TW103201708U TW103201708U TWM494965U TW M494965 U TWM494965 U TW M494965U TW 103201708 U TW103201708 U TW 103201708U TW 103201708 U TW103201708 U TW 103201708U TW M494965 U TWM494965 U TW M494965U
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本新型創作是有關於一種電子裝置，且特別是有關於一種包含導電網格構件的電子裝置。The present invention relates to an electronic device, and more particularly to an electronic device including a conductive mesh member.
透明導電氧化物(transparent conducting oxide，TCO)薄膜因具有導電性以及在可見光範圍內的高透明度等特性，被廣泛應用於各種光電產品，例如：平面顯示器、太陽能電池、光電晶體、接觸感應面板(Touch Panel)、發光元件、有機發光平面顯示面板、電漿顯示面板(PDP Panel)、汽車防熱除霧玻璃、光電轉換器、透明加熱器、防靜電膜、紅外線反射裝置、建築用功能性玻璃等。Transparent conductive oxide (TCO) thin films are widely used in various optoelectronic products due to their electrical conductivity and high transparency in the visible range, such as flat panel displays, solar cells, photovoltaic crystals, and contact sensing panels. Touch Panel), light-emitting elements, organic light-emitting flat display panels, plasma display panels (PDP Panel), automotive heat-resistant defogging glass, photoelectric converters, transparent heaters, antistatic films, infrared reflectors, functional glass for construction, etc. .
然而，透明導電氧化物在導電性上仍舊無法與金屬材料相比，因此近年來已有其他技術被提出來，以達到良好導電性以及高透明度的需求，例如金屬網格。利用金屬網格層取代導電氧化物層可以達到理想的導電特性，且金屬網格層具有許多個開口來實現高透明度需求。不過，金屬網格本體的遮光性質往往導致在實際應用上的困難。舉例來說，在顯示面板上方以金屬網格層製作構件(例如屏蔽層、觸控元件或是其他)時，顯示面板中每個畫 素被金屬網格本體遮蔽的面積不一致，這將導致畫素顯示亮度被削減的程度不一致而發生顯示品質不良的現象。另外，從製作方式來看，金屬網格層往往先被製作於獨立的基材上而後再將此獨立基材與顯示面板貼合以配置於顯示面板上。因此，要以金屬網格層取代導電氧化物薄膜仍需要克服一些問題。However, transparent conductive oxides are still inferior in electrical conductivity to metallic materials, so other techniques have been proposed in recent years to achieve good electrical conductivity and high transparency requirements, such as metal meshes. The use of a metal mesh layer in place of the conductive oxide layer achieves the desired conductive properties, and the metal mesh layer has a number of openings to achieve high transparency requirements. However, the shading nature of the metal mesh body often leads to difficulties in practical applications. For example, when a component (such as a shielding layer, a touch element, or the like) is fabricated with a metal mesh layer above the display panel, each drawing in the display panel The area covered by the metal mesh body is inconsistent, which results in a phenomenon in which the brightness of the pixel display is inconsistent and the display quality is poor. In addition, from the perspective of the manufacturing method, the metal mesh layer is often fabricated on a separate substrate and then the independent substrate is bonded to the display panel to be disposed on the display panel. Therefore, there is still a need to overcome some problems in order to replace the conductive oxide film with a metal mesh layer.
本新型創作提供一種電子裝置，在畫素陣列結構上配置導電網格構件而仍具有理想的顯示效果。The novel creation provides an electronic device in which a conductive mesh member is disposed on a pixel array structure and still has an ideal display effect.
本新型創作一實施例的一種電子裝置，包括一導電網格構件與一畫素陣列結構。導電網格構件包括依據多個預定面積區而排列的多個多邊形圖案。預定面積區在一第一方向上規律排列而具有一第一間距，在一第二方向上規律排列而具有一第二間距，且第一方向與第二方向相交一交角。導電網格構件配置於畫素陣列結構上方。畫素陣列結構包括排列成一陣列的多個畫素開口區而任相鄰兩個畫素開口區之間有一非開口區，且第一間距為n個畫素開口區以及(n-1)個非開口區在一列方向上的總寬度，而第二間距為m個畫素開口區以及(m-1)個非開口區在一行方向上的總寬度，其中n與m為正整數。An electronic device according to an embodiment of the present invention comprises a conductive mesh member and a pixel array structure. The conductive mesh member includes a plurality of polygonal patterns arranged in accordance with a plurality of predetermined area regions. The predetermined area regions are regularly arranged in a first direction to have a first pitch, regularly arranged in a second direction to have a second pitch, and the first direction intersects the second direction at an angle of intersection. The conductive mesh member is disposed above the pixel array structure. The pixel array structure includes a plurality of pixel opening regions arranged in an array and a non-opening region between adjacent two pixel opening regions, and the first spacing is n pixel opening regions and (n-1) non-openings The total width of the regions in one column direction, and the second pitch is the total width of m pixel open regions and (m-1) non-open regions in one row direction, where n and m are positive integers.
在本新型創作一實施例中，上述多邊形圖案彼此連接而構成多個節點，這些節點有至少部分位於預定面積區之間的邊界上。In an embodiment of the present invention, the polygonal patterns are connected to each other to form a plurality of nodes, and the nodes have at least partially located on a boundary between the predetermined area regions.
在本新型創作一實施例中，上述多邊形圖案彼此連接而構成多個節點，且這些節點有至少部分位於預定面積區的邊界附近，且節點的此至少部分至邊界的最短距離不大於第一間距的10%或是不大於第二間距的10%。In an embodiment of the present invention, the polygonal patterns are connected to each other to form a plurality of nodes, and the nodes are at least partially located near a boundary of the predetermined area, and the shortest distance from the at least part of the node to the boundary is not greater than the first spacing. 10% or no more than 10% of the second spacing.
在本新型創作一實施例中，上述預定面積區各自包括一內縮預定面積區以及一節點設置面積區。節點設置面積區包圍內縮預定面積區。多邊形圖案彼此連接而構成多個節點，且節點設置於節點設置面積區中。內縮預定面積區在第一方向的寬度不小於第一間距的80%，而內縮預定面積區在第二方向的寬度不小於第二間距的80%。In an embodiment of the present invention, the predetermined area areas each include a retracted predetermined area area and a node set area area. The node setting area area surrounds the indented predetermined area area. The polygonal patterns are connected to each other to constitute a plurality of nodes, and the nodes are disposed in the node setting area area. The width of the indented predetermined area region in the first direction is not less than 80% of the first pitch, and the width of the indented predetermined area region in the second direction is not less than 80% of the second pitch.
在本新型創作一實施例中，上述列方向與行方向的交角相同於第一方向與第二方向的交角。第一方向與第二方向分別平行於列方向與行方向。第一方向與第二方向分別相交於列方向與行方向。In an embodiment of the present invention, the intersection angle of the column direction and the row direction is the same as the intersection angle of the first direction and the second direction. The first direction and the second direction are parallel to the column direction and the row direction, respectively. The first direction and the second direction intersect in the column direction and the row direction, respectively.
在本新型創作一實施例中，上述預定面積區的邊界相交於多個虛擬交點。多邊形圖案彼此連接而構成多個節點，且各節點位於相鄰兩個虛擬交點之間。各節點與相鄰兩個虛擬交點之間分別相隔一第一距離與一第二距離，且第一距離與第二距離都大於0。第一距離與第二距離相同。In an embodiment of the present invention, the boundaries of the predetermined area regions intersect at a plurality of virtual intersections. The polygonal patterns are connected to each other to form a plurality of nodes, and each node is located between two adjacent virtual intersections. Each node and the adjacent two virtual intersections are separated by a first distance and a second distance, and the first distance and the second distance are both greater than zero. The first distance is the same as the second distance.
在本新型創作一實施例中，上述導電網格構件包括多個疊置設置的子層，且各子層由多條細線構成。子層的細線垂直投影至畫素陣列結構上的投影輪廓構成多邊形圖案。In an embodiment of the present invention, the conductive mesh member includes a plurality of sub-layers disposed in a stack, and each sub-layer is composed of a plurality of thin wires. The projected outline of the sub-layer's thin lines vertically projected onto the pixel array structure constitutes a polygonal pattern.
在本新型創作一實施例中，上述電子裝置更包括一第一基板以及一第二基板。畫素陣列結構位於第一基板與第二基板之間而第一基板位於導電網格構件與畫素陣列結構之間。電子裝置更包括一第三基板，其覆蓋導電網格構件使導電網格構件位於第一基板與第三基板之間。電子裝置更包括一黏著層，黏著層配置於導電網格構件與第三基板之間，且導電網格構件配置於第一基板上。電子裝置更包括一黏著層，黏著層配置於導電網格構件與第一基板之間，且導電網格構件配置於第三基板上。電子裝置更包括一第三基板與一第一黏著層，其中第三基板位於第一基板與導電網格構件之間，且第一黏著層將第一基板與第三基板貼合。電子裝置更包括一第四基板，其覆蓋導電網格構件使導電網格構件位於第三基板與第四基板之間。電子裝置更包括一第二黏著層，第二黏著層配置於導電網格構件與第四基板之間，且導電網格構件配置於第三基板上。In an embodiment of the present invention, the electronic device further includes a first substrate and a second substrate. The pixel array structure is located between the first substrate and the second substrate and the first substrate is between the conductive mesh member and the pixel array structure. The electronic device further includes a third substrate covering the conductive mesh member such that the conductive mesh member is located between the first substrate and the third substrate. The electronic device further includes an adhesive layer disposed between the conductive mesh member and the third substrate, and the conductive mesh member is disposed on the first substrate. The electronic device further includes an adhesive layer disposed between the conductive mesh member and the first substrate, and the conductive mesh member is disposed on the third substrate. The electronic device further includes a third substrate and a first adhesive layer, wherein the third substrate is located between the first substrate and the conductive mesh member, and the first adhesive layer bonds the first substrate and the third substrate. The electronic device further includes a fourth substrate covering the conductive mesh member such that the conductive mesh member is located between the third substrate and the fourth substrate. The electronic device further includes a second adhesive layer disposed between the conductive mesh member and the fourth substrate, and the conductive mesh member is disposed on the third substrate.
在本新型創作一實施例中，上述導電網格構件的多邊形圖案構成訊號獨立的多個觸控電極。In an embodiment of the present invention, the polygonal pattern of the conductive mesh member constitutes a plurality of touch electrodes independently of signals.
在本新型創作一實施例中，上述各多邊形圖案由多條細線構成且各細線為直線、弧線、波浪線、折線或上述之組合。各細線的線寬為0.1μ m至1mm。各細線的線寬為0.1μ m至0.1mm。In an embodiment of the present invention, each of the polygonal patterns is composed of a plurality of thin lines, and each of the thin lines is a straight line, an arc, a wavy line, a broken line, or a combination thereof. Each thin line has a line width of 0.1 μm to 1 mm. Each thin line has a line width of 0.1 μm to 0.1 mm.
在本新型創作一實施例中，上述畫素開口區受導電網格構件遮蔽的面積比的差異小於20%。畫素開口區受導電網格構件遮蔽的面積比的差異小於10%。In an embodiment of the present invention, the area ratio of the pixel opening area blocked by the conductive mesh member is less than 20%. The area ratio of the pixel opening area blocked by the conductive mesh member is less than 10%.
本新型創作另一實施例的電子裝置，包括一導電網格構件以及一畫素陣列結構。導電網格構件配置於畫素陣列結構上方，其中畫素陣列結構包括排列成一陣列的多個畫素開口區，而畫素開口區受導電網格構件遮蔽的面積比的差異小於20%。The electronic device of another embodiment of the present invention includes a conductive mesh member and a pixel array structure. The conductive mesh member is disposed above the pixel array structure, wherein the pixel array structure comprises a plurality of pixel open regions arranged in an array, and the area ratio of the pixel open regions blocked by the conductive mesh members is less than 20%.
在本新型創作一實施例中，上述畫素開口區受導電網格構件遮蔽的面積比的差異小於10%。In an embodiment of the present invention, the area ratio of the pixel opening area blocked by the conductive mesh member is less than 10%.
本新型創作又一實施例的電子裝置包括一導電網格構件以及一畫素陣列結構。導電網格構件包括多個多邊形圖案，其中多邊形圖案彼此連接以構成多個節點，節點設置於一節點配置區中，且節點配置區圍出多個內縮預定面積區。各內縮預定面積區在第一方向上具有一第一寬度與一第一間距，第一寬度不小於第一間距的80%，而各內縮預定面積區在第二方向上具有一第二寬度與一第二間距，第二寬度不小於第二間距的80%。導電網格構件配置於畫素陣列結構上方，畫素陣列結構包括排列成一陣列的多個畫素開口區而任相鄰兩個畫素開口區之間設有一非開口區，且第一間距為n個畫素開口區以及(n-1)個非開口區在一列方向上的總寬度，而第二間距為m個畫素開口區以及(m-1)個非開口區在一行方向上的總寬度，其中n與m為正整數。The electronic device of still another embodiment of the present invention includes a conductive mesh member and a pixel array structure. The conductive mesh member includes a plurality of polygonal patterns, wherein the polygonal patterns are connected to each other to constitute a plurality of nodes, the nodes are disposed in a node configuration area, and the node arrangement area encloses a plurality of indented predetermined area areas. Each of the indented predetermined area regions has a first width and a first spacing in the first direction, the first width is not less than 80% of the first spacing, and each of the indented predetermined area regions has a second in the second direction The width is a second spacing, and the second width is not less than 80% of the second spacing. The conductive mesh member is disposed above the pixel array structure, and the pixel array structure comprises a plurality of pixel opening regions arranged in an array, and a non-opening region is disposed between adjacent two pixel opening regions, and the first spacing is n The total width of the pixel open area and (n-1) non-open areas in one column direction, and the second interval is m pixel open areas and the total width of (m-1) non-open areas in one row direction Where n and m are positive integers.
基於上述，本新型創作實施例的電子裝置，於畫素陣列結構上方設置有導電網格構件，且導電網格構件的網格圖案設置於規律排列的多個預定面積區中。預定面積區的排列與畫素陣列結構中的畫素開口區排列可以設定為具有一特定關係而使這些畫 素開口區被導電網格構件遮蔽的面積均勻化。如此一來，電子裝置可以具有理想的顯示品質。Based on the above, in the electronic device of the present invention, a conductive mesh member is disposed above the pixel array structure, and the mesh pattern of the conductive mesh member is disposed in a plurality of predetermined area regions regularly arranged. The arrangement of the predetermined area regions and the pixel opening area arrangement in the pixel array structure may be set to have a specific relationship to make the pictures The area of the open area that is covered by the conductive mesh member is uniformized. In this way, the electronic device can have an ideal display quality.
為讓本新型創作的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will become more apparent and understood from the following description.
10A、10B、10C、10D、10E、100、100A、200、300、400、500‧‧‧電子裝置10A, 10B, 10C, 10D, 10E, 100, 100A, 200, 300, 400, 500‧‧‧ electronic devices
20、110、210、310、410、510、610‧‧‧導電網格構件20, 110, 210, 310, 410, 510, 610‧‧‧ conductive mesh members
30、120‧‧‧畫素陣列結構30, 120‧‧‧ pixel array structure
40‧‧‧第一基板40‧‧‧First substrate
50‧‧‧第二基板50‧‧‧second substrate
60‧‧‧保護層60‧‧‧Protective layer
70‧‧‧第三基板70‧‧‧ third substrate
80、82‧‧‧黏著層80, 82‧‧‧ adhesive layer
90‧‧‧第四基板90‧‧‧fourth substrate
112、212、312、412、512‧‧‧多邊形圖案112, 212, 312, 412, 512‧‧‧ polygon patterns
114、214、314、414、514‧‧‧節點114, 214, 314, 414, 514‧‧‧ nodes
116、612A、612B‧‧‧導電細線116, 612A, 612B‧‧‧ conductive thin wire
118‧‧‧開口118‧‧‧ openings
122、122A、122B、122C、122D‧‧‧畫素開口區122, 122A, 122B, 122C, 122D‧‧‧ pixel open area
124‧‧‧非開口區124‧‧‧Non-open area
602‧‧‧基板602‧‧‧Substrate
602A‧‧‧中央區602A‧‧‧Central District
602B‧‧‧周圍區602B‧‧‧ surrounding area
604‧‧‧裝飾層604‧‧‧Decorative layer
606‧‧‧第一絕緣層606‧‧‧First insulation
606A、608A‧‧‧接觸洞606A, 608A‧‧‧ contact hole
608‧‧‧第二絕緣層608‧‧‧Second insulation
610A、610B‧‧‧子層610A, 610B‧‧‧ sub-layer
614A、614B‧‧‧圖案單元614A, 614B‧‧‧ pattern unit
A1、A2、A3、A4、A5、A6‧‧‧預定面積區A1, A2, A3, A4, A5, A6‧‧‧ predetermined area
A7‧‧‧內縮預定面積區A7‧‧‧ contracted area
A8‧‧‧節點設置面積區A8‧‧‧ node setting area
C‧‧‧行方向C‧‧‧ directions
D1、D2‧‧‧方向D1, D2‧‧‧ direction
d1、d2、d3、d4、d5‧‧‧距離D1, d2, d3, d4, d5‧‧‧ distance
L1、L2、L3、L4、L5、L6、L7、L8、L9、L10‧‧‧虛擬線L1, L2, L3, L4, L5, L6, L7, L8, L9, L10‧‧‧ virtual lines
N‧‧‧虛擬交點N‧‧‧ virtual intersection
P1、P2、P3、P4、P5、P6、P7、P8、P9、P10‧‧‧間距P1, P2, P3, P4, P5, P6, P7, P8, P9, P10‧‧‧ spacing
R‧‧‧列方向R‧‧‧ direction
W‧‧‧線寬W‧‧‧Line width
W1、W2、W3、W4、W5、W6、W7、W8‧‧‧寬度W1, W2, W3, W4, W5, W6, W7, W8‧‧‧ width
Θ‧‧‧角度Θ‧‧‧ angle
圖1A為本新型創作一實施例的電子裝置的示意圖。FIG. 1A is a schematic diagram of an electronic device according to an embodiment of the present invention.
圖1B為圖1A的電子裝置中導電網格結構的佈局方式示意圖。1B is a schematic view showing the layout of a conductive mesh structure in the electronic device of FIG. 1A.
圖2為圖1A的電子裝置中導電網格構件與畫素陣列結構各自獨立的示意圖。2 is a schematic diagram of the conductive grid member and the pixel array structure in the electronic device of FIG. 1A.
圖3為本新型創作一實施例的電子裝置的示意圖。FIG. 3 is a schematic diagram of an electronic device according to an embodiment of the present invention.
圖4為本新型創作另一實施例的電子裝置的示意圖。4 is a schematic diagram of an electronic device according to another embodiment of the present invention.
圖5為圖4的電子裝置中導電網格構件與畫素陣列結構各自獨立的示意圖。FIG. 5 is a schematic diagram of the conductive grid member and the pixel array structure in the electronic device of FIG. 4, respectively.
圖6為本新型創作又一實施例的電子裝置的示意圖。FIG. 6 is a schematic diagram of an electronic device according to still another embodiment of the present invention.
圖7為本新型創作另一實施例的電子裝置的示意圖。FIG. 7 is a schematic diagram of an electronic device according to another embodiment of the present invention.
圖8為圖7的電子裝置中導電網格構件與畫素陣列結構各自獨立的示意圖。FIG. 8 is a schematic diagram of the conductive grid member and the pixel array structure in the electronic device of FIG. 7 respectively.
圖9A為本新型創作再一實施例的電子裝置的示意圖。FIG. 9A is a schematic diagram of an electronic device according to still another embodiment of the present invention.
圖9B為圖9A的電子裝置中導電網格結構的佈局方式示意 圖。FIG. 9B is a schematic diagram showing the layout of the conductive grid structure in the electronic device of FIG. 9A; Figure.
圖10A為本新型創作一實施例的導電網格構件的示意圖。FIG. 10A is a schematic view of a conductive mesh member of an embodiment of the present invention.
圖10B為圖10A的導電網格結構配置於基板上的剖面示意圖。FIG. 10B is a schematic cross-sectional view showing the conductive mesh structure of FIG. 10A disposed on a substrate. FIG.
圖11A至圖11E為本新型創作多個實施例的電子裝置的剖面示意圖。11A-11E are schematic cross-sectional views of an electronic device in which various embodiments are created.
圖1A為本新型創作一實施例的電子裝置的示意圖，在圖1A中的電子裝置例如是搭配有觸控結構的顯示裝置，而圖2為圖1A的電子裝置中導電網格構件與畫素陣列結構各自獨立的示意圖。1A is a schematic diagram of an electronic device according to an embodiment of the present invention. The electronic device in FIG. 1A is, for example, a display device with a touch structure, and FIG. 2 is a conductive mesh member and a pixel in the electronic device of FIG. 1A. A separate schematic of the array structure.
請參照圖1A與圖2，圖1A及2繪示部份的觸控結構搭配顯示裝置的子畫素(subpixel)結構示意圖。電子裝置100的觸控結構包括導電網格構件110，而顯示裝置包括畫素陣列結構120，其中導電網格構件110包括多個多邊形圖案112，且這些多邊形圖案112彼此藉由多條導電細線116連接而構成多個節點114，例如圖1所示，各多邊形圖案112彼此藉由4條導電細線116連接而構成4個節點114，而畫素陣列結構120則包括有排列成一陣列的多個畫素開口區122，即多個子畫素，而任相鄰兩個畫素開口區122之間設有一非開口區124。在此，非開口區124是指畫素陣列結構120中不用來顯示的區域，依照一般的顯示裝置設計而言， 非開口區124構成一黑色矩陣(black matrix)結構。由圖1與圖2可知，導電網格構件110配置於畫素陣列結構120上方，因此使用者使用電子裝置100時，導電網格構件110位於使用者與畫素陣列結構120之間。值得一提的是，本新型創作的導電網格構件110構成觸控結構中的觸控電極，以供使用者在進行觸碰操作時，藉由互容式或是自容式的操作依據觸控電極的電容變化進行觸碰偵測。在此，互容式操作為利用觸控電極之間的電容變化進行觸碰偵測；自容式操作則利用導体(如手指或觸控筆)接近觸控電極造成的電容變化進行觸碰偵測。Please refer to FIG. 1A and FIG. 2 . FIG. 1A and FIG. 2 are schematic diagrams showing a subpixel structure of a part of the touch structure and the display device. The touch structure of the electronic device 100 includes a conductive mesh member 110, and the display device includes a pixel array structure 120, wherein the conductive mesh member 110 includes a plurality of polygonal patterns 112, and the polygonal patterns 112 are mutually coupled by a plurality of conductive thin lines 116 A plurality of nodes 114 are connected to each other. For example, as shown in FIG. 1, each polygon pattern 112 is connected to each other by four conductive thin wires 116 to form four nodes 114, and the pixel array structure 120 includes a plurality of pictures arranged in an array. The open area 122 is a plurality of sub-pixels, and a non-open area 124 is disposed between adjacent two pixel open areas 122. Here, the non-opening area 124 refers to an area in the pixel array structure 120 that is not used for display. According to a general display device design, The non-opening area 124 constitutes a black matrix structure. As shown in FIG. 1 and FIG. 2 , the conductive mesh member 110 is disposed above the pixel array structure 120 . Therefore, when the user uses the electronic device 100 , the conductive mesh member 110 is located between the user and the pixel array structure 120 . It is worth mentioning that the conductive mesh member 110 of the present invention constitutes a touch electrode in the touch structure, so that the user can touch the touch operation by mutual capacitance or self-capacity operation. Touch detection is performed by changing the capacitance of the control electrode. Here, the mutual capacitive operation is to perform touch detection by using a change in capacitance between the touch electrodes; the self-capacitance operation uses a conductor (such as a finger or a stylus) to approach the touch electrode to cause a change in capacitance to perform touch detection. Measurement.
多邊形圖案112如是由多條導電細線116所構成的封閉網格圖案，且各導電細線116為直線、弧線、波浪線、折線或上述之組合，如圖1所示，由4條導電細線116構成一菱形的封閉網格圖案。導電細線116的材質可為金屬例如金、鋁、銅、銀、鉻、鈦、鉬、釹之其中至少一者、上述材料之合金、上述材料之複合層或上述材料與上述材料之合金之複合層，但並不以此為限而可使用其他導電材料。再者，以上所述的複合層可以例如是由鉬、鋁-釹合金及鉬組成的三層堆疊結構，但亦不以此為限，只要能達到導電效果的堆疊結構亦在本新型創作的保護範圍內。當然，導電細線的材質可以是非金屬的導電材質，如有機導電材質、氧化物導電材質等。多邊形圖案112中，各導電細線116的線寬W例如是介於0.1微米(μm)至1毫米(mm)，或是0.1微米至0.1毫米，或是0.1微米至30微米，或是1微米至10微米。而且，多邊 形圖案112所連接而成的導電網格構件110具有多個開口118，這些開口118所佔面積相較於導電細線116所佔面積大許多，故可使得導電網格構件110對於可見光的透光率達75%以上，甚至較佳透光率可達85%以上。The polygonal pattern 112 is a closed mesh pattern composed of a plurality of conductive thin wires 116, and each of the conductive thin wires 116 is a straight line, an arc, a wavy line, a broken line or a combination thereof, and is composed of four conductive thin wires 116 as shown in FIG. A diamond-shaped closed grid pattern. The conductive thin wire 116 may be made of a metal such as at least one of gold, aluminum, copper, silver, chromium, titanium, molybdenum, tantalum, an alloy of the above materials, a composite layer of the above materials, or a composite of the above materials and alloys of the above materials. Layers, but not limited to other conductive materials. Furthermore, the composite layer described above may be, for example, a three-layer stacked structure composed of molybdenum, an aluminum-niobium alloy, and molybdenum, but is not limited thereto, as long as a stacking structure capable of achieving a conductive effect is also created in the novel. Within the scope of protection. Of course, the material of the conductive thin wire may be a non-metallic conductive material, such as an organic conductive material, an oxide conductive material, or the like. In the polygonal pattern 112, the line width W of each of the conductive thin wires 116 is, for example, 0.1 micrometer (μm) to 1 millimeter (mm), or 0.1 micrometer to 0.1 millimeter, or 0.1 micrometer to 30 micrometer, or 1 micrometer to 10 microns. And multilateral The conductive mesh member 110 connected by the pattern 112 has a plurality of openings 118. The area occupied by the openings 118 is much larger than the area occupied by the conductive thin wires 116, so that the conductive mesh member 110 can transmit light to visible light. The rate is above 75%, and even the preferred light transmittance is over 85%.
整體而言，導電網格構件110具有良好的導電性以及高度的可見光穿透率。因此，將導電網格構件110設置於使用者與畫素陣列結構120之間，不會因為導電網格構件110的存在而明顯降低電子裝置100的顯示亮度，所以導電網格構件110可以用來取代整面沉積的透明導電氧化物薄膜。不過，導電網格構件110的導電細線116與開口118對光線的穿透率差異相當顯著。將導電網格構件110配置於畫素陣列結構120上方，可能影響電子裝置100在顯示效果上的均勻性。因此，多邊形圖案112的排列規律與畫素陣列結構120的排列規律，兩者的關係需要詳加設計。特別是，在本實施例中，經由圖2的配置規律，這些畫素開口區122受導電網格構件110遮蔽的面積比的差異明顯減小以達到理想的顯示效果。Overall, the conductive mesh member 110 has good electrical conductivity and a high visible light transmittance. Therefore, the conductive mesh member 110 is disposed between the user and the pixel array structure 120, and the display brightness of the electronic device 100 is not significantly reduced due to the presence of the conductive mesh member 110. Therefore, the conductive mesh member 110 can be used. Instead of a transparent conductive oxide film deposited over the entire surface. However, the difference in the transmittance of the conductive thin wires 116 and the openings 118 of the conductive mesh member 110 to the light is quite remarkable. The conductive mesh member 110 is disposed above the pixel array structure 120, which may affect the uniformity of the display effect of the electronic device 100. Therefore, the arrangement rule of the polygon pattern 112 and the arrangement rule of the pixel array structure 120, the relationship between the two needs to be detailedly designed. In particular, in the present embodiment, the difference in the area ratio of the pixel opening regions 122 blocked by the conductive mesh members 110 is significantly reduced via the configuration rule of FIG. 2 to achieve a desired display effect.
具體而言，請參照圖1A、圖1B與圖2，多邊形圖案112在此係依據多個預定面積區A1排列，其中預定面積區A1在一第一方向D1上規律排列而具有一第一間距P1，並在一第二方向D2上規律排列而具有一第二間距P2。畫素開口區122沿著列方向R與行方向C規律排列而構成陣列時，第一方向D1與第二方向D2相交的交角相同於列方向R與行方向C的夾角。在本實施例中， 導電網格構件110與畫素陣列結構120堆疊在一起時，第一方向D1平行於列方向R，而第二方向D2平行於行方向C，但本新型創作不以此為限。在其他的實施例中，第一方向D1可以與列方向R相交一角度，而同時第二方向D2可以與行方向C相交相同的角度。本實施例的設計可以讓預定面積區A1依照畫素開口區122的分布規律來設計。因此，導電網格構件110可以具有下列的排列規律。Specifically, referring to FIG. 1A, FIG. 1B and FIG. 2, the polygonal pattern 112 is arranged according to a plurality of predetermined area areas A1, wherein the predetermined area area A1 is regularly arranged in a first direction D1 to have a first spacing. P1 is regularly arranged in a second direction D2 to have a second pitch P2. When the pixel opening area 122 is regularly arranged along the column direction R and the row direction C to form an array, the intersection angle of the first direction D1 and the second direction D2 is the same as the angle between the column direction R and the row direction C. In this embodiment, When the conductive mesh member 110 and the pixel array structure 120 are stacked together, the first direction D1 is parallel to the column direction R, and the second direction D2 is parallel to the row direction C, but the novel creation is not limited thereto. In other embodiments, the first direction D1 may intersect the column direction R by an angle while the second direction D2 may intersect the row direction C by the same angle. The design of this embodiment allows the predetermined area area A1 to be designed in accordance with the distribution rule of the pixel opening area 122. Therefore, the conductive mesh member 110 can have the following arrangement law.
在本實施例中，每個預定面積區A1設計為對應於一個畫素開口區122，因此第一間距P1為一個畫素開口區122與零個非開口區124在列方向R上的總寬度W1，而第二間距P2為一個畫素開口區122與零個非開口區124在行方向C上的總寬度W2。不過，本新型創作不以此為限。在其他實施例中，每個預定面積區A1對應於多個畫素開口區122時，第一間距P1可以為n個畫素開口區122以及(n-1)個非開口區124在列方向R上的總寬度，而第二間距P2為m個畫素開口區122以及(m-1)個非開口區124在行方向C上的總寬度，其中n與m為正整數。In the present embodiment, each predetermined area area A1 is designed to correspond to one pixel open area 122, so the first pitch P1 is the total width of one pixel open area 122 and zero non-open areas 124 in the column direction R. W1, and the second pitch P2 is the total width W2 of the pixel opening area 122 and the zero non-opening areas 124 in the row direction C. However, this new creation is not limited to this. In other embodiments, when each predetermined area area A1 corresponds to the plurality of pixel open areas 122, the first pitch P1 may be n pixel open areas 122 and (n-1) non-open areas 124 in the column direction. The total width on R, and the second pitch P2 is the total width of the m pixel open areas 122 and (m-1) non-open areas 124 in the row direction C, where n and m are positive integers.
在本實施例中，預定面積區A1的邊界可以由虛擬線L1與L2來界定。由圖1B與圖2可知，虛擬線L1與L2各自通過多個節點114，也就是說節點114是位於預定面積區A1的邊界上。同時，虛擬線L1與L2相交於多個虛擬交點N，且各節點114位於相鄰兩個虛擬交點N之間。各節點114與相鄰兩個虛擬交點N之間分別相隔一第一距離d1與一第二距離d2。在此，第一距離 d1與第二距離d2的比為1：1。各虛擬線L1與L2大致為直線，其中虛擬線L1都大致上平行於方向D1，而虛擬線L2都大致上平行於方向D2且方向D1與方向D2相交。In the present embodiment, the boundary of the predetermined area area A1 may be defined by the virtual lines L1 and L2. As can be seen from FIG. 1B and FIG. 2, the virtual lines L1 and L2 each pass through a plurality of nodes 114, that is, the nodes 114 are located on the boundary of the predetermined area area A1. At the same time, the virtual lines L1 and L2 intersect at a plurality of virtual intersections N, and each node 114 is located between two adjacent virtual intersections N. Each node 114 and the adjacent two virtual intersections N are separated by a first distance d1 and a second distance d2, respectively. Here, the first distance The ratio of d1 to the second distance d2 is 1:1. Each of the imaginary lines L1 and L2 is substantially a straight line, wherein the imaginary line L1 is substantially parallel to the direction D1, and the imaginary line L2 is substantially parallel to the direction D2 and the direction D1 intersects the direction D2.
一般來說，各個畫素開口區122的面積影響著顯示亮度。由圖1可知，多邊形圖案112的分布規律是依據畫素陣列結構120中畫素開口區122的尺寸與分布規律而設計。每個畫素開口區122被多邊形圖案112遮蔽的面積比例會大致相同。因此，基於導電網格構件110的遮蔽而使這些畫素開口區122所呈現的亮度下降的程度大致是相同的，藉以達到均勻的顯示效果。舉例來說，這些畫素開口區122被遮蔽的比例的差異小於20%甚至是小於10%。在部分實施例中，畫素開口區122若是矩形，這些畫素開口區122被遮蔽的比例的差異可以小於1%。若畫素開口區是折曲如V字形的設計(常見於邊緣電場式液晶顯示面板(FFS LCD)中的畫素開口區設計)，則這些畫素開口區122被遮蔽的比例的差異約4~5%。換言之，選取兩個畫素開口區122A、122B來看，這兩個畫素開口區122A、122B的開口面積分別為Z0而兩畫素開口區122A、122B被遮蔽的面積分別為Z1與Z2時，20%>|[(Z1-Z2)/Z0]|。如此一來，讓電子裝置100可以呈現均勻的顯示效果，特別是，電子裝置100不會因為導電網格構件110設置於畫素陣列結構120與使用者之間而呈現不均勻的顯示品質。In general, the area of each pixel open area 122 affects display brightness. As can be seen from FIG. 1, the distribution pattern of the polygonal pattern 112 is designed according to the size and distribution law of the pixel opening region 122 in the pixel array structure 120. The area ratio of each of the pixel open areas 122 masked by the polygonal pattern 112 will be substantially the same. Therefore, the degree of brightness reduction of the pixel opening regions 122 is substantially the same based on the shielding of the conductive mesh members 110, thereby achieving a uniform display effect. For example, the difference in the ratio of the masked open areas 122 being masked is less than 20% or even less than 10%. In some embodiments, if the pixel opening regions 122 are rectangular, the difference in the ratio of the pixel opening regions 122 to be masked may be less than 1%. If the pixel opening area is a curved, V-shaped design (typically a pixel open area design in a fringe field type liquid crystal display panel (FFS LCD)), the difference in the ratio of the mask opening areas 122 to be masked is about 4 ~5%. In other words, when the two pixel open areas 122A, 122B are selected, the opening areas of the two pixel open areas 122A, 122B are respectively Z0 and the areas of the two pixel open areas 122A, 122B are shielded by Z1 and Z2, respectively. , 20%>|[(Z1-Z2)/Z0]|. In this way, the electronic device 100 can display a uniform display effect. In particular, the electronic device 100 does not exhibit uneven display quality because the conductive mesh member 110 is disposed between the pixel array structure 120 and the user.
不過，本新型創作不以圖1的布局方式為限，在其他的實施例中，列方向R與方向D1可以相交一角度。舉例而言，導電 網格構件110與畫素陣列結構120的位置關係可以如圖3所示。請先參照圖3，電子裝置100A包括導電網格構件110與畫素陣列結構120，其中導電網格構件110與畫素陣列結構120各自的結構設計可參照圖2的相關描述。不過，圖3不同於圖1之處在於，電子裝置100A的導電網格構件110所定義出來的預定面積區A2的邊界(虛擬線L1與L2)並不平行於畫素開口區122的列方向R與行方向C。However, the novel creation is not limited to the layout of FIG. 1. In other embodiments, the column direction R and the direction D1 may intersect at an angle. For example, conductive The positional relationship of the mesh member 110 and the pixel array structure 120 can be as shown in FIG. Referring to FIG. 3 , the electronic device 100A includes a conductive mesh member 110 and a pixel array structure 120 . The structural design of each of the conductive mesh member 110 and the pixel array structure 120 can be referred to the related description of FIG. 2 . However, FIG. 3 differs from FIG. 1 in that the boundary (virgin lines L1 and L2) of the predetermined area area A2 defined by the conductive mesh member 110 of the electronic device 100A is not parallel to the column direction of the pixel open area 122. R and row direction C.
由圖3可知，在本實施例中，導電網格構件110相較於電子裝置100的導電網格構件110旋轉一角度θ，其例如為5度。因此，列方向R與虛擬線L1的延伸方向(第一方向D1)相交5度，而行方向C與虛擬線L2的延伸方向(第二方向D2)相交5度。導電網格構件110中多邊形圖案112的排列間距與畫素陣列結構120中畫素開口區122的尺寸相同，因此電子裝置100A中這些畫素開口區122被導電網格構件110遮蔽的面積比例仍是大致相同的。舉例而言，畫素開口區122C被導電網格構件110遮蔽的面積比率為28.5%而畫素開口區122D被導電網格構件110遮蔽的面積比率為29%，兩者的遮蔽面積比的差異為0.5%。As can be seen from FIG. 3, in the present embodiment, the conductive mesh member 110 is rotated by an angle θ compared to the conductive mesh member 110 of the electronic device 100, which is, for example, 5 degrees. Therefore, the column direction R intersects the extending direction of the virtual line L1 (the first direction D1) by 5 degrees, and the row direction C intersects the extending direction of the virtual line L2 (the second direction D2) by 5 degrees. The arrangement pitch of the polygonal patterns 112 in the conductive mesh member 110 is the same as the size of the pixel open regions 122 in the pixel array structure 120, so the area ratio of the pixel opening regions 122 in the electronic device 100A blocked by the conductive mesh members 110 is still It is roughly the same. For example, the area ratio of the pixel opening area 122C blocked by the conductive mesh member 110 is 28.5%, and the area ratio of the pixel opening area 122D blocked by the conductive mesh member 110 is 29%, and the difference of the shielding area ratio between the two It is 0.5%.
一般來說，在製作電子裝置100或100A時，導電網格構件110與畫素陣列結構120是分別製作於不同基板上而後藉由貼合的方式將兩基板貼合在一起以使導電網格構件110位於畫素陣列結構120上方。因此，圖3中的角度θ都可能是基於貼合製程中可能發生的對位誤差而發生的。不過，在上述實施例中，雖 然對位上發生了誤差，基於導電網格構件110與畫素陣列結構120的布局規律具有一定的關係(如圖2及相關的描述所示)，電子裝置100或100A仍可以保有理想的顯示品質並且導電網格構件110可以提供良好的導電性以實現所需要的功能。因此，在本實施例的設計方式下，電子裝置100與100A可以具有更高的製作良率。Generally, when the electronic device 100 or 100A is fabricated, the conductive mesh member 110 and the pixel array structure 120 are separately fabricated on different substrates, and then the two substrates are bonded together by a bonding method to make the conductive mesh. Member 110 is located above pixel array structure 120. Therefore, the angle θ in FIG. 3 may all occur based on a registration error that may occur in the bonding process. However, in the above embodiment, However, an error occurs in the alignment, and based on the layout rule of the conductive mesh member 110 and the pixel array structure 120 (as shown in FIG. 2 and related description), the electronic device 100 or 100A can still maintain an ideal display. The quality and conductive mesh member 110 can provide good electrical conductivity to achieve the desired functionality. Therefore, in the design mode of the embodiment, the electronic devices 100 and 100A can have higher production yield.
在前述實施例中，以單一個畫素開口區122的尺寸作為設計導電網格構件110的參考依據，不過，本新型創作也可以選擇以多個畫素開口區122的尺寸作為設計導電網格構件110的參考依據。In the foregoing embodiment, the size of the single pixel opening area 122 is used as a reference for designing the conductive mesh member 110. However, the novel creation may also select the size of the plurality of pixel opening areas 122 as the design conductive grid. Reference basis for member 110.
圖4為本新型創作另一實施例的電子裝置的示意圖，而圖5為圖4的電子裝置中導電網格構件與畫素陣列結構的拆解示意圖。請參照圖4與圖5，電子裝置200包括導電網格構件210與畫素陣列結構120，其中導電網格構件210包括多個多邊形圖案212，且這些多邊形圖案212彼此連接而構成多個節點214，而畫素陣列結構120則包括有排列成一陣列的多個畫素開口區122，且畫素開口區122之間設置有非開口區124。在此，畫素陣列結構120可以參照前述實施例的說明而不另贅述。由圖4與圖5可知，導電網格構件210配置於畫素陣列結構120上方，因此使用者使用電子裝置200時，導電網格構件210位於使用者與畫素陣列結構120之間。4 is a schematic diagram of an electronic device according to another embodiment of the present invention, and FIG. 5 is a schematic diagram of disassembly of a conductive mesh member and a pixel array structure in the electronic device of FIG. 4. Referring to FIG. 4 and FIG. 5, the electronic device 200 includes a conductive mesh member 210 and a pixel array structure 120. The conductive mesh member 210 includes a plurality of polygonal patterns 212, and the polygonal patterns 212 are connected to each other to form a plurality of nodes 214. The pixel array structure 120 includes a plurality of pixel opening regions 122 arranged in an array, and a non-opening region 124 is disposed between the pixel opening regions 122. Here, the pixel array structure 120 can refer to the description of the foregoing embodiment without further elaboration. As shown in FIG. 4 and FIG. 5 , the conductive mesh member 210 is disposed above the pixel array structure 120 . Therefore, when the user uses the electronic device 200 , the conductive mesh member 210 is located between the user and the pixel array structure 120 .
具體來說，在本實施例中，依據畫素陣列結構120的畫素開口區122的尺寸而決定導電網格構件210的排列時，預定面 積區A3可以對應於三個畫素開口區122來設計。因此，導電網格構件210可以具有下列的排列規律。Specifically, in the present embodiment, when the arrangement of the conductive mesh members 210 is determined according to the size of the pixel opening region 122 of the pixel array structure 120, the predetermined surface The product area A3 can be designed corresponding to the three pixel opening areas 122. Therefore, the conductive mesh member 210 can have the following arrangement rules.
多邊形圖案212在此係依據多個預定面積區A3排列，其中預定面積區A3在第一方向D1上規律排列而具有第一間距P3，在第二方向D2上規律排列而具有第二間距P4。畫素開口區122沿著列方向R與行方向C規律排列而構成陣列時，第一方向D1與第二方向D2相交的交角相同於列方向R與行方向C的夾角。另外，每個預定面積區A3設計為對應於同一列方向R上的三個畫素開口區122，因此第一間距P3可以為3個畫素開口區122以及2個非開口區124在列方向R上的總寬度W3，而第二間距P4為1個畫素開口區122與0個非開口區124在行方向C上的總寬度W4。也就是說，預定面積區A3對應於n個畫素開口區122時，各預定面積區A3在一方向上的間距可以為n個畫素開口區122以及(n-1)個非開口區124在此方向上的總寬度，其中n為正整數。The polygonal pattern 212 is here arranged in accordance with a plurality of predetermined area areas A3, wherein the predetermined area areas A3 are regularly arranged in the first direction D1 to have a first pitch P3, and are regularly arranged in the second direction D2 to have a second pitch P4. When the pixel opening area 122 is regularly arranged along the column direction R and the row direction C to form an array, the intersection angle of the first direction D1 and the second direction D2 is the same as the angle between the column direction R and the row direction C. In addition, each of the predetermined area areas A3 is designed to correspond to the three pixel open areas 122 in the same column direction R, so the first pitch P3 may be three pixel open areas 122 and two non-open areas 124 in the column direction. The total width W3 on R, and the second pitch P4 is the total width W4 of the 1 pixel open area 122 and the 0 non-open areas 124 in the row direction C. That is, when the predetermined area area A3 corresponds to the n pixel opening areas 122, the spacing of each predetermined area area A3 in one direction may be n pixel opening areas 122 and (n-1) non-opening areas 124 at The total width in this direction, where n is a positive integer.
在本實施例中，導電網格構件210的這些節點214是以規律方式排列，因此將導電網格構件210的這些節點214連接起來可以獲得多條虛擬線L3與L4。虛擬線L3大致上彼此平行，而虛擬線L4大致上彼此平行。虛擬線L3延伸於第一方向D1而虛擬線L4延伸於第二方向D2。虛擬線L3與L4為預定面積區A3的邊界，虛擬線L3與L4相交於多個虛擬交點N，且各節點214位於相鄰兩個虛擬交點N之間。各個節點214落在相鄰兩個虛擬交點N的中間。由圖5可知，單一個多邊形圖案212大致對應於 三個畫素開口區122，而此三個畫素開口區122可以顯示不同的色彩，例如紅、綠與藍，但本新型創作不以此為限。In the present embodiment, the nodes 214 of the conductive mesh member 210 are arranged in a regular manner, so that the nodes 214 of the conductive mesh member 210 are connected to obtain a plurality of virtual lines L3 and L4. The virtual lines L3 are substantially parallel to each other, and the virtual lines L4 are substantially parallel to each other. The virtual line L3 extends in the first direction D1 and the virtual line L4 extends in the second direction D2. The virtual lines L3 and L4 are the boundaries of the predetermined area area A3, the virtual lines L3 and L4 intersect with the plurality of virtual intersections N, and each node 214 is located between the adjacent two virtual intersections N. Each node 214 falls in the middle of two adjacent virtual intersections N. As can be seen from FIG. 5, a single polygonal pattern 212 roughly corresponds to The three pixels open area 122, and the three pixel open areas 122 can display different colors, such as red, green and blue, but the novel creation is not limited thereto.
在本實施例中，導電網格構件210的排列規律與畫素開口區122的排列規律呈現特定關係，因此這些畫素開口區122被導電網格構件210遮蔽的面積比的差異不大。舉例來說，畫素開口區122被遮蔽的面積比例的差異小於20%甚至是小於10%。因此，電子裝置200可以具有理想的顯示品質。In the present embodiment, the arrangement rule of the conductive mesh members 210 and the arrangement rule of the pixel open regions 122 exhibit a specific relationship, and therefore the area ratios of the pixel opening regions 122 blocked by the conductive mesh members 210 are not much different. For example, the difference in the proportion of the area of the pixel open area 122 that is masked is less than 20% or even less than 10%. Therefore, the electronic device 200 can have an ideal display quality.
圖6為本新型創作又一實施例的電子裝置的示意圖。請參照圖6，電子裝置300包括導電網格構件310與畫素陣列結構120，其中導電網格構件310包括多個多邊形圖案312，且這些多邊形圖案312彼此連接而構成多個節點314，而畫素陣列結構120則包括有排列成一陣列的多個畫素開口區122以及設置於畫素開口區122之間的非開口區124。在此，畫素陣列結構120可以參照前述實施例的說明而不另贅述。由圖6可知，導電網格構件310配置於畫素陣列結構120上方，因此使用者使用電子裝置300時，導電網格構件310位於使用者與畫素陣列結構120之間。FIG. 6 is a schematic diagram of an electronic device according to still another embodiment of the present invention. Referring to FIG. 6, the electronic device 300 includes a conductive mesh member 310 and a pixel array structure 120. The conductive mesh member 310 includes a plurality of polygonal patterns 312, and the polygonal patterns 312 are connected to each other to form a plurality of nodes 314, and The pixel array structure 120 includes a plurality of pixel opening regions 122 arranged in an array and a non-opening region 124 disposed between the pixel opening regions 122. Here, the pixel array structure 120 can refer to the description of the foregoing embodiment without further elaboration. As shown in FIG. 6 , the conductive mesh member 310 is disposed above the pixel array structure 120 . Therefore, when the user uses the electronic device 300 , the conductive mesh member 310 is located between the user and the pixel array structure 120 .
具體來說，在本實施例中，依據畫素陣列結構120的畫素開口區122的尺寸而決定導電網格構件310的排列時，預定面積區A4可以對應於2×2的四個畫素開口區122來設計。因此，導電網格構件310可以具有下列的排列規律。多邊形圖案312在此係依據多個預定面積區A4排列，其中預定面積區A4在第一方向D1上規律排列而具有第一間距P5，在第二方向D2上規律排列而 具有第二間距P6。畫素開口區122沿著列方向R與行方向C規律排列而構成陣列時，第一方向D1與第二方向D2相交的交角相同於列方向R與行方向C的夾角。另外，每個預定面積區A4設計為對應於2×2的四個畫素開口區122，因此第一間距P5可以為2個畫素開口區122以及1個非開口區124在列方向R上的總寬度W5，而第二間距P6為2個畫素開口區122以及1個非開口區124在行方向C上的總寬度W6。Specifically, in the present embodiment, when the arrangement of the conductive mesh members 310 is determined according to the size of the pixel opening region 122 of the pixel array structure 120, the predetermined area A4 may correspond to 2 pixels of 2×2. The open area 122 is designed. Therefore, the conductive mesh member 310 can have the following arrangement rules. The polygonal pattern 312 is arranged here according to a plurality of predetermined area areas A4, wherein the predetermined area areas A4 are regularly arranged in the first direction D1 to have a first pitch P5, which are regularly arranged in the second direction D2. There is a second pitch P6. When the pixel opening area 122 is regularly arranged along the column direction R and the row direction C to form an array, the intersection angle of the first direction D1 and the second direction D2 is the same as the angle between the column direction R and the row direction C. In addition, each predetermined area area A4 is designed to correspond to 2×2 of four pixel open areas 122, so the first pitch P5 may be 2 pixel open areas 122 and 1 non-open area 124 in the column direction R. The total width W5 is the total width W6 of the two pixel open areas 122 and one non-opening area 124 in the row direction C.
導電網格構件310的這些節點314連接起來可以獲得多條虛擬線L5與L6。虛擬線L5大致上彼此平行，而虛擬線L6大致上彼此平行。虛擬線L5延伸於第一方向D1與虛擬線L6延伸於第二方向D2。並且，第一方向D1與第二方向D2分別平行列方向R與行方向C。在此，虛擬線L5與虛擬線L6為多個預定面積區A4的邊界。虛擬線L5與L6相交於多個虛擬交點N，且各節點314位於相鄰兩個虛擬交點N之間。各個節點314落在相鄰兩個虛擬交點N的中間且位於虛擬線L5與L6其中一者上。在本實施例中，導電網格構件310的排列規律與畫素陣列結構120的排列規律呈現特定關係，因此這些畫素開口區122被導電網格構件310遮蔽的面積比差異不大。舉例來說，畫素開口區122被遮蔽的比例的差異小於20%甚至是小於10%。因此，電子裝置300可以具有理想的顯示品質。These nodes 314 of the conductive mesh member 310 are connected to obtain a plurality of virtual lines L5 and L6. The virtual lines L5 are substantially parallel to each other, and the virtual lines L6 are substantially parallel to each other. The virtual line L5 extends in the first direction D1 and the virtual line L6 extends in the second direction D2. Further, the first direction D1 and the second direction D2 are parallel to the column direction R and the row direction C, respectively. Here, the virtual line L5 and the virtual line L6 are boundaries of a plurality of predetermined area areas A4. The virtual lines L5 and L6 intersect at a plurality of virtual intersections N, and each node 314 is located between two adjacent virtual intersections N. Each node 314 falls in the middle of two adjacent virtual intersections N and is located on one of the virtual lines L5 and L6. In the present embodiment, the arrangement rule of the conductive mesh members 310 and the arrangement rule of the pixel array structure 120 exhibit a specific relationship, and therefore the area ratios of the pixel opening regions 122 blocked by the conductive mesh members 310 are not much different. For example, the difference in the ratio of the shaded open areas 122 being masked is less than 20% or even less than 10%. Therefore, the electronic device 300 can have an ideal display quality.
圖7為本新型創作另一實施例的電子裝置的示意圖，而圖8為圖7的電子裝置中導電網格構件與畫素陣列結構各自獨立 的示意圖。請參照圖7與圖8，電子裝置400相似於電子裝置100，不過兩者的差異主要在於電子裝置400中，導電網格構件410的多個多邊形圖案412具有不同輪廓。FIG. 7 is a schematic diagram of an electronic device according to another embodiment of the present invention, and FIG. 8 is a diagram showing that the conductive mesh member and the pixel array structure are independent of each other in the electronic device of FIG. Schematic diagram. Referring to FIG. 7 and FIG. 8 , the electronic device 400 is similar to the electronic device 100 , but the difference between the two is mainly in the electronic device 400 . The plurality of polygonal patterns 412 of the conductive mesh member 410 have different contours.
在本實施例中，這些多邊形圖案412依據多個預定面積區A5而排列，且兩兩相連而構成多個節點414。預定面積區A5的尺寸設計與圖1的預定面積區A1相同，也就是，預定面積區A5在第一方向D1具有第一間距P1，其等於畫素開口區122在列方向R上的寬度W1，並且在第二方向D2上具有第二間距P2，其等於畫素開口區122在行方向C上的寬度W2。將導電網格構件410的這些節點414連接起來可以獲得多條虛擬線L7與L8以及多條虛擬線L9與L10，其中虛擬線L7與L8恰為預定面積區A5的邊界，而虛擬線L9與L10則為非規律排列的線。在此，虛擬線L7與虛擬線L8相互交錯而可以劃分出規律排列的多個預定面積區A5。也就是說，預定面積區A5的邊界即由虛擬線L7與虛擬線L8定義的。另外，虛擬線L7與L8相交於多個虛擬交點N，且各節點414位於相鄰兩個虛擬交點N之間。各節點414與相鄰兩個虛擬交點N之間分別相隔一第一距離d3與一第二距離d4。在此，第一距離d3不同於第二距離d4，因此多邊形圖案412為不等邊的四邊形。In the present embodiment, the polygonal patterns 412 are arranged according to a plurality of predetermined area areas A5, and are connected in pairs to form a plurality of nodes 414. The size design of the predetermined area area A5 is the same as the predetermined area area A1 of FIG. 1, that is, the predetermined area area A5 has a first pitch P1 in the first direction D1 which is equal to the width W1 of the pixel open area 122 in the column direction R. And having a second pitch P2 in the second direction D2 equal to the width W2 of the pixel open region 122 in the row direction C. The nodes 414 of the conductive mesh member 410 are connected to obtain a plurality of virtual lines L7 and L8 and a plurality of virtual lines L9 and L10, wherein the virtual lines L7 and L8 are exactly the boundary of the predetermined area area A5, and the virtual line L9 and L10 is an irregularly arranged line. Here, the virtual line L7 and the virtual line L8 are interlaced with each other to divide a plurality of predetermined area areas A5 which are regularly arranged. That is, the boundary of the predetermined area area A5 is defined by the virtual line L7 and the virtual line L8. In addition, the virtual lines L7 and L8 intersect at a plurality of virtual intersections N, and each node 414 is located between two adjacent virtual intersections N. Each node 414 and the adjacent two virtual intersections N are separated by a first distance d3 and a second distance d4, respectively. Here, the first distance d3 is different from the second distance d4, and thus the polygonal pattern 412 is an equilateral quadrangle.
由於導電網格構件410中多邊形圖案412的排列規律與畫素陣列結構120中畫素開口區122的尺寸有關，電子裝置400中畫素開口區122被導電網格構件410遮蔽的面積比例是大致相 同的。特別是，這些畫素開口區122被遮蔽的比例的差異小於20%甚至是小於10%。因此，電子裝置400可以具有理想的顯示品質。Since the arrangement regularity of the polygonal pattern 412 in the conductive mesh member 410 is related to the size of the pixel open area 122 in the pixel array structure 120, the area ratio of the pixel open area 122 in the electronic device 400 that is shielded by the conductive mesh member 410 is approximately phase The same. In particular, the difference in the ratio of these pixel open areas 122 being masked is less than 20% or even less than 10%. Therefore, the electronic device 400 can have an ideal display quality.
由前述實施例可知，導電網格構件110、210、310與410的圖案設計是依據畫素陣列結構120中畫素開口區122的尺寸與排列規律而設置的，因此導電網格構件110、210、310與410對同一個裝置中的畫素開口區122的遮蔽比例是大致均等的。特別是，在發生對位誤差的情形下，導電網格構件110、210、310與410對同一個裝置中的畫素開口區122的遮蔽比例仍是大致均等的，藉此讓電子裝置100、100A、200、300與400具有理想的顯示品質以及高製作良率。值得一提的是，前述實施例中，畫素開口區122的排列方式僅是一種範例，並非用以限定本新型創作。在其他的實施例中，畫素開口區122排列成陣列的方式可以為交錯型排列(delta arrangement)或是四畫素形排列，或是畫素開口區的尺寸大小可以不一致。此時，設計者可以根據畫素開口區的規律性決定出用來設計導電網格構件中各多邊形圖案的排列規則。另外，上述實施例中，導電網格構件的各節點都是設置於預定面積區的邊界上，但本新型創作不以此為限。It can be seen from the foregoing embodiments that the pattern design of the conductive mesh members 110, 210, 310, and 410 is set according to the size and arrangement of the pixel opening regions 122 in the pixel array structure 120, and thus the conductive mesh members 110, 210 The shielding ratios of 310 and 410 to the pixel opening area 122 in the same device are substantially equal. In particular, in the case where a registration error occurs, the shielding ratios of the conductive mesh members 110, 210, 310, and 410 to the pixel opening regions 122 in the same device are still substantially equal, thereby allowing the electronic device 100, 100A, 200, 300 and 400 have ideal display quality and high production yield. It should be noted that, in the foregoing embodiment, the arrangement of the pixel opening areas 122 is only an example, and is not intended to limit the novel creation. In other embodiments, the pixel opening regions 122 may be arranged in an array in a delta arrangement or a four-pixel arrangement, or the size of the pixel opening regions may be inconsistent. At this time, the designer can determine the arrangement rule for designing the polygonal patterns in the conductive mesh member according to the regularity of the open area of the pixel. In addition, in the above embodiment, each node of the conductive mesh member is disposed on the boundary of the predetermined area, but the novel creation is not limited thereto.
舉例而言，圖9A為本新型創作又一實施例的電子裝置，而圖9B為圖9A的電子裝置中導電網格構件的佈局示意圖。在圖9A中，電子裝置500包括一導電網格構件510以及一畫素陣列結構120，其中導電網格構件510配置於畫素陣列結構120上方。導電網格構件510包括多個多邊形圖案512，且多邊形圖案512是依 據預定面積區A6排列的。畫素陣列結構120包括排列成一陣列的多個畫素開口區122而任相鄰兩個畫素開口區122之間設有一非開口區124。以本實施例而言，預定面積區A6在第一方向D1上規律排列而具有第一間距P7，在第二方向D2上也是規律排列而具有第二間距P8。在此，第一方向D1與第二方向D2的定義相同於前述實施例的描述，並且，第一方向D1可以平行於畫素開口區122的列方向R，而第二方向D2可以平行於畫素開口區122的行方向C，但本新型創作不以此為限。在其他實施例中，第一方向D1與列方向R可以彼此相交而不相平行，不過，第一方向D1與第二方向D2之間的交角等於列方向R與行方向C的交角。For example, FIG. 9A is an electronic device according to another embodiment of the present invention, and FIG. 9B is a schematic layout view of a conductive mesh member in the electronic device of FIG. 9A. In FIG. 9A, the electronic device 500 includes a conductive mesh member 510 and a pixel array structure 120, wherein the conductive mesh member 510 is disposed above the pixel array structure 120. The conductive mesh member 510 includes a plurality of polygonal patterns 512, and the polygonal pattern 512 is According to the predetermined area area A6. The pixel array structure 120 includes a plurality of pixel opening regions 122 arranged in an array, and a non-opening region 124 is disposed between adjacent two pixel opening regions 122. In the present embodiment, the predetermined area areas A6 are regularly arranged in the first direction D1 to have a first pitch P7, and are also regularly arranged in the second direction D2 to have a second pitch P8. Here, the definitions of the first direction D1 and the second direction D2 are the same as those of the foregoing embodiment, and the first direction D1 may be parallel to the column direction R of the pixel open area 122, and the second direction D2 may be parallel to the drawing. The row direction C of the open area 122 is not limited to this. In other embodiments, the first direction D1 and the column direction R may intersect each other without being parallel, however, the angle of intersection between the first direction D1 and the second direction D2 is equal to the intersection angle of the column direction R and the row direction C.
在本實施例中，上述預定面積區A6是根據畫素開口區122的尺寸與分布設定的。舉例而言，預定面積區A6在第一方向D1的間距P7為3個畫素開口區122以及2個非開口區124在列方向R上的總寬度W7。同時，預定面積區A6在第二方向D2上的間距P8為1個畫素開口區122以及0個非開口區124在行方向C上的總寬度W8。In the present embodiment, the predetermined area area A6 is set in accordance with the size and distribution of the pixel opening area 122. For example, the pitch P7 of the predetermined area A6 in the first direction D1 is the total width W7 of the three pixel open areas 122 and the two non-open areas 124 in the column direction R. At the same time, the pitch P8 of the predetermined area area A6 in the second direction D2 is the total width W8 of the one pixel open area 122 and the zero non-open areas 124 in the row direction C.
由圖9B可知，多邊形圖案512彼此連接而構成多個節點514，其中這些節點514設置於預定面積區A6的邊界附近。具體而言，預定面積區A6各自包括一內縮預定面積區A7以及一節點設置面積區A8，其中節點設置面積區A8包圍內縮預定面積區A7，且節點514即設置於節點設置面積區A8中。也就是說，相較於前述實施例而言，本實施例中的節點514不限定要設置於預 定面積區A6的邊界上。As can be seen from FIG. 9B, the polygonal patterns 512 are connected to each other to constitute a plurality of nodes 514, wherein the nodes 514 are disposed near the boundary of the predetermined area area A6. Specifically, the predetermined area areas A6 each include a contracted predetermined area area A7 and a node set area area A8, wherein the node set area area A8 surrounds the contracted predetermined area area A7, and the node 514 is disposed in the node set area area A8. in. That is to say, compared with the foregoing embodiment, the node 514 in this embodiment is not limited to be set in the pre- On the boundary of the area A6.
具體來說，預定面積區A6在第一方向D1的間距P7與在第二方向D2上的間距P8分別等於內縮預定面積區A7在第一方向D1的間距P9與在第二方向的間距P10。也就是說，預定面積區A6與內縮預定面積區A7具有相同的間距。同時，以本實施例而言，間距P7與P9為3個畫素開口區122以及2個非開口區124在列方向R上的總寬度W7，而間距P8與P10為1個畫素開口區122以及0個非開口區124在行方向C上的總寬度W8。另外，各內縮預定面積區A7在第一方向D1上的寬度W9不小於間距P7或P9的80%，而各內縮預定面積區A7在第二方向D2上的寬度W10不小於間距P8或P10的80%。Specifically, the pitch P7 of the predetermined area A6 in the first direction D1 and the pitch P8 in the second direction D2 are respectively equal to the pitch P9 of the indented predetermined area A7 in the first direction D1 and the pitch P10 in the second direction. . That is, the predetermined area area A6 has the same pitch as the indented predetermined area area A7. Meanwhile, in the present embodiment, the pitches P7 and P9 are the total width W7 of the three pixel opening regions 122 and the two non-opening regions 124 in the column direction R, and the pitches P8 and P10 are one pixel opening region. 122 and the total width W8 of the 0 non-opening regions 124 in the row direction C. In addition, the width W9 of each of the indented predetermined area regions A7 in the first direction D1 is not less than 80% of the pitch P7 or P9, and the width W10 of each of the indented predetermined area regions A7 in the second direction D2 is not less than the pitch P8 or 80% of P10.
將節點514設置於節點設置面積區A8中，則這些節點514有至少部分不在預定面積區A6的邊界上而是在邊界附近，且不在邊界上的這些節點514至邊界的最短距離d5不大於對應的間距P7或P9的10%，或是不大於對應的間距P8或P10的10%。如此一來，多邊形圖案512的分布規律與畫素開口區122的分布相關，而使畫素開口區122被遮蔽比例是大致均等的，藉以讓電子裝置500具有理想的顯示品質。The node 514 is disposed in the node setting area A8, then the nodes 514 are at least partially not on the boundary of the predetermined area area A6 but in the vicinity of the boundary, and the shortest distance d5 of the nodes 514 to the boundary not on the boundary is not greater than the corresponding The pitch of P7 or P9 is 10%, or is not more than 10% of the corresponding pitch P8 or P10. In this way, the distribution pattern of the polygon pattern 512 is related to the distribution of the pixel opening area 122, and the mask opening area 122 is substantially equalized, so that the electronic device 500 has an ideal display quality.
以上的實施例中，導電網格構件110、210、310、410與510並不限定是具有單層的結構。在其他實施例中，以圖10A為例，導電網格構件610可包括多個子層610A與610B，子層610A與610B彼此疊置設置。子層610A由導電細線612A交錯而成， 而子層610B由導電細線612B交錯而成。當導電網格構件610應用於前述電子裝置100~500任一者時，導電細線612A與612B垂直投影至畫素陣列結構上的投影輪廓將會構成前述的多邊形圖案112、212、312、412或512。也就是說，單一子層610A的導電細線612A構成的圖案單元614A或是單一子層610B的導電細線612B構成的圖案單元614B不一定要依據畫素陣列結構中畫素開口區的尺寸與排列規律而設計，但是子層610A與子層610B疊置在一起而構成的整體輪廓可以相同於前述實施例中導電網格構件110、210、310、410與510任何一者。In the above embodiments, the conductive mesh members 110, 210, 310, 410, and 510 are not limited to have a single layer structure. In other embodiments, taking FIG. 10A as an example, the conductive mesh member 610 can include a plurality of sub-layers 610A and 610B, and the sub-layers 610A and 610B are disposed one on top of the other. The sub-layer 610A is interlaced by the conductive thin wires 612A. The sub-layer 610B is formed by interlacing the conductive thin wires 612B. When the conductive mesh member 610 is applied to any of the foregoing electronic devices 100-500, the projection profiles perpendicularly projected onto the pixel array structure by the conductive thin wires 612A and 612B will constitute the aforementioned polygonal pattern 112, 212, 312, 412 or 512. That is to say, the pattern unit 614A formed by the conductive thin line 612A of the single sub-layer 610A or the conductive thin line 612B of the single sub-layer 610B does not necessarily have to be based on the size and arrangement of the open area of the pixel in the pixel array structure. The design, but the sub-layer 610A and the sub-layer 610B are stacked together to form an overall contour which is identical to any of the conductive mesh members 110, 210, 310, 410 and 510 in the previous embodiment.
一般來說，子層610A與610B可以配置於同一基板的相對兩側，或是分別配置於不同基板上，再將兩基板貼合在一起以做為需要的構件。另外，子層610A與610B可以配置於同一基板的相同一側，並以絕緣層分隔開來。舉例而言，請參考第10B圖，第10B圖為圖10A的導電網格結構配置於同一基板同一側的剖面示意圖。在圖10B中，導電網格結構610包括子層610A與610B，子層610A與610B依序設於基板602上表面，基板602具有中央區602A與周圍區602B且基板602上另設有位於周圍區602B內的裝飾層604。此外，第一絕緣層606整面覆蓋子層600A與裝飾層604。第二絕緣層608覆蓋子層600B與第一絕緣層606，其中第一絕緣層606與第二絕緣層608的材料舉例為有機絕緣材料或無機絕緣材料(例如SiO2 或SiNx )，可以分別為單層或複合材料層。在本實施例中，第一與第二絕緣層606、608可以分別具有接 觸洞606A、608A，其中接觸洞606A、608A位於周圍區602B且可以分別曝露出子層610A的一部分與子層610B的一部分以實現兩者之間或是兩者與其他構件的電性傳導關係。Generally, the sub-layers 610A and 610B may be disposed on opposite sides of the same substrate, or respectively disposed on different substrates, and then the two substrates are bonded together to form a required member. In addition, the sub-layers 610A and 610B may be disposed on the same side of the same substrate and separated by an insulating layer. For example, please refer to FIG. 10B. FIG. 10B is a schematic cross-sectional view showing the conductive mesh structure of FIG. 10A disposed on the same side of the same substrate. In FIG. 10B, the conductive mesh structure 610 includes sub-layers 610A and 610B, and the sub-layers 610A and 610B are sequentially disposed on the upper surface of the substrate 602. The substrate 602 has a central region 602A and a surrounding region 602B, and the substrate 602 is additionally disposed around. Decorative layer 604 within region 602B. In addition, the first insulating layer 606 covers the sub-layer 600A and the decorative layer 604 over the entire surface. The second insulating layer 608 covers the sub-layer 600B and the first insulating layer 606. The materials of the first insulating layer 606 and the second insulating layer 608 are exemplified by an organic insulating material or an inorganic insulating material (for example, SiO 2 or SiN x ). It is a single layer or a composite layer. In this embodiment, the first and second insulating layers 606, 608 may have contact holes 606A, 608A, respectively, wherein the contact holes 606A, 608A are located in the peripheral region 602B and may expose a portion of the sub-layer 610A and the sub-layer 610B, respectively. Part of it is to achieve an electrical conduction relationship between the two or both.
上述實施例中的導電網格構件110、210、310、410、510與610可以根據設計者的需求而做為不同功能的構件。舉例來說，導電網格構件110、210、310、410、510與610可以整面完整地配置於畫素陣列結構上方而提供電磁波屏蔽的功能。或是，導電網格構件110、210、310、410、510與610可以經由將部分的導電細線斷開而定義出訊號獨立的多個觸控電極以提供觸控感測功能。也就是說，導電網格構件110、210、310、410、510與610可以是觸控電極層。另外，畫素陣列結構可以藉由多種方式來實現顯示功能。舉例而言，畫素陣列結構可以是有機發光畫素陣列、液晶畫素陣列、電泳畫素陣列、電濕潤畫素陣列中任何一種或多種的組合。The conductive mesh members 110, 210, 310, 410, 510, and 610 in the above embodiments may be configured as different functional components according to the needs of the designer. For example, the conductive mesh members 110, 210, 310, 410, 510, and 610 can be integrally disposed over the pixel array structure to provide electromagnetic wave shielding. Alternatively, the conductive mesh members 110, 210, 310, 410, 510, and 610 can define a plurality of signal-independent touch electrodes by disconnecting portions of the conductive thin wires to provide a touch sensing function. That is, the conductive mesh members 110, 210, 310, 410, 510, and 610 may be touch electrode layers. In addition, the pixel array structure can realize the display function in various ways. For example, the pixel array structure may be a combination of any one or more of an organic light-emitting pixel array, a liquid crystal pixel array, an electrophoretic pixel array, and an electrowetting pixel array.
更進一步而言，上述電子裝置100、100A、200、300、400與500的具體架構還可以包括基板等其他可提供支撐、承載作用的構件。舉例而言，圖11A至圖11E為本新型創作多個實施例的電子裝置的剖面示意圖。Further, the specific architecture of the electronic devices 100, 100A, 200, 300, 400, and 500 may further include other components that can provide support and load. For example, FIG. 11A to FIG. 11E are schematic cross-sectional views of an electronic device in which various embodiments are created.
請先參照圖11A，電子裝置10A包括導電網格構件20、畫素陣列結構30、第一基板40與第二基板50，其中導電網格構件20可以為前述多個實施例中導電網格構件110、210、310、410、510與610其中一者，而畫素陣列結構30為前述實施例的畫素陣 列結構120。在本實施例中，畫素陣列結構30位於第一基板40與第二基板50之間，而第一基板40位於導電網格構件20與畫素陣列結構30之間。第一基板40可為一硬式透光基板或一可撓式透光基板，其材質例如為玻璃或塑料，但不以此為限。第二基板50則可以提供支撐與保護畫素陣列結構30的功能。此時，導電網格構件20可以直接製作於第一基板40上，而畫素陣列結構30也可以有一部分構件(例如彩色濾光層與共用電極至少其中一者)製作於第一基板40上，也就是說第一基板40與配置其上的構件可以構成彩色濾光基板，但本新型創作不以此為限。另外，為了保護導電網格構件20，電子裝置10A可以進一步設置有保護層60，以覆蓋住導電網格構件20。Referring first to FIG. 11A, the electronic device 10A includes a conductive mesh member 20, a pixel array structure 30, a first substrate 40 and a second substrate 50, wherein the conductive mesh member 20 may be a conductive mesh member of the foregoing various embodiments. One of 110, 210, 310, 410, 510, and 610, and the pixel array structure 30 is the pixel array of the foregoing embodiment Column structure 120. In the present embodiment, the pixel array structure 30 is located between the first substrate 40 and the second substrate 50, and the first substrate 40 is located between the conductive mesh member 20 and the pixel array structure 30. The first substrate 40 can be a hard transparent substrate or a flexible transparent substrate, and the material thereof is, for example, glass or plastic, but is not limited thereto. The second substrate 50 can then provide the function of supporting and protecting the pixel array structure 30. At this time, the conductive mesh member 20 can be directly formed on the first substrate 40, and the pixel array structure 30 can also be formed on the first substrate 40 by a part of the components (for example, at least one of the color filter layer and the common electrode). That is, the first substrate 40 and the components disposed thereon may constitute a color filter substrate, but the novel creation is not limited thereto. In addition, in order to protect the conductive mesh member 20, the electronic device 10A may be further provided with a protective layer 60 to cover the conductive mesh member 20.
在圖11B中，電子裝置10B包括導電網格構件20、畫素陣列結構30、第一基板40、第二基板50、第三基板70與黏著層80，其中導電網格構件20可以為前述多個實施例中導電網格構件110、210、310、410、510與610其中一者，而畫素陣列結構30為前述實施例的畫素陣列結構120。電子裝置10B不同於電子裝置10A之處在於，電子裝置10B藉由黏著層80將第三基板70貼附於第一基板40，因此導電網格構件20位於第三基板70與第一基板40之間。具體來說，導電網格構件20位於黏著層80與第一基板40之間。此時，第三基板70可以是硬質透光基板以覆蓋保護下部元件，且第三基板70也可稱為覆蓋板。值得一提的是，當導電網格構件20以前述實施例的導電網格構件610來實現時，兩 個子層也可以分別製作於第一基板40與第三基板70上，而不需限定以圖10B的方式製作。In FIG. 11B, the electronic device 10B includes a conductive mesh member 20, a pixel array structure 30, a first substrate 40, a second substrate 50, a third substrate 70, and an adhesive layer 80, wherein the conductive mesh member 20 may be as described above. In one embodiment, one of the conductive mesh members 110, 210, 310, 410, 510, and 610, and the pixel array structure 30 is the pixel array structure 120 of the foregoing embodiment. The electronic device 10B is different from the electronic device 10A in that the electronic device 10B attaches the third substrate 70 to the first substrate 40 by the adhesive layer 80, and thus the conductive mesh member 20 is located on the third substrate 70 and the first substrate 40. between. Specifically, the conductive mesh member 20 is located between the adhesive layer 80 and the first substrate 40. At this time, the third substrate 70 may be a hard transparent substrate to cover the lower member, and the third substrate 70 may also be referred to as a cover plate. It is worth mentioning that when the conductive mesh member 20 is implemented by the conductive mesh member 610 of the foregoing embodiment, The sub-layers may also be formed on the first substrate 40 and the third substrate 70, respectively, without being limited to be fabricated in the manner of FIG. 10B.
在圖11C中，電子裝置10C具有的構件相同於電子裝置10B，不過電子裝置10C中黏著層80位於導電網格構件20與第一基板40之間。也就是說，圖11C的實施例是將導電網格構件20先製作於第三基板70上，再藉由黏著層80將第一基板40與第三基板70貼合在一起。值得一提的是，當導電網格構件20以前述實施例的導電網格構件610來實現時，兩個子層可以分別製作於第一基板40與第三基板70上，而不需限定以圖10B的方式製作。In FIG. 11C, the electronic device 10C has the same components as the electronic device 10B, but the adhesive layer 80 in the electronic device 10C is located between the conductive mesh member 20 and the first substrate 40. That is, in the embodiment of FIG. 11C, the conductive mesh member 20 is first formed on the third substrate 70, and the first substrate 40 and the third substrate 70 are bonded together by the adhesive layer 80. It should be noted that when the conductive mesh member 20 is implemented by the conductive mesh member 610 of the foregoing embodiment, the two sub-layers may be separately fabricated on the first substrate 40 and the third substrate 70 without limitation. The method of Fig. 10B is produced.
在圖11D中，電子裝置10D相似於電子裝置10C，不過電子裝置10D的設計是讓第三基板70與黏著層80位於導電網格構件20與第一基板40之間。此時，為了保護導電網格構件20，電子裝置10B可以進一步設置有保護層60以覆蓋導電網格構件20。在此實施例中，第三基板70可以是薄膜式基板而非前述的覆蓋板。值得一提的是，當導電網格構件20以前述實施例的導電網格構件610來實現時，兩個子層可以分別製作於第三基板70的相對兩側，而不需限定以圖10B的方式製作。In FIG. 11D, the electronic device 10D is similar to the electronic device 10C, but the electronic device 10D is designed such that the third substrate 70 and the adhesive layer 80 are located between the conductive mesh member 20 and the first substrate 40. At this time, in order to protect the conductive mesh member 20, the electronic device 10B may be further provided with a protective layer 60 to cover the conductive mesh member 20. In this embodiment, the third substrate 70 may be a film substrate instead of the aforementioned cover sheet. It should be noted that when the conductive mesh member 20 is implemented by the conductive mesh member 610 of the foregoing embodiment, the two sub-layers may be respectively fabricated on opposite sides of the third substrate 70 without being limited to FIG. 10B. Way of making.
在圖11E中，電子裝置10E除了具有電子裝置10D的所具有導電網格構件20、畫素陣列結構30、第一基板40、第二基板50、第三基板70與黏著層80外，更包括第四基板90與黏著層82，其中第四基板90藉由黏著層82貼附於第三基板70上。此時，第四基板90可以視為覆蓋板以保護下部元件，因此第四基板90為 硬質基板。值得一提的是，當導電網格構件20以前述實施例的導電網格構件610來實現時，兩個子層可以分別製作於第四基板90與第三基板70上，而不需限定以圖10B的方式製作。In FIG. 11E, the electronic device 10E includes, in addition to the conductive mesh member 20, the pixel array structure 30, the first substrate 40, the second substrate 50, the third substrate 70, and the adhesive layer 80 of the electronic device 10D. The fourth substrate 90 and the adhesive layer 82 are attached to the third substrate 70 by the adhesive layer 82. At this time, the fourth substrate 90 can be regarded as a cover plate to protect the lower member, and thus the fourth substrate 90 is Hard substrate. It should be noted that when the conductive mesh member 20 is implemented by the conductive mesh member 610 of the foregoing embodiment, the two sub-layers may be separately fabricated on the fourth substrate 90 and the third substrate 70 without limitation. The method of Fig. 10B is produced.
綜上所述，本新型創作在畫素陣列結構上方設置導電網格構件時，依據畫素陣列結構的排列規律規劃導電網格構件的圖案排列，使導電網格構件中多邊形圖案的排列規律與畫素陣列結構中畫素開口區的排列規律呈現一定的關係。如此一來，電子裝置的顯示效果不因畫素陣列結構上方的導電網格構件而變得不均勻。換言之，電子裝置具有理想的顯示效果。In summary, when the conductive mesh member is arranged above the pixel array structure, the pattern arrangement of the conductive mesh members is planned according to the arrangement rule of the pixel array structure, so that the arrangement pattern of the polygonal patterns in the conductive mesh member is The arrangement rule of the open area of the pixel in the pixel array structure has a certain relationship. As a result, the display effect of the electronic device does not become uneven due to the conductive mesh member above the pixel array structure. In other words, the electronic device has an ideal display effect.
100‧‧‧電子裝置100‧‧‧Electronic devices
110‧‧‧導電網格構件110‧‧‧Conductive mesh components
112‧‧‧多邊形圖案112‧‧‧Polygonal pattern
114‧‧‧節點114‧‧‧ nodes
116‧‧‧細線116‧‧‧ Thin line
118‧‧‧開口118‧‧‧ openings
120‧‧‧畫素陣列結構120‧‧‧ pixel array structure
122、122A、122B‧‧‧畫素開口區122, 122A, 122B‧‧‧ pixel open area
124‧‧‧非開口區124‧‧‧Non-open area
A1‧‧‧預定面積區A1‧‧‧Scheduled area
C‧‧‧行方向C‧‧‧ directions
D1、D2‧‧‧方向D1, D2‧‧‧ direction
d1、d2‧‧‧距離D1, d2‧‧‧ distance
L1、L2‧‧‧虛擬線L1, L2‧‧‧ virtual line
N‧‧‧虛擬交點N‧‧‧ virtual intersection
P1、P2‧‧‧間距P1, P2‧‧‧ spacing
R‧‧‧列方向R‧‧‧ direction
W‧‧‧線寬W‧‧‧Line width
W1、W2‧‧‧寬度W1, W2‧‧‧ width
Claims (28)
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| US201461925654P | 2014-01-10 | 2014-01-10 |
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| TWM494965U true TWM494965U (en) | 2015-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW103201708U TWM494965U (en) | 2014-01-10 | 2014-01-27 | Electronic device |
| TW103102971A TW201528080A (en) | 2014-01-10 | 2014-01-27 | Electronic device |
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| TW103102971A TW201528080A (en) | 2014-01-10 | 2014-01-27 | Electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106990868A (en) * | 2017-02-21 | 2017-07-28 | 友达光电股份有限公司 | Touch control display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI611324B (en) * | 2016-05-12 | 2018-01-11 | 敦泰電子有限公司 | Touch electrode structure |
| US10535499B2 (en) * | 2017-11-03 | 2020-01-14 | Varian Semiconductor Equipment Associates, Inc. | Varied component density for thermal isolation |
-
2014
- 2014-01-27 TW TW103201708U patent/TWM494965U/en not_active IP Right Cessation
- 2014-01-27 TW TW103102971A patent/TW201528080A/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106990868A (en) * | 2017-02-21 | 2017-07-28 | 友达光电股份有限公司 | Touch control display device |
| TWI616790B (en) * | 2017-02-21 | 2018-03-01 | 友達光電股份有限公司 | Touch Display Device |
| CN106990868B (en) * | 2017-02-21 | 2020-04-07 | 友达光电股份有限公司 | Touch control display device |
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