TWM493129U - Pixel units and driving circuits - Google Patents
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本創作涉及一種畫素單元及驅動電路,特别是涉及一種發光元件的畫素單元及驅動電路。The present invention relates to a pixel unit and a driving circuit, and more particularly to a pixel unit and a driving circuit of a light emitting element.
現今,利用如發光二極體(LED)和有機發光二極體(OLED)之發光元件作為光源,已是相當普遍的應用。而發光元件的亮度是根據流過其上的驅動電流來決定,因此,對於一用以驅動發光元件的驅動電路來說,其中,用以產生驅動電流之電晶體的特性,往往對發光元件的發光性能有最大的影響。Nowadays, the use of light-emitting elements such as light-emitting diodes (LEDs) and organic light-emitting diodes (OLEDs) as light sources has become a fairly common application. The brightness of the light-emitting element is determined according to the driving current flowing therethrough. Therefore, for a driving circuit for driving the light-emitting element, the characteristics of the transistor for generating the driving current are often for the light-emitting element. Luminescence performance has the greatest impact.
因為製程上會有均勻性問題,使得由複數發光元件與對應的驅動電路所組成的面板,其中,每個用於產生驅動電流之電晶體的臨界電壓都不相同,導致驅動電流有差異。此外,隨著長時間的操作與使用,每個用於產生驅動電流的電晶體會有不同程度的劣化現象,也使得臨界電壓的偏移程度不一致,也導致驅動電流有差異。這些都會造成在相同的資料輸入下,卻產生不相等的驅動電流,而使得由這些發光元件與對應的驅動電路所組成的面板呈現亮度不均或烙印的現象。Because there is a problem of uniformity in the process, a panel composed of a plurality of light-emitting elements and corresponding driving circuits, wherein the threshold voltages of the transistors for generating the driving current are different, resulting in a difference in driving current. In addition, with long-term operation and use, each of the transistors for generating the driving current has different degrees of deterioration, and the degree of offset of the threshold voltage is also inconsistent, which also causes a difference in driving current. These will cause unequal drive currents under the same data input, and the panel composed of these light-emitting elements and corresponding drive circuits will exhibit uneven brightness or branding.
本創作的目的在於提供一種不受驅動電晶體之 臨界電壓影響的畫素單元及驅動電路。The purpose of this creation is to provide an unactuated transistor The pixel unit and the driving circuit affected by the threshold voltage.
本創作畫素單元包含一驅動電路及具有一第一端及一第二端的一發光元件。驅動電路包括一第一電晶體、一第一開關、一電容器、及一控制模組。The created pixel unit includes a driving circuit and a light emitting element having a first end and a second end. The driving circuit includes a first transistor, a first switch, a capacitor, and a control module.
第一電晶體包括一第一端、一第二端、及一控制端。第一開關包括電連接一第一電源電壓的一第一端、電連接第一電晶體之控制端的一第二端、及接收一第一控制信號的一控制端,且根據第一控制信號的控制,決定是否輸出第一電源電壓至第一電晶體之控制端。電容器電連接第一電晶體之控制端與第二端間。The first transistor includes a first end, a second end, and a control end. The first switch includes a first end electrically connected to a first power voltage, a second end electrically connected to the control end of the first transistor, and a control end receiving a first control signal, and according to the first control signal Control determines whether to output the first power voltage to the control terminal of the first transistor. The capacitor is electrically connected between the control end of the first transistor and the second end.
控制模組電連接於第一電晶體的第二端與發光元件的第一端間,且接收一資料電壓及第一控制信號,並至少根據第一控制信號的控制,決定是否產生相關於資料電壓且經過第一電晶體的一參考電流,使第一電晶體的控制端及第二端間的跨壓相關於參考電流。第一電晶體根據其控制端及第二端間的跨壓來產生與參考電流大小相等之一驅動電流。The control module is electrically connected between the second end of the first transistor and the first end of the light emitting component, and receives a data voltage and a first control signal, and determines whether the data is generated according to at least the control of the first control signal The voltage passes through a reference current of the first transistor such that the voltage across the control terminal and the second terminal of the first transistor is related to the reference current. The first transistor generates a driving current equal to the magnitude of the reference current according to the voltage across the control terminal and the second terminal.
本創作藉由控制模組至少根據第一控制信號,產生相關於資料電壓的驅動電流,而不受驅動電晶體(即第一電晶體)之臨界電壓的影響。The present invention generates a driving current related to the data voltage by the control module based on at least the first control signal, without being affected by the threshold voltage of the driving transistor (ie, the first transistor).
701~710‧‧‧驅動電路701~710‧‧‧ drive circuit
801~810‧‧‧控制模組801~810‧‧‧Control Module
901~910‧‧‧發光元件901~910‧‧‧Lighting elements
C1‧‧‧電容器C1‧‧‧ capacitor
Data‧‧‧資料電壓Data‧‧‧data voltage
IREF‧‧‧參考電流IREF‧‧‧reference current
P1‧‧‧補償階段P1‧‧‧Compensation phase
P2‧‧‧發光階段P2‧‧‧Lighting stage
S1‧‧‧第一控制信號S1‧‧‧ first control signal
S2‧‧‧第二控制信號S2‧‧‧ second control signal
SW1‧‧‧第一開關SW1‧‧‧ first switch
SW2‧‧‧第二開關SW2‧‧‧second switch
SW3‧‧‧第三開關SW3‧‧‧ third switch
T1‧‧‧第一電晶體T1‧‧‧first transistor
T2‧‧‧第二電晶體T2‧‧‧second transistor
VDD‧‧‧第一電源電壓VDD‧‧‧first supply voltage
VL‧‧‧參考電壓VL‧‧‧reference voltage
VSS‧‧‧第二電源電壓VSS‧‧‧second supply voltage
圖1是一電路示意圖,說明本創作畫素單元之一第一較佳實施例;圖2是一時序圖,輔助圖1說明第一較佳實施例;圖3是一電路示意圖,說明第一較佳實施例在一補償階段的態樣;圖4是一電路示意圖,說明第一較佳實施例在一發光階段的態樣;圖5是一電路示意圖,說明本創作畫素單元之一第二較佳實施例;圖6是一時序圖,輔助圖5說明第二較佳實施例;圖7是一電路示意圖,說明本創作畫素單元之一第三較佳實施例;圖8是一時序圖,輔助圖7說明第三較佳實施例;圖9是一電路示意圖,說明本創作畫素單元之一第四較佳實施例;圖10是一時序圖,輔助圖9說明該四較佳實施例;圖11是一電路示意圖,說明本創作畫素單元之一第五較佳實施例;圖12是一時序圖,輔助圖11說明第五較佳實施例;圖13是一電路示意圖,說明本創作畫素單元之一第六較佳實施例;圖14是一時序圖,輔助圖13說明第六較佳實施例; 圖15是一電路示意圖,說明本創作畫素單元之一第七較佳實施例;圖16是一時序圖,輔助圖15說明第七較佳實施例;圖17是一電路示意圖,說明本創作畫素單元之一第八較佳實施例;圖18是一時序圖,輔助圖17說明第八較佳實施例;圖19是一電路示意圖,說明本創作畫素單元之一第九較佳實施例;圖20是一時序圖,輔助圖19說明第九較佳實施例;圖21是一電路示意圖,說明本創作畫素單元之一第十較佳實施例;及圖22是一時序圖,輔助圖21說明第十較佳實施例。1 is a circuit diagram showing a first preferred embodiment of the present pixel unit; FIG. 2 is a timing diagram, and FIG. 1 is a first preferred embodiment; FIG. 3 is a circuit diagram illustrating the first The preferred embodiment is in a compensation stage; FIG. 4 is a circuit diagram illustrating the first preferred embodiment in an illumination stage; FIG. 5 is a circuit diagram illustrating one of the present pixel units. 2 is a timing chart, and FIG. 6 is a second preferred embodiment; FIG. 7 is a circuit diagram showing a third preferred embodiment of the present pixel unit; FIG. FIG. 9 is a circuit diagram illustrating a fourth preferred embodiment of the present pixel unit; FIG. 10 is a timing diagram, and FIG. 9 illustrates the four comparisons. FIG. 11 is a circuit diagram showing a fifth preferred embodiment of the present pixel unit; FIG. 12 is a timing diagram, and FIG. 11 is a fifth preferred embodiment; FIG. 13 is a circuit diagram. , a sixth preferred embodiment of the present pixel unit; FIG. 14 Is a timing diagram, and FIG. 13 illustrates a sixth preferred embodiment; Figure 15 is a circuit diagram showing a seventh preferred embodiment of the present pixel unit; Figure 16 is a timing diagram, and Figure 15 is a seventh preferred embodiment; Figure 17 is a circuit diagram illustrating the creation An eighth preferred embodiment of the pixel unit; FIG. 18 is a timing diagram, and FIG. 17 is a first preferred embodiment; FIG. 19 is a circuit diagram illustrating a ninth preferred embodiment of the present pixel unit. 20 is a timing chart, and FIG. 19 is a ninth preferred embodiment; FIG. 21 is a circuit diagram showing a tenth preferred embodiment of the present pixel unit; and FIG. 22 is a timing chart. The auxiliary diagram 21 illustrates the tenth preferred embodiment.
參閱圖1,本創作畫素單元之一第一較佳實施例,包含一發光元件901及一驅動電路701,發光元件901具有一第一端一第二端,驅動電路701包括一第一電晶體T1、一第一開關SW1、一電容器C1、及一控制模組801。Referring to FIG. 1, a first preferred embodiment of the present pixel unit includes a light-emitting element 901 and a driving circuit 701. The light-emitting element 901 has a first end and a second end, and the driving circuit 701 includes a first electric circuit. The crystal T1, a first switch SW1, a capacitor C1, and a control module 801.
第一電晶體T1包括接收一第一電源電壓VDD的一第一端、一第二端、及一控制端,定義A、B點分別為第一電晶體T1的控制端與第二端。第一開關SW1包括電連接第一電源電壓VDD的一第一端、電連接第一電晶體T1之控制端的一第二端、及接收一第一控制信號S1(N)的一控制端,且根據第一控制信號S1(N)的控制,決定是否輸出第一電源電壓VDD至第一 電晶體T1之控制端。其中,在由本創作之複數個畫素單元所組成的陣列的顯示面板中,N表示顯示面板中的任一列,例如:第一控制信號S1(2)表示第二列的第一控制信號。電容器C1電連接第一電晶體T1之控制端與第二端間。發光元件901的第二端接收一第二電源電壓VSS。The first transistor T1 includes a first end, a second end, and a control end for receiving a first power supply voltage VDD. The A and B points are defined as a control end and a second end of the first transistor T1, respectively. The first switch SW1 includes a first end electrically connected to the first power voltage VDD, a second end electrically connected to the control end of the first transistor T1, and a control end receiving a first control signal S1(N), and Determining whether to output the first power voltage VDD to the first according to the control of the first control signal S1(N) The control terminal of the transistor T1. Wherein, in the display panel of the array consisting of the plurality of pixel units of the present creation, N represents any column in the display panel, for example, the first control signal S1(2) represents the first control signal of the second column. The capacitor C1 is electrically connected between the control end and the second end of the first transistor T1. The second end of the light emitting element 901 receives a second power voltage VSS.
控制模組801電連接於第一電晶體T1的第二端與發光元件 901的第一端間,且接收一資料電壓Data及第一控制信號S1(N),並至少根據第一控制信號S1(N)的控制,決定是否產生一相關於資料電壓Data且經過第一電晶體T1的參考電流,使第一電晶體T1的控制端及第二端間的跨壓相關於參考電流,第一電晶體T1根據其控制端及第二端間的跨壓來產生與參考電流大小相等之驅動電流。The control module 801 is electrically connected to the second end of the first transistor T1 and the light emitting element Between the first end of the 901, and receiving a data voltage Data and a first control signal S1 (N), and at least according to the control of the first control signal S1 (N), determining whether to generate a data voltage related to Data and passing through the first The reference current of the transistor T1 is such that the voltage across the control terminal and the second terminal of the first transistor T1 is related to the reference current, and the first transistor T1 is generated and referenced according to the voltage across the control terminal and the second terminal. A drive current of equal magnitude.
控制模組801包括一第二開關SW2、一第二電晶體T2、及一 第三開關SW3。第二開關SW2具有電連接第一電晶體T1之第二端的一第一端、一第二端、及接收第一控制信號S1(N)的一控制端,且根據第一控制信號S1(N)的控制,於導通與不導通間切換。第二電晶體T2具有分別電連接第二開關SW2之第二端的一第一端與一控制端,及接收資料電壓Data的一第二端。第三開關SW3具有電連接第一電晶體T1之第二端的一第一端、電連接發光元件901之第一端的一第二端、及接收一第二控制信號S2(N)的一控制端,且根據第二控制信號S2(N)的控制,以決定是否將來自第一電晶體T1的驅動電流輸出到發光元件901。The control module 801 includes a second switch SW2, a second transistor T2, and a The third switch SW3. The second switch SW2 has a first end electrically connected to the second end of the first transistor T1, a second end, and a control end receiving the first control signal S1(N), and according to the first control signal S1 (N Control, switching between conduction and non-conduction. The second transistor T2 has a first end and a control end electrically connected to the second end of the second switch SW2, and a second end receiving the data voltage Data. The third switch SW3 has a first end electrically connected to the second end of the first transistor T1, a second end electrically connected to the first end of the light emitting element 901, and a control for receiving a second control signal S2(N) And, according to the control of the second control signal S2(N), to determine whether to output the driving current from the first transistor T1 to the light-emitting element 901.
在本實施例中,發光元件901為有機發光二極體,且第一電 晶體T1、第二電晶體T2、第一開關SW1、第二開關SW2、及第三開關SW3可以用任何N型電晶體(NMOS)來實現。In this embodiment, the light emitting element 901 is an organic light emitting diode, and the first electricity The crystal T1, the second transistor T2, the first switch SW1, the second switch SW2, and the third switch SW3 can be implemented by any N-type transistor (NMOS).
圖2是一時序圖,輔助圖1說明第一較佳實施例。畫素單元 根據第一及第二控制信號S1(N)、S2(N),在一補償階段P1及一發光階段P2操作,且為方便說明在以下圖示中以畫叉符號代表開關或電晶體不導通。Fig. 2 is a timing chart, and Fig. 1 illustrates a first preferred embodiment. Pixel unit According to the first and second control signals S1(N), S2(N), operating in a compensation phase P1 and an illumination phase P2, and for convenience of description, in the following illustration, the symbol is represented by a fork symbol or the transistor is not conductive. .
圖3是一電路示意圖,說明第一較佳實施例在補償階段P1的態樣。參閱圖2與圖3,在補償階段P1時,第一控制信號S1(N)為邏輯高準位,使第一與第二開關SW1、SW2導通,A點的電壓VA 為VDD。第二控制信號S2(N)為邏輯低準位,使第三開關SW3不導通。第二電晶體T2依據其控制端與第二端的跨壓VGS,2 產生相關於資料電壓Data_N的參考電流IREF ,並且使得參考電流IREF 的大小與一經過第一電晶體T1之電流I1 及一經過第二電晶體T2之電流I2 的大小相等(即I REF =I 1 =I 2 )。電容器C1儲存第一電晶體T1之控制端與第二端的跨壓VGS,1 。電流I1 和I2 的公式如下所示:I 2 =K (V GS ,2 -V TH ,2 )2 =K (V GS ,1 -V TH ,1 )2 =I 1 ---公式一其中,K為電晶體常數,VTH,1 為第一電晶體T1之臨界電壓,VTH,2 為第二電晶體T2之臨界電壓。在本實施例中,由公式一推導可得:V GS ,2 -V TH ,2 =V GS ,1 -V TH ,1 ---公式二由公式二推導可得:V GS ,1 =V GS ,2 -V TH ,2 +V TH ,1 ---公式三由於VGS,1 為A點的電壓VA 減去B點的電壓VB (即V GS ,1 =V A -V B ),在補償階段P1時,電壓VA 為VDD,將電壓VA 和電壓VB 帶公式二,可以得到下式:V GS ,2 -V TH ,2 =V A -V B -V TH ,1 =VDD -V B -V TH ,1 ---公式四由公式四推導可得:V B =-V GS ,2 +V TH ,2 +VDD -V TH ,1 。Figure 3 is a circuit diagram illustrating the aspect of the first preferred embodiment in the compensation phase P1. Referring to FIG. 2 and FIG. 3, in the compensation phase P1, the first control signal S1(N) is at a logic high level, and the first and second switches SW1 and SW2 are turned on, and the voltage V A at the point A is VDD. The second control signal S2(N) is at a logic low level, so that the third switch SW3 is not turned on. The second transistor T2 which is based on cross voltage V GS of the control terminal and the second terminal, generating 2 related to reference current I REF voltage Data_N data, and so the magnitude of the reference current I REF and a current through the first transistor T1 of the I 1 and a current I 2 passing through the second transistor T2 are equal in magnitude (i.e., I REF = I 1 = I 2 ). The capacitor C1 stores the voltage across the control terminal and the second terminal V GS,1 of the first transistor T1. The equations for currents I 1 and I 2 are as follows: I 2 = K ( V GS , 2 - V TH , 2 ) 2 = K ( V GS , 1 - V TH , 1 ) 2 = I 1 ---Formula 1 Where K is the transistor constant, V TH, 1 is the threshold voltage of the first transistor T1, and V TH, 2 is the threshold voltage of the second transistor T2. In this embodiment, we derive from Equation 1 that V GS , 2 - V TH , 2 = V GS , 1 - V TH , 1 --- Equation 2 is derived from Equation 2: V GS , 1 = V GS , 2 - V TH , 2 + V TH , 1 --- Equation 3 Since V GS, 1 is the voltage V A at point A minus the voltage V B at point B (ie V GS , 1 = V A - V B In the compensation phase P1, the voltage V A is VDD, and the voltage V A and the voltage V B are given by the formula 2, and the following equation can be obtained: V GS , 2 - V TH , 2 = V A - V B - V TH , 1 = VDD - V B - V TH , 1 --- Equation 4 is derived from Equation 4: V B =- V GS , 2 + V TH , 2 + VDD - V TH ,1 .
圖4是一電路示意圖,說明第一較佳實施例在發光階段P2的 態樣。參閱圖2與圖4,在發光階段P2時,第一控制信號S1(N)為邏輯低準位,使第一與第二開關SW1、SW2不導通。第二控制信號S2(N)為邏輯高準位,使第三開關SW3導通。此時,B點的電壓VB' 為VSS+VDRIVE ,VDRIVE 為發光元件901的導通電壓。因為電容器C1儲存跨壓VGS,1 ,使得第一電晶體T1在發光階段P2的跨壓V GS ,1 '相等於第一電晶體T1在補償階段P1時的跨壓VGS,1 。其作用原理為,電容器C1將B點的電壓變化△V B 耦合至A點,因此,A點在發光階段P2的電壓VA' 可表示為:V A '=V A +△V B =VDD +△V B ---公式五其中,B點的電壓變化△V B 可表示為:△V B =V B '-V B =VSS +V DRIVE -V B ---公式六將公式六帶入公式五後可得:V A '=VDD +VSS +V DRIVE -V B 。Figure 4 is a circuit diagram showing the aspect of the first preferred embodiment in the illumination phase P2. Referring to FIG. 2 and FIG. 4, in the light-emitting phase P2, the first control signal S1(N) is at a logic low level, so that the first and second switches SW1, SW2 are not turned on. The second control signal S2(N) is at a logic high level to turn on the third switch SW3. At this time, the voltage V B ' at point B is VSS+V DRIVE , and V DRIVE is the on-voltage of the light-emitting element 901. Because the voltage across the storage capacitor C1 is V GS, 1, such that a first transistor T1 P2 stage in emission cross voltage V GS, 1 'is equal to a first transistor T1 cross voltage V GS at the compensation stage P1, 1. Its mechanism of capacitor C1 the point B of the voltage variation △ V B is coupled to a point A, therefore, the point A in the emission phase P2, the voltage V A 'may be expressed as: V A' = V A + △ V B = VDD +△ V B ---Formula 5 where the voltage change at point B Δ V B can be expressed as: △ V B = V B '- V B = VSS + V DRIVE - V B --- Equation 6 will formula six After entering Equation 5, you can get: V A '= VDD + VSS + V DRIVE - V B .
由於跨壓V GS ,1 '為A點的電壓VA' 減去B點的電壓VB' (即V GS ,1 '=V A '-V B '),將電壓VA' 和電壓VB' 的值代入,化簡後可以得到下式:V GS ,1 '=VDD -V B ---公式七將電壓VB 的值代入公式七,化簡後可以得到下式:V GS ,1 '=V GS ,2 -V TH ,2 +V TH ,1 ---公式八由公式三和公式八可以證明,第一電晶體T1在發光階段P2的跨壓VGS,1' 相等於第一電晶體T1在補償階段P1時的跨壓VGS,1 。Due to the voltage across the V GS , 1 ' is the voltage V A ' at point A minus the voltage V B ' at point B (ie V GS , 1 '= V A '- V B '), the voltage V A ' and the voltage V Substituting the value of B' , after simplification, the following formula can be obtained: V GS , 1 '= VDD - V B --- Equation 7 Substituting the value of voltage V B into formula VII, the following formula can be obtained: V GS , 1 '= V GS , 2 - V TH , 2 + V TH , 1 --- Equation 8 From Equation 3 and Equation 8, it can be proved that the voltage across the first transistor T1 in the illuminating phase P2 is equal to V GS,1' The voltage across the first transistor T1 at the compensation phase P1 is V GS,1 .
第一電晶體T1根據跨壓VGS,1' 產生驅動電流IDRIVE ,驅動電流IDRIVE 經由導通的第三開關SW3供應發光元件901。驅動電流IDRIVE 可以由以下公式推導:I DRIVE =K (V GS ,1 '-V TH ,1 )2 =K (V GS ,2 -V TH ,2 +V TH ,1 -V TH ,1 )2 =K (V GS ,2 -V TH ,2 )2 =I 1 =I REF ---公式九由公式九可知,驅動電流IDRIVE 和參考電流IREF 的大小相等,且相關於第二電晶體T2在補償階段P1時的跨壓VGS,2 與臨界電壓VTH,2 的差值。又第二電晶體T2在補償階段P1時之第二端電壓為資料電壓Data_N,因此,驅動電流IDRIVE 與資料電壓Data_N有關,但驅動電流IDRIVE 與第一電晶體的臨界電壓VTH,1 無關。The first transistor T1 generates a drive current I DRIVE according to the voltage across the voltage V GS, 1 ' , and the drive current I DRIVE is supplied to the light-emitting element 901 via the turned-on third switch SW3. The drive current I DRIVE can be derived from the following formula: I DRIVE = K ( V GS , 1 '- V TH , 1 ) 2 = K ( V GS , 2 - V TH , 2 + V TH , 1 - V TH , 1 ) 2 = K ( V GS , 2 - V TH , 2 ) 2 = I 1 = I REF --- Equation 9 From Equation 9, the drive current I DRIVE and the reference current I REF are equal in magnitude and related to the second The difference between the voltage V GS,2 of the crystal T2 at the compensation phase P1 and the threshold voltage V TH,2 . The second terminal voltage of the second transistor T2 in the compensation phase P1 is the data voltage Data_N. Therefore, the driving current I DRIVE is related to the data voltage Data_N, but the driving current I DRIVE and the threshold voltage V TH,1 of the first transistor. Nothing.
與習知技術相比,本創作藉由第二電晶體T2產生參考電流 IREF ,並且使驅動電流IDRIVE 相等於參考電流IREF ,使得驅動電流IDRIVE 與第一電晶體T1之臨界電壓VTH,1 無關,也就不會因為第一電晶體T1之製程的均勻性問題,使得不同畫素單元之第一電晶體T1的臨界電壓VTH,1 不同,導致在相同資料電壓Data時,卻有驅動電流IDRIVE 不相等的現象,進而改善由畫素單元所組成的面板之亮度不均或烙印的問題。Compared with the prior art, the present invention generates the reference current I REF by the second transistor T2 and makes the driving current I DRIVE equal to the reference current I REF such that the driving current I DRIVE and the threshold voltage V of the first transistor T1 TH, 1 is irrelevant, so that the threshold voltage V TH,1 of the first transistor T1 of different pixel units is different due to the uniformity of the process of the first transistor T1, resulting in the same data voltage Data, there drive current I dRIVE unequal phenomenon, thereby improving unevenness in brightness of the panel by the pixel units consisting of mark or question.
在以下的各實施例中,為說明方便起見,未在圖上畫出參 考電流IREF 及驅動電流IDRIVE ,但參考電流IREF 及驅動電流IDRIVE 的定義分別如圖3和圖4所示。In the following embodiments, for convenience of description, the reference current I REF and the drive current I DRIVE are not shown in the figure, but the definitions of the reference current I REF and the drive current I DRIVE are respectively shown in FIGS. 3 and 4 . Show.
參閱圖5,本創作畫素單元之第二較佳實施例,大致上是與 第一較佳實施例相似,不同的地方在於:控制模組802之第二電晶體T2具有電連接第二開關SW2之第二端的一第一端、接收資料電壓Data的一控制端、及接收一第二控制信號S2(N)的一第二端。Referring to FIG. 5, a second preferred embodiment of the present pixel unit is substantially The first preferred embodiment is similar in that the second transistor T2 of the control module 802 has a first end electrically connected to the second end of the second switch SW2, a control terminal receiving the data voltage Data, and receiving a second end of the second control signal S2(N).
圖6是一時序圖,輔助圖5說明第二較佳實施例。參閱圖5與 圖6,利用與第一較佳實施例相似的推導可知,在發光階段P2時的驅動電流 IDRIVE 相等於在補償階段的參考電流IREF ,並且,驅動電流IDRIVE 可表示為:I DRIVE =I REF =K (V GS ,2 -V TH ,2 )2 ---公式十其中,第二電晶體T2在補償階段P1時的跨壓VGS,2 與資料電壓Data_N相關。由公式十可知,驅動電流IDRIVE 與資料電壓Data_N有關,但驅動電流IDRIVE 與第一電晶體的臨界電壓VTH,1 無關,具有與第一較佳實施例相同的優點。Fig. 6 is a timing chart, and Fig. 5 illustrates a second preferred embodiment. Referring to FIG. 5 and FIG. 6, with the similar derivation from the first preferred embodiment, the driving current I DRIVE in the lighting phase P2 is equal to the reference current IREF in the compensation phase, and the driving current I DRIVE can be expressed as: I DRIVE = I REF = K ( V GS , 2 - V TH , 2 ) 2 --- Equation 10 The voltage across the voltage V GS,2 of the second transistor T2 during the compensation phase P1 is related to the data voltage Data_N. As can be seen from the equation 10, the drive current I DRIVE is related to the data voltage Data_N, but the drive current I DRIVE is independent of the threshold voltage V TH,1 of the first transistor, and has the same advantages as the first preferred embodiment.
參閱圖7,本創作畫素單元之第三較佳實施例,大致上是與第一較佳實施例相似,不同的地方在於:控制模組803之第二電晶體T2具有電連接第二開關SW2之第二端的一第一端、接收資料電壓Data的一控制端、及接收相鄰之另一列的第一控制信號S1(N+1)的一第二端。Referring to FIG. 7, a third preferred embodiment of the present pixel unit is substantially similar to the first preferred embodiment. The difference is that the second transistor T2 of the control module 803 has an electrical connection to the second switch. A first end of the second end of the SW2, a control end receiving the data voltage Data, and a second end receiving the first control signal S1(N+1) of the adjacent another column.
圖8是一時序圖,輔助圖7說明第三較佳實施例。參閱圖7與圖8,利用與第一較佳實施例相似的推導可知,在發光階段P2時的驅動電流IDRIVE 相等於在補償階段的參考電流IREF ,並且,驅動電流IDRIVE 可表示為:I DRIVE =I REF =K (V GS ,2 -V TH ,2 )2 ………公式十一其中,第二電晶體T2在補償階段P1時的跨壓VGS,2 與資料電壓DATA_N相關。由公式十一可知,驅動電流IDRIVE 與資料電壓DATA_N有關,但驅動電流IDRIVE 與第一電晶體的臨界電壓VTH,1 無關,具有與第一較佳實施例相同的優點。Fig. 8 is a timing chart, and Fig. 7 illustrates a third preferred embodiment. Referring to FIG. 7 and FIG. 8, with the similar derivation from the first preferred embodiment, the driving current I DRIVE in the lighting phase P2 is equal to the reference current I REF in the compensation phase, and the driving current I DRIVE can be expressed as : I DRIVE = I REF = K ( V GS , 2 - V TH , 2 ) 2 ......... Equation 11 where the voltage across the voltage V GS,2 of the second transistor T2 during the compensation phase P1 is related to the data voltage DATA_N . As can be seen from Equation 11, the drive current I DRIVE is related to the data voltage DATA_N, but the drive current I DRIVE is independent of the threshold voltage V TH,1 of the first transistor, and has the same advantages as the first preferred embodiment.
參閱圖9,本創作畫素單元之第四較佳實施例,大致上是與第一較佳實施例相似,不同的地方在於:控制模組804之第二電晶體T2具有電連接第二開關SW2之第二端的一第一端、接收資料電壓Data的一控制端、及接收一參考電壓VL的一第二端。Referring to FIG. 9, a fourth preferred embodiment of the present pixel unit is substantially similar to the first preferred embodiment. The difference is that the second transistor T2 of the control module 804 has an electrical connection to the second switch. A first end of the second end of the SW2, a control end receiving the data voltage Data, and a second end receiving a reference voltage VL.
圖10是一時序圖,輔助圖9說明第四較佳實施例。參閱圖9 與圖10,利用與第一較佳實施例相似的推導可知,在發光階段P2時,驅動電流IDRIVE 相等於在補償階段的參考電流IREF ,並且,驅動電流IDRIVE 可表示為:I DRIVE =I REF =K (V GS ,2 -V TH ,2 )2 ………公式十二其中,第二電晶體T2在補償階段P1時的跨壓VGS,2 與資料電壓DATA_N相關。由公式十二可知,驅動電流IDRIVE 與資料電壓DATA_N有關,但驅動電流IDRIVE 與第一電晶體的臨界電壓VTH,1 無關,具有與第一較佳實施例相同的優點。Fig. 10 is a timing chart, and Fig. 9 illustrates a fourth preferred embodiment. Referring to FIG. 9 and FIG. 10, with the similar derivation from the first preferred embodiment, in the lighting phase P2, the driving current I DRIVE is equal to the reference current I REF in the compensation phase, and the driving current I DRIVE can be expressed as : I DRIVE = I REF = K ( V GS , 2 - V TH , 2 ) 2 ... Equation 12 where the voltage across the voltage V GS,2 of the second transistor T2 during the compensation phase P1 is related to the data voltage DATA_N . It can be seen from Equation 12 that the drive current I DRIVE is related to the data voltage DATA_N, but the drive current I DRIVE has the same advantages as the first preferred embodiment regardless of the threshold voltage V TH,1 of the first transistor.
參閱圖11,本創作畫素單元之第五較佳實施例,大致上是與第一較佳實施例相似,不同的地方在於:控制模組805之第三開關SW3為一P型電晶體(PMOS),並具有電連接第一電晶體T1之第二端的一第一端、電連接發光元件905之第一端的一第二端、及接收第一控制信號S1(N)的一控制端,且根據第一控制信號S1(N)的控制,以決定是否將來自第一電晶體T1的驅動電流輸出到發光元件905。Referring to FIG. 11, a fifth preferred embodiment of the present pixel unit is substantially similar to the first preferred embodiment. The difference is that the third switch SW3 of the control module 805 is a P-type transistor ( a PMOS) having a first end electrically connected to the second end of the first transistor T1, a second end electrically connected to the first end of the light emitting element 905, and a control end receiving the first control signal S1(N) And according to the control of the first control signal S1(N), to decide whether to output the driving current from the first transistor T1 to the light-emitting element 905.
圖12是一時序圖,輔助圖11說明第五較佳實施例。參閱圖11與圖12,在補償階段P1時,第一控制信號S1(N)為邏輯高準位,使第一與第二開關SW1、SW2導通,並使第三開關SW3不導通。在發光階段P2時,第一控制信號S1(N)為邏輯低準位,使第一與第二開關SW1、SW2不導通,並使第三開關SW3導通。Fig. 12 is a timing chart, and Fig. 11 illustrates a fifth preferred embodiment. Referring to FIG. 11 and FIG. 12, in the compensation phase P1, the first control signal S1(N) is at a logic high level, the first and second switches SW1, SW2 are turned on, and the third switch SW3 is not turned on. In the light-emitting phase P2, the first control signal S1(N) is at a logic low level, so that the first and second switches SW1, SW2 are not turned on, and the third switch SW3 is turned on.
參閱圖13,本創作畫素單元之第六較佳實施例,大致上是與第三較佳實施例相似,不同的地方在於:控制模組806之第三開關SW3為一P型電晶體(PMOS),並具 有電連接第一電晶體T1之第二端的一第一端、電連接發光元件906之第一端的一第二端、及接收第一控制信號S1(N)的一控制端,且根據第一控制信號S1(N)的控制,以決定是否將來自第一電晶體T1的驅動電流輸出到發光元件906。Referring to FIG. 13, a sixth preferred embodiment of the present pixel unit is substantially similar to the third preferred embodiment. The difference is that the third switch SW3 of the control module 806 is a P-type transistor ( PMOS) a first end electrically connected to the second end of the first transistor T1, a second end electrically connected to the first end of the light emitting element 906, and a control end receiving the first control signal S1(N), and according to the Control of the control signal S1(N) to determine whether to output the drive current from the first transistor T1 to the light-emitting element 906.
圖14是一時序圖,輔助圖13說明第六較佳實施例。參閱圖 13與圖14,在補償階段P1時,第一控制信號S1(N)為邏輯高準位,使第一與第二開關SW1、SW2導通,並使第三開關SW3不導通。在發光階段P2時,第一控制信號S1(N)為邏輯低準位,使第一與第二開關SW1、SW2不導通,並使第三開關SW3導通。Fig. 14 is a timing chart, and Fig. 13 illustrates a sixth preferred embodiment. See picture 13 and FIG. 14, in the compensation phase P1, the first control signal S1(N) is at a logic high level, the first and second switches SW1, SW2 are turned on, and the third switch SW3 is not turned on. In the light-emitting phase P2, the first control signal S1(N) is at a logic low level, so that the first and second switches SW1, SW2 are not turned on, and the third switch SW3 is turned on.
參閱圖15,本創作畫素單元之第七較佳實施例,大致上是 與第四較佳實施例相似,不同的地方在於:控制模組807之第三開關SW3為一P型電晶體(PMOS),並具有電連接第一電晶體T1之第二端的一第一端、電連接發光元件907之第一端的一第二端、及接收第一控制信號S1(N)的一控制端,且根據第一控制信號S1(N)的控制,以決定是否將來自第一電晶體T1的驅動電流輸出到發光元件907。Referring to Figure 15, a seventh preferred embodiment of the present pixel unit is substantially Similar to the fourth preferred embodiment, the difference is that the third switch SW3 of the control module 807 is a P-type transistor (PMOS) and has a first end electrically connected to the second end of the first transistor T1. a second end of the first end of the light-emitting element 907, and a control end of the first control signal S1(N), and according to the control of the first control signal S1(N), to determine whether it will come from the first The drive current of a transistor T1 is output to the light-emitting element 907.
圖16是一時序圖,輔助圖15說明第七較佳實施例。參閱圖 15與圖16,在補償階段P1時,第一控制信號S1(N)為邏輯高準位,使第一與第二開關SW1、SW2導通,並使第三開關SW3不導通。在發光階段P2時,第一控制信號S1(N)為邏輯低準位,使第一與第二開關SW1、SW2不導通,並使第三開關SW3導通。Fig. 16 is a timing chart, and Fig. 15 illustrates a seventh preferred embodiment. See picture 15 and FIG. 16, in the compensation phase P1, the first control signal S1(N) is at a logic high level, the first and second switches SW1, SW2 are turned on, and the third switch SW3 is not turned on. In the light-emitting phase P2, the first control signal S1(N) is at a logic low level, so that the first and second switches SW1, SW2 are not turned on, and the third switch SW3 is turned on.
參閱圖17,本創作畫素單元之第八較佳實施例,大致上是 與第一較佳實施例相似,不同的地方在於:控制模組808省略第三開關SW3(見圖1),且第二開關SW2具有電連接第一電晶體T1之第二端與發光元件908之第一端的一第一端、一第二端、及接收第一控制信號S1(N)的一控制端,且根據第一控制信號S1(N)的控制,於導通與不導通間切換。Referring to Figure 17, an eighth preferred embodiment of the present pixel unit is substantially Similar to the first preferred embodiment, the difference is that the control module 808 omits the third switch SW3 (see FIG. 1), and the second switch SW2 has a second end electrically connected to the first transistor T1 and the light-emitting element 908. a first end, a second end of the first end, and a control end receiving the first control signal S1(N), and switching between conducting and non-conducting according to the control of the first control signal S1(N) .
圖18是一時序圖,輔助圖17說明第八較佳實施例。參閱圖 17與圖18,畫素單元根據第一控制信號S1(N),在一補償階段P1及一發光階段P2操作,且在補償階段P1時,發光元件908之第一端與第二端的跨壓需小於發光元件的導通電壓VDRIVE ,即VB -VSS<VDRIVE 。Figure 18 is a timing chart, and Figure 17 illustrates an eighth preferred embodiment. Referring to FIG. 17 and FIG. 18, the pixel unit operates according to the first control signal S1(N) in a compensation phase P1 and an illumination phase P2, and in the compensation phase P1, the first end and the second end of the light-emitting element 908 The voltage across the voltage needs to be less than the turn-on voltage V DRIVE of the light-emitting element, ie V B -VSS < V DRIVE .
參閱圖19,本創作畫素單元之第九較佳實施例,大致上是 與第三較佳實施例相似,不同的地方在於:控制模組809省略第三開關SW3(見圖7),且第二開關SW2具有電連接第一電晶體T1之第二端與發光元件909之第一端的一第一端、一第二端、及接收第一控制信號S1(N)的一控制端,且根據第一控制信號S1(N)的控制,於導通與不導通間切換。Referring to Figure 19, a ninth preferred embodiment of the present pixel unit is substantially Similar to the third preferred embodiment, the difference is that the control module 809 omits the third switch SW3 (see FIG. 7), and the second switch SW2 has a second end electrically connected to the first transistor T1 and the light-emitting element 909. a first end, a second end of the first end, and a control end receiving the first control signal S1(N), and switching between conducting and non-conducting according to the control of the first control signal S1(N) .
圖20是一時序圖,輔助圖19說明第九較佳實施例。參閱圖 19與圖20,畫素單元根據第一控制信號S1(N)及相鄰之另一列的第一控制信號S1(N+1),在一補償階段P1及一發光階段P2操作,且在補償階段P1時,發光元件909之第一端與第二端的跨壓需小於發光元件的導通電壓VDRIVE ,即VB -VSS<VDRIVE 。Fig. 20 is a timing chart, and Fig. 19 illustrates a ninth preferred embodiment. Referring to FIG. 19 and FIG. 20, the pixel unit operates according to the first control signal S1(N) and the first control signal S1(N+1) of another adjacent column, in a compensation phase P1 and an illumination phase P2, and During the compensation phase P1, the voltage across the first end and the second end of the light-emitting element 909 needs to be smaller than the turn-on voltage V DRIVE of the light-emitting element, that is, V B -VSS < V DRIVE .
參閱圖21,本創作畫素單元之第十較佳實施例,大致上是 與第四較佳實施例相似,不同的地方在於:控制模組8省略第三開關SW3(見圖9),且第二開關SW2具有電連接第一電晶體T1之第二端與發光元件910之第一端的一第一端、一第二端、及接收第一控制信號S1(N)的一控制端,且 根據第一控制信號S1(N)的控制,於導通與不導通間切換。Referring to Figure 21, a tenth preferred embodiment of the present pixel unit is substantially Similar to the fourth preferred embodiment, the difference is that the control module 8 omits the third switch SW3 (see FIG. 9), and the second switch SW2 has a second end electrically connected to the first transistor T1 and the light-emitting element 910. a first end, a second end, and a control end of the first control signal S1(N) Switching between conduction and non-conduction according to the control of the first control signal S1(N).
圖22是一時序圖,輔助圖21說明第十較佳實施例。參閱圖 21與圖22,畫素單元根據第一控制信號S1(N),在一補償階段P1及一發光階段P2操作,且在補償階段P1時,發光元件910之第一端與第二端的跨壓需小於發光元件的導通電壓VDRIVE ,即VB -VSS<VDRIVE 。Fig. 22 is a timing chart, and Fig. 21 illustrates a tenth preferred embodiment. Referring to FIG. 21 and FIG. 22, the pixel unit operates according to the first control signal S1(N) in a compensation phase P1 and an illumination phase P2, and in the compensation phase P1, the first end and the second end of the light-emitting element 910 The voltage across the voltage needs to be less than the turn-on voltage V DRIVE of the light-emitting element, ie V B -VSS < V DRIVE .
由以上各實施例可知,藉由控制模組至少根據第一控制信 號S1(N),能產生相關於資料電壓Data的驅動電流IDRIVE ,而不受第一電晶體T1之臨界電壓VTH,1 的影響。也就是說,不會因為驅動電晶體(在以上實施例為第一電晶體T1)之製程的均勻性問題,使得不同畫素單元之驅動電晶體的臨界電壓不同,導致在給予相同資料電壓時,卻有相對應的驅動電流不相等的現象,進而改善由畫素單元所組成的面板之亮度不均或烙印的問題。It can be seen from the above embodiments that the control module I can generate the driving current I DRIVE related to the data voltage Data by at least the first control signal S1(N), without being affected by the threshold voltage V TH of the first transistor T1 . The impact of 1 . That is to say, the threshold voltage of the driving transistors of different pixel units is not different due to the uniformity of the process of driving the transistor (the first transistor T1 in the above embodiment), resulting in the same data voltage being applied. However, there is a phenomenon that the corresponding driving currents are not equal, thereby improving the uneven brightness or branding of the panel composed of the pixel units.
701‧‧‧驅動電路701‧‧‧ drive circuit
801‧‧‧控制模組801‧‧‧Control Module
901‧‧‧發光元件901‧‧‧Lighting elements
C1‧‧‧電容器C1‧‧‧ capacitor
Data‧‧‧資料電壓Data‧‧‧data voltage
S1‧‧‧第一控制信號S1‧‧‧ first control signal
S2‧‧‧第二控制信號S2‧‧‧ second control signal
SW1‧‧‧第一開關SW1‧‧‧ first switch
SW2‧‧‧第二開關SW2‧‧‧second switch
SW3‧‧‧第三開關SW3‧‧‧ third switch
T1‧‧‧第一電晶體T1‧‧‧first transistor
T2‧‧‧第二電晶體T2‧‧‧second transistor
VDD‧‧‧第一電源電壓VDD‧‧‧first supply voltage
VSS‧‧‧第二電源電壓VSS‧‧‧second supply voltage
Claims (15)
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TW103126470A TWI571853B (en) | 2013-11-07 | 2014-08-01 | Pixel units and driving circuits |
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TWI571853B (en) * | 2013-11-07 | 2017-02-21 | 宸鴻光電科技股份有限公司 | Pixel units and driving circuits |
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TWI228696B (en) * | 2003-03-21 | 2005-03-01 | Ind Tech Res Inst | Pixel circuit for active matrix OLED and driving method |
KR100560479B1 (en) * | 2004-03-10 | 2006-03-13 | 삼성에스디아이 주식회사 | Light emitting display device, and display panel and driving method thereof |
TWI258117B (en) * | 2004-06-11 | 2006-07-11 | Au Optronics Corp | Pixel structure, driving method thereof |
US8044891B2 (en) * | 2005-08-05 | 2011-10-25 | Chimei Innolux Corporation | Systems and methods for providing threshold voltage compensation of pixels |
TWI410932B (en) * | 2008-05-09 | 2013-10-01 | Innolux Corp | Pixel structure |
CN102290027B (en) * | 2010-06-21 | 2013-10-30 | 北京大学深圳研究生院 | Pixel circuit and display device |
KR101162864B1 (en) * | 2010-07-19 | 2012-07-04 | 삼성모바일디스플레이주식회사 | Pixel and Organic Light Emitting Display Device Using the same |
CN102708790A (en) * | 2011-12-01 | 2012-10-03 | 京东方科技集团股份有限公司 | Pixel unit driving circuit and method, pixel unit and display device |
CN103354077B (en) * | 2013-05-31 | 2017-02-08 | 上海和辉光电有限公司 | Pixel drive circuit and display panel |
CN203607085U (en) * | 2013-11-07 | 2014-05-21 | 宸鸿光电科技股份有限公司 | Picture element unit and drive circuit |
CN104637432B (en) * | 2013-11-07 | 2017-03-01 | 宸鸿光电科技股份有限公司 | Pixel cell and drive circuit |
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TWI571853B (en) | 2017-02-21 |
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