TWM484863U - Sequential pulse signal generator - Google Patents
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本發明係關於一種脈波產生器,特別是一種將一輸入電壓轉換一連續脈波信號之脈波產生器。The present invention relates to a pulse wave generator, and more particularly to a pulse wave generator for converting an input voltage into a continuous pulse wave signal.
連續脈波產生器已廣泛地使用在利用時脈訊號(clock signal)之觸發來產生電子脈衝訊號之積體電路的運用產品。圖1所示為一習知之連續脈波產生器1,其包含一延遲單元12及一NAND邏輯閘11。該延遲單元12係由奇數個反相器彼此串接形成,以將一輸入訊號Vin反相並延遲一特定內部時間(certain internal time)而形成一負邏輯運算(negative logic operation)之延遲訊號Vd。該NAND邏輯閘11接收該延遲訊號Vd及該輸入訊號Vin之後,經過NAND運算輸出一輸出訊號Vout。由於該輸出訊號Vout之脈寬與該延遲單元12中之反相器INV數目有關。因此,該輸出訊號Vout之脈寬將與反相器INV數目有關且無法經由外部設定調整。Continuous pulse wave generators have been widely used in applications that use an integrated circuit for generating an electronic pulse signal using a trigger of a clock signal. 1 shows a conventional continuous pulse generator 1 comprising a delay unit 12 and a NAND logic gate 11. The delay unit 12 is formed by serially connecting an odd number of inverters to invert an input signal Vin and delay a specific internal time to form a negative logic operation delay signal Vd. . After receiving the delay signal Vd and the input signal Vin, the NAND logic gate 11 outputs an output signal Vout through a NAND operation. Since the pulse width of the output signal Vout is related to the number of inverters INV in the delay unit 12. Therefore, the pulse width of the output signal Vout will be related to the number of inverters INV and cannot be adjusted via an external setting.
圖2(a)所示為另一習知之連續脈波產生器2,係利用一電壓源Vdc交替地經由電阻R4與R6分別對電容C1與C2充電及交替地經經由電阻R4及R3與R6及R7分別對電容C1與C2放電,藉由控制開關元件Q1與Q2之開啟(turn on)或截斷(turn off),以穩定地在Vout1與Vout2產生如圖2(b)所示之對稱脈波訊號。由於該輸出訊號Vout1與Vout2之脈寬與電容與電阻之數值有關。因此,該輸出訊號Vout1與Vout2之脈寬將固定不變。Figure 2 (a) shows another conventional continuous pulse generator 2, which uses a voltage source Vdc to alternately charge capacitors C1 and C2 via resistors R4 and R6, respectively, and alternately via resistors R4 and R3 and R6. And R7 discharges the capacitors C1 and C2, respectively, by controlling the turn-on or turn-off of the switching elements Q1 and Q2 to stably generate the symmetrical pulse as shown in FIG. 2(b) at Vout1 and Vout2. Wave signal. Since the pulse widths of the output signals Vout1 and Vout2 are related to the values of the capacitance and the resistance. Therefore, the pulse widths of the output signals Vout1 and Vout2 will be fixed.
另,美國專利US6,121,803揭示一脈波產生器,係根據一電壓源Vcc由0V上升至一預設值並將一電源打開或重置以穩定地產生脈波訊號。當該電壓源Vcc之上升斜率控制不良時,將導致脈波脈寬改變。此外,將該電壓源Vcc由0V提昇至一預設值(5V或3V)時,所需之時間需要數微秒或更長,因此無法滿足脈波寬度小於微秒的運用上。再者,若欲產生一具預期脈寬之連續脈波,習知技藝需要許多的反相器或電晶體,如此將增 加電路設計之複雜度及成本。In addition, U.S. Patent No. 6,121,803 discloses a pulse generator which rises from 0 V to a predetermined value according to a voltage source Vcc and opens or resets a power source to stably generate a pulse wave signal. When the rising slope of the voltage source Vcc is poorly controlled, the pulse width will be changed. In addition, when the voltage source Vcc is raised from 0V to a preset value (5V or 3V), the required time takes several microseconds or longer, and thus the operation in which the pulse width is less than microseconds cannot be satisfied. Furthermore, if a continuous pulse wave of a desired pulse width is to be generated, conventional techniques require many inverters or transistors, which will increase Add complexity and cost to circuit design.
為解決上述技術問題,本發明提供了一種連續脈波信號產生器,用以將一輸入電壓轉換一連續脈波信號,包括:一檢測模組、一電流放大模組、一充電/放電器、一比較模組以及一輸出模組。該檢測模組用於將一輸入電壓轉換為一輸入電流;該電流放大模組耦接至該充電/放電器,並產生該連續脈波信號與一充電/放電控制信號,以回應該輸入電流;其中,該充電/放電器耦接至該比較模組與該輸出模組;該比較模組耦接至該輸出模組並產生一比較信號,以回應該充電/放電控制信號;以及該連續脈波信號係由該輸出模組之一輸出輸出。In order to solve the above technical problem, the present invention provides a continuous pulse wave signal generator for converting an input voltage into a continuous pulse wave signal, comprising: a detecting module, a current amplifying module, a charging/discharging device, A comparison module and an output module. The detection module is configured to convert an input voltage into an input current; the current amplification module is coupled to the charge/discharger, and generates the continuous pulse signal and a charge/discharge control signal to respond to the input current The charging/discharging device is coupled to the comparison module and the output module; the comparison module is coupled to the output module and generates a comparison signal to respond to the charging/discharging control signal; and the continuous The pulse signal is outputted by one of the output modules.
本發明還提供一種連續脈波信號產生器,用以將一輸入電阻轉換一連續脈波信號,包括:一檢測模組、一電流放大模組、一充電/放電器、一比較模組以及一輸出模組。該檢測模組用於將一輸入電阻轉換為一輸入電流;該電流放大模組耦接至該充電/放電器,並產生該連續脈波信號與一充電/放電控制信號,以回應該輸入電流;其中,該充電/放電器耦接至該比較模組與該輸出模組;該比較模組耦接至該輸出模組並產生一比較信號,以回應該充電/放電控制信號;以及該連續脈波信號係由該輸出模組之一輸出輸出。The invention also provides a continuous pulse wave signal generator for converting an input resistance into a continuous pulse wave signal, comprising: a detection module, a current amplification module, a charge/discharge device, a comparison module and a Output module. The detection module is configured to convert an input resistance into an input current; the current amplification module is coupled to the charge/discharger, and generates the continuous pulse signal and a charge/discharge control signal to respond to the input current The charging/discharging device is coupled to the comparison module and the output module; the comparison module is coupled to the output module and generates a comparison signal to respond to the charging/discharging control signal; and the continuous The pulse signal is outputted by one of the output modules.
1、2‧‧‧習知之脈波產生器1, 2‧‧‧Knowledge pulse generator
12‧‧‧延遲單元12‧‧‧Delay unit
11‧‧‧NAND邏輯閘11‧‧‧NAND Logic Gate
300‧‧‧連續脈波信號產生器300‧‧‧Continuous Pulse Signal Generator
301‧‧‧檢測模組301‧‧‧Test module
302‧‧‧電流放大模組302‧‧‧Current amplification module
303‧‧‧充電/放電器303‧‧‧Charge/discharger
304‧‧‧比較模組304‧‧‧Comparative Module
305‧‧‧輸出模組305‧‧‧Output module
310‧‧‧電阻310‧‧‧resistance
311‧‧‧運算放大器311‧‧‧Operational Amplifier
312、313、314‧‧‧MOSFET312, 313, 314‧‧‧ MOSFET
315‧‧‧開關315‧‧‧ switch
316‧‧‧電容316‧‧‧ Capacitance
317、318‧‧‧比較器317, 318‧‧‧ comparator
319‧‧‧SR正反器319‧‧‧SR positive and negative
320‧‧‧連續脈衝信號320‧‧‧Continuous pulse signal
400‧‧‧連續脈波信號產生器400‧‧‧Continuous Pulse Signal Generator
401‧‧‧檢測模組401‧‧‧Test module
402‧‧‧電流放大模組402‧‧‧Current amplification module
403‧‧‧充電/放電器403‧‧‧Charge/discharger
404‧‧‧比較模組404‧‧‧Comparative Module
405‧‧‧輸出模組405‧‧‧Output module
410‧‧‧輸入電阻410‧‧‧Input resistance
411‧‧‧運算放大器411‧‧‧Operational Amplifier
412、413、414‧‧‧MOSFET412, 413, 414‧‧‧ MOSFET
415‧‧‧開關415‧‧‧ switch
416‧‧‧電容416‧‧‧ Capacitance
417、418‧‧‧比較器417, 418‧‧‧ comparator
419‧‧‧SR正反器419‧‧‧SR positive and negative
420‧‧‧連續脈衝信號420‧‧‧Continuous pulse signal
以下結合附圖和具體實施例對本發明的技術方法進行詳細的描述,以使本發明的特徵和優點更為明顯。其中:圖1(a)所示為習知連續脈波信號產生器的示意圖。The technical method of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments to make the features and advantages of the present invention more obvious. Wherein: Figure 1 (a) shows a schematic diagram of a conventional continuous pulse wave signal generator.
圖1(b)所示為另一習知連續脈波信號產生器的輸出波形示意圖。Fig. 1(b) is a diagram showing the output waveform of another conventional continuous pulse wave signal generator.
圖2(a)所示為另一習知連續脈波信號產生器的示意圖。Figure 2 (a) is a schematic diagram of another conventional continuous pulse wave signal generator.
圖2(b)所示為另一習知連續脈波信號產生器的輸出波形示意圖。Fig. 2(b) is a diagram showing the output waveform of another conventional continuous pulse wave signal generator.
圖3所示為根據本發明一實施例連續脈波信號產生器方塊示意電路圖。3 is a schematic circuit diagram of a continuous pulse wave signal generator block in accordance with an embodiment of the present invention.
圖4所示為根據本發明另一實施例連續脈波信號產生器方塊示意電路圖。4 is a schematic circuit diagram of a continuous pulse wave signal generator block in accordance with another embodiment of the present invention.
以下將對本發明的實施例做出詳細說明。雖然本發明將結合實施例進行闡述,但應理解這並非意指將本發明限定於這些實施例。相反地,本發明意在涵蓋由後附申請專利範圍所界定的本發明精神和範圍內所定義的各種變化、修改和均等物。The embodiments of the present invention will be described in detail below. While the invention will be described in conjunction with the embodiments, it is understood that the invention is not limited to the embodiments. Rather, the invention is to cover various modifications, equivalents, and equivalents of the invention as defined by the scope of the appended claims.
此外,在以下對本發明的詳細描述中,闡明大量的具體細節以提供針對本發明的全面理解。然而,本技術領域中具有通常知識者應理解,沒有這些具體細節,本發明同樣可以實施。在其他實例中,對於習知方法、流程、元件和電路未作詳細描述,以便於凸顯本發明之主旨。In addition, in the following detailed description of the embodiments of the invention However, it will be understood by those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail in order to facilitate the invention.
以下部分詳細描述係以程序、邏輯方塊、步驟、以及其他代表電腦記憶體內資料位元的運算之符號表示之。這些描述與表述係為資料處理技術領域中具有通常知識者用以傳達其工作實質內容的最有效方式。在本發明中,一程序、一邏輯方塊、一步驟或其他等等,被認定為以一自身一致順序之步驟或指令導引產生一所需之結果。The following detailed description is a symbolic representation of procedures, logic blocks, steps, and other operations that represent data bits in a computer memory. These descriptions and representations are the most effective way for those of ordinary skill in the field of data processing technology to convey the substance of their work. In the present invention, a program, a logic block, a step or the like is considered to produce a desired result in a self-consistent sequence of steps or instructions.
根據本發明實施例係提供一連續脈波信號之脈波產生器。有利之處在於,該脈波產生器所產生之連續脈波信號之可一具預期脈寬。A pulse wave generator for a continuous pulse wave signal is provided in accordance with an embodiment of the present invention. Advantageously, the continuous pulse signal generated by the pulse generator can have a desired pulse width.
圖3所示為根據本發明一實施例脈衝信號產生器300的例示性示意電路圖。連續脈波信號產生器300,包括:一檢測模組301、一電流放大模組302、一充電/放電器303、一比較模組304以及一輸出模組305。檢測模組301用以一輸入電壓轉換一電流信號。在一實施例中,檢測模組301由MOSFET 312、運算放大器311、以及電阻310組成。電流放大模組302為由MOSFET 313和MOSFET 314所構成一電流鏡。在一實施例中,MOSFET 313和MOSFET 314所構成一電流鏡其之放大率可由MOSFET 313和MOSFET 314之通道之長寬比例決定。充電/放電器303由電容316與開關315並聯組成。在一實施例中,比較模組304為由比較器317的和比較器318所組成之一窗形比較器。在一實施例中,輸出模組305為一SR正反器。脈衝信號產生器300經由端子IN接收一輸入電壓Vin後,產生一連續脈衝信號Vout於端子OUT。FIG. 3 shows an illustrative schematic circuit diagram of a pulse signal generator 300 in accordance with an embodiment of the present invention. The continuous pulse signal generator 300 includes a detection module 301, a current amplification module 302, a charge/discharger 303, a comparison module 304, and an output module 305. The detecting module 301 is configured to convert a current signal by an input voltage. In one embodiment, the detection module 301 is comprised of a MOSFET 312, an operational amplifier 311, and a resistor 310. The current amplification module 302 is a current mirror formed by the MOSFET 313 and the MOSFET 314. In one embodiment, the MOSFET 313 and MOSFET 314 form a current mirror whose amplification can be determined by the aspect ratio of the channels of MOSFET 313 and MOSFET 314. The charge/discharger 303 is composed of a capacitor 316 in parallel with the switch 315. In one embodiment, the comparison module 304 is a window comparator composed of the comparator 317 and the comparator 318. In one embodiment, the output module 305 is an SR flip-flop. After receiving the input voltage Vin via the terminal IN, the pulse signal generator 300 generates a continuous pulse signal Vout at the terminal OUT.
在脈衝信號產生器300中,運算放大器311的非反相輸入端 接收一輸入電壓Vin。在一實施例中,輸入電壓Vin為0V~5V。因此,運算放大器311的反相輸入端電壓也為Vin。電流I310透過電阻310流到地。流經金屬氧化物半導體場效應電晶體(MOSFET)313和MOSFET 312的電流I1與電流I310相等。由於MOSFET 313和MOSFET 314構成電流鏡,因此流經MOSFET 314的電流I2也與電流I310相等。比較器317的輸出和比較器318的輸出分別與SR正反器319的S輸入端和R輸入端耦接。比較器317的反相輸入端接收預設電壓V1。比較器318的非反相輸入端接收預設電壓V2。在一實施例中,V1大於V2且V2大於0。電容316耦接於MOSFET 314和地之間,且有一端與比較器317非反相輸入端和比較器318反相輸入端輸入之間的共同節點耦接。SR正反器319的Q輸出端與開關315及SR正反器319的S輸入端耦接。開關315與電容316並聯。開關315的導通狀態(例如:導通/關斷)由SR正反器319的Q輸出端決定。在一實施例中,開關315為一MOSFET。In the pulse signal generator 300, the non-inverting input terminal of the operational amplifier 311 Receiving an input voltage Vin. In an embodiment, the input voltage Vin is 0V~5V. Therefore, the inverting input voltage of the operational amplifier 311 is also Vin. Current I310 flows through resistor 310 to ground. The current I1 flowing through the metal oxide semiconductor field effect transistor (MOSFET) 313 and the MOSFET 312 is equal to the current I310. Since MOSFET 313 and MOSFET 314 form a current mirror, current I2 flowing through MOSFET 314 is also equal to current I310. The output of comparator 317 and the output of comparator 318 are coupled to the S input and R input of SR flip flop 319, respectively. The inverting input of the comparator 317 receives the preset voltage V1. The non-inverting input of comparator 318 receives a preset voltage V2. In an embodiment, V1 is greater than V2 and V2 is greater than zero. Capacitor 316 is coupled between MOSFET 314 and ground and has a common node coupled between one end and a non-inverting input of comparator 317 and an inverting input of comparator 318. The Q output of the SR flip-flop 319 is coupled to the S input of the switch 315 and the SR flip-flop 319. Switch 315 is in parallel with capacitor 316. The on state of switch 315 (eg, on/off) is determined by the Q output of SR flip-flop 319. In an embodiment, the switch 315 is a MOSFET.
電容316兩端的初始電壓近似為0,小於V2。因此SR正反器319的R輸入端接收比較器318輸出的數位信號1。SR正反器319的Q輸出端被設置為數位信號0,其關斷開關315。當開關315關斷,隨著電容316由電流I2充電,電容316兩端的電壓升高。當電容316兩端電壓大於V1,SR正反器319的S輸入端接收比較器317輸出的數位信號1。SR正反器319的Q輸出端被設置為數位信號1,其導通開關315。當開關315導通,隨著電容316經由開關315放電,電容316兩端的電壓降低。當電容316兩端的電壓下降到低於V2,比較器318輸出數位信號1,且SR正反器319的Q輸出端被設置為數位信號0,其關斷開關315。接著電容316又由電流I2充電。如此,經由上述過程,脈衝信號產生器300產生連續脈衝信號320。控制預設電壓V1與V2之大小值,可控制連續脈衝信號之脈寬。連續脈衝信號320被同時傳送至SR正反器319的S輸入端,其包括在SR正反器319的Q輸出端上一系列的脈衝信號320。因此,控制預設電壓V1與V2之大小值,本發明即可相當容易地產生具任一預期脈寬之連續脈波。The initial voltage across capacitor 316 is approximately zero, less than V2. Therefore, the R input terminal of the SR flip-flop 319 receives the digital signal 1 output from the comparator 318. The Q output of SR flip-flop 319 is set to digital signal 0, which turns off switch 315. When switch 315 is turned off, as capacitor 316 is charged by current I2, the voltage across capacitor 316 rises. When the voltage across the capacitor 316 is greater than V1, the S input of the SR flip-flop 319 receives the digital signal 1 output by the comparator 317. The Q output of the SR flip-flop 319 is set to digital signal 1, which turns on the switch 315. When switch 315 is turned on, as capacitor 316 is discharged via switch 315, the voltage across capacitor 316 decreases. When the voltage across capacitor 316 drops below V2, comparator 318 outputs digital signal 1, and the Q output of SR flip-flop 319 is set to digital signal 0, which turns off switch 315. Capacitor 316 is in turn charged by current I2. As such, the pulse signal generator 300 generates the continuous pulse signal 320 via the above process. Controlling the magnitude of the preset voltages V1 and V2 controls the pulse width of the continuous pulse signal. The continuous pulse signal 320 is simultaneously transmitted to the S input of the SR flip-flop 319, which includes a series of pulse signals 320 at the Q output of the SR flip-flop 319. Therefore, by controlling the magnitude values of the preset voltages V1 and V2, the present invention can relatively easily generate continuous pulse waves having any desired pulse width.
圖4(a)所示為根據本發明另一實施例脈衝信號產生器400的 例示性示意電路圖。連續脈波信號產生器400,包括:一檢測模組401、一電流放大模組402、一充電/放電器403、一比較模組404以及一輸出模組405。圖4中與圖3編號相同的元件具有類似功能,為簡明起見在此不重複描述。檢測模組401用以一輸入電阻轉換一電流信號。在一實施例中,檢測模組401由MOSFET 412、運算放大器411、以及電阻410組成。電流放大模組402為由MOSFET 413和MOSFET 414所構成一電流鏡。在一實施例中,MOSFET 413和MOSFET 414所構成一電流鏡其之放大率可由MOSFET 413和MOSFET 414之通道之長寬比例決定。充電/放電器403由電容416與開關415並聯組成。在一實施例中,比較模組304為由比較器417的和比較器418所組成之一窗形比較器。在一實施例中,輸出模組405為一SR正反器。脈衝信號產生器400經由端子IN接收一輸入電阻410後,產生一連續脈衝信號Vout於端子OUT。4(a) shows a pulse signal generator 400 according to another embodiment of the present invention. An illustrative schematic circuit diagram. The continuous pulse wave signal generator 400 includes a detection module 401, a current amplification module 402, a charge/discharger 403, a comparison module 404, and an output module 405. Elements in Figure 4 that are numbered the same as in Figure 3 have similar functions and will not be repeatedly described herein for the sake of brevity. The detection module 401 is configured to convert a current signal by an input resistor. In one embodiment, the detection module 401 is comprised of a MOSFET 412, an operational amplifier 411, and a resistor 410. The current amplification module 402 is a current mirror formed by the MOSFET 413 and the MOSFET 414. In one embodiment, the MOSFET 413 and MOSFET 414 form a current mirror whose amplification can be determined by the aspect ratio of the channels of MOSFET 413 and MOSFET 414. Charge/discharger 403 is comprised of capacitor 416 in parallel with switch 415. In one embodiment, the comparison module 304 is a window comparator composed of the comparator 417 and the comparator 418. In an embodiment, the output module 405 is an SR flip-flop. After the pulse signal generator 400 receives an input resistor 410 via the terminal IN, a continuous pulse signal Vout is generated at the terminal OUT.
在脈衝信號產生器400中,運算放大器411的非反相輸入端接收一預設輸入電壓Vint。在一實施例中,預設輸入電壓Vint為5伏特。在另一實施例中,預設輸入電壓Vint為3.3伏特。因此,運算放大器411的反相輸入端電壓也為Vin。電流I410透過輸入電阻410流到地。在一實施例中,輸入電阻410為1仟歐姆~100仟歐姆。流經金屬氧化物半導體場效應電晶體(MOSFET)413和MOSFET 412的電流I1與電流I410相等。由於MOSFET 413和MOSFET 414構成電流鏡,因此流經MOSFET 414的電流I2也與電流I410相等。比較器417的輸出和比較器418的輸出分別與SR正反器419的S輸入端和R輸入端耦接。比較器317的反相輸入端接收預設電壓V1。比較器418的非反相輸入端接收預設電壓V2。在一實施例中,V1大於V2且V2大於0。電容416耦接於MOSFET 414和地之間,且有一端與比較器417非反相輸入端和比較器418反相輸入端輸入之間的共同節點耦接。SR正反器419的Q輸出端與開關415及SR正反器419的S輸入端耦接。開關415與電容416並聯。開關415的導通狀態(例如:導通/關斷)由SR正反器419的Q輸出端決定。在一實施例中,開關415為一MOSFET。In the pulse signal generator 400, the non-inverting input of the operational amplifier 411 receives a predetermined input voltage Vint. In an embodiment, the preset input voltage Vint is 5 volts. In another embodiment, the preset input voltage Vint is 3.3 volts. Therefore, the inverting input voltage of the operational amplifier 411 is also Vin. Current I410 flows through input resistor 410 to ground. In one embodiment, the input resistance 410 is 1 仟 ohms to 100 仟 ohms. The current I1 flowing through the metal oxide semiconductor field effect transistor (MOSFET) 413 and the MOSFET 412 is equal to the current I410. Since MOSFET 413 and MOSFET 414 form a current mirror, current I2 flowing through MOSFET 414 is also equal to current I410. The output of comparator 417 and the output of comparator 418 are coupled to the S input and R input of SR flip-flop 419, respectively. The inverting input of the comparator 317 receives the preset voltage V1. The non-inverting input of comparator 418 receives a predetermined voltage V2. In an embodiment, V1 is greater than V2 and V2 is greater than zero. Capacitor 416 is coupled between MOSFET 414 and ground and has a common node coupling between one end and a non-inverting input of comparator 417 and an inverting input of comparator 418. The Q output of the SR flip-flop 419 is coupled to the S input of the switch 415 and the SR flip-flop 419. Switch 415 is coupled in parallel with capacitor 416. The on state of switch 415 (eg, on/off) is determined by the Q output of SR flip-flop 419. In an embodiment, the switch 415 is a MOSFET.
電容416兩端的初始電壓近似為0,小於V2。因此SR正反器419的R輸入端接收比較器418輸出的數位信號1。SR正反器419的Q輸出端被設置為數位信號0,其關斷開關415。當開關415關斷,隨著電容416由電流I2充電,電容416兩端的電壓升高。當電容416兩端電壓大於V1,SR正反器419的S輸入端接收比較器417輸出的數位信號1。SR正反器419的Q輸出端被設置為數位信號1,其導通開關415。當開關415導通,隨著電容416經由開關415放電,電容416兩端的電壓降低。當電容416兩端的電壓下降到低於V2,比較器418輸出數位信號1,且SR正反器419的Q輸出端被設置為數位信號0,其關斷開關415。接著電容416又由電流I2充電。如此,經由上述過程,脈衝信號產生器400產生連續脈衝信號420。控制預設電壓V1與V2之大小值,可控制連續衝信號之脈寬。連續脈衝信號420被同時傳送至SR正反器419的S輸入端,其包括在SR正反器319的Q輸出端上一系列的連續脈衝信號420。因此,控制預設電壓V1與V2之大小值,本發明即可相當容易地產生具任一預期脈寬之連續脈波。The initial voltage across capacitor 416 is approximately zero, less than V2. Therefore, the R input terminal of the SR flip-flop 419 receives the digital signal 1 output from the comparator 418. The Q output of SR flip-flop 419 is set to digital signal 0, which turns off switch 415. When switch 415 is turned off, as capacitor 416 is charged by current I2, the voltage across capacitor 416 rises. When the voltage across the capacitor 416 is greater than V1, the S input of the SR flip-flop 419 receives the digital signal 1 output by the comparator 417. The Q output of the SR flip-flop 419 is set to a digital signal 1, which turns on the switch 415. When switch 415 is turned on, as capacitor 416 discharges via switch 415, the voltage across capacitor 416 decreases. When the voltage across capacitor 416 drops below V2, comparator 418 outputs digital signal 1, and the Q output of SR flip-flop 419 is set to digital signal 0, which turns off switch 415. Capacitor 416 is in turn charged by current I2. As such, the pulse signal generator 400 generates a continuous pulse signal 420 via the above process. Controlling the magnitude of the preset voltages V1 and V2 controls the pulse width of the continuous rush signal. The continuous pulse signal 420 is simultaneously transmitted to the S input of the SR flip-flop 419, which includes a series of continuous pulse signals 420 at the Q output of the SR flip-flop 319. Therefore, by controlling the magnitude values of the preset voltages V1 and V2, the present invention can relatively easily generate continuous pulse waves having any desired pulse width.
上文具體實施方式和附圖僅為本發明之常用實施例。顯然,在不脫離後附申請專利範圍所界定的本發明精神和保護範圍的前提下可以有各種增補、修改和替換。本技術領域中具有通常知識者應該理解,本發明在實際應用中可根據具體的環境和工作要求在不背離發明準則的前提下在形式、結構、佈局、比例、材料、元素、元件及其它方面有所變化。因此,在此披露之實施例僅用於說明而非限制,本發明之範圍由後附申請專利範圍及其合法均等物界定,而不限於此前之描述。The above detailed description and the accompanying drawings are only typical embodiments of the invention. It is apparent that various additions, modifications and substitutions are possible without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood by those of ordinary skill in the art that the present invention may be applied in the form of the form, structure, arrangement, ratio, material, element, element, and other aspects in the actual application without departing from the invention. Changed. Therefore, the embodiments disclosed herein are intended to be illustrative and not restrictive, and the scope of the invention is defined by the scope of the appended claims and their legal equivalents.
300‧‧‧連續脈波信號產生器300‧‧‧Continuous Pulse Signal Generator
301‧‧‧檢測模組301‧‧‧Test module
302‧‧‧電流放大模組302‧‧‧Current amplification module
303‧‧‧充電/放電器303‧‧‧Charge/discharger
304‧‧‧比較模組304‧‧‧Comparative Module
305‧‧‧輸出模組305‧‧‧Output module
310‧‧‧電阻310‧‧‧resistance
311‧‧‧運算放大器311‧‧‧Operational Amplifier
312、313、314‧‧‧MOSFET312, 313, 314‧‧‧ MOSFET
315‧‧‧開關315‧‧‧ switch
316‧‧‧電容316‧‧‧ Capacitance
317、318‧‧‧比較器317, 318‧‧‧ comparator
319‧‧‧SR正反器319‧‧‧SR positive and negative
320‧‧‧連續脈波信號320‧‧‧Continuous pulse signal
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