TWM452439U - Low-temperature testing system for testing wafer-level integrated circuit - Google Patents

Abstract

The invention discloses a low-temperature testing system for testing a wafer-level integrated circuit. The low-temperature testing system of the invention includes a carrying fixture and a press coupling apparatus. The carrying fixture includes a wafer pad and a liquid conduit. The wafer pad holds the wafer-level such that a plurality of chips on the wafer-level integrated circuit face upward. The liquid conduit supplies a low temperature liquid through, and is thermally coupled to the wafer pad. The low temperature liquid exchanges heat with the heat-conducting device to lower the temperature of the wafer-level integrated circuit to a predetermined temperature. The press coupling apparatus thereon includes a probe device. When the temperature of the wafer-level integrated circuit lowers to the predetermined temperature, the press coupling apparatus and/or the carrying fixture move so that the chips of the wafer-level integrated circuit contact the probe device in sequence to perform test.

Description

Low temperature test system for testing wafer level integrated circuits

This creation is about a low-temperature testing system for testing wafer-level integrated circuits at low temperatures.

Conventional semiconductor devices (including semiconductor optoelectronic devices) are fabricated by fabricating tens of thousands of wafers on a wafer. After completing the integrated circuit of the uncut front wafer, it is usually necessary to perform electrical testing of the wafer level integrated circuit to distinguish between good and defective products.

Certain types of wafer-level integrated circuits must be circuit tested at low temperatures, for example, at -40 ° C, or even at -60 ° C in more demanding environments.

Most of the existing cryogenic test systems use low temperature nitrogen gas to heat exchange with the pressure fixture under the wafer level integrated circuit, so that the wafer level integrated circuit can be tested in a low temperature environment. However, by using low-temperature nitrogen to reach a low temperature, nitrogen gas is lost and cannot be recovered. Once the nitrogen supply to the low temperature nitrogen supply is exhausted, the low temperature test must be stopped and the operator is replaced with a new low temperature nitrogen supply before the low temperature test can be performed again. Therefore, the method of using low-temperature nitrogen to achieve low temperature may cause disadvantages such as poor use efficiency of the low-temperature test system, costly operation time, and high cost of nitrogen energy.

In addition, the method of using low-temperature nitrogen to reach a low temperature is not easy to control the temperature required for testing under the wafer-level integrated circuit. The existing cryogenic test systems have not seen designs that can control the temperature required for testing, and have not seen designs that can be tested at -60 °C.

Therefore, the technical problem to be solved by the present invention is to provide a low temperature test system for testing a wafer level integrated circuit at a low temperature state, and has good performance, good temperature control, convenient operation, greatly reduced cost, and controllable -Tested at -60 ° C environment and other advantages.

A cryogenic test system of a preferred embodiment of the present invention for testing a wafer level integrated circuit. The wafer level integrated circuit includes a plurality of wafers thereon. The low temperature test system of this creation includes a bearing fixture and a crimping device. The carrier fixture includes a wafer spacer and a liquid conduit. Wafer pads are used to hold the wafer level integrated circuit and have multiple wafers on the wafer level circuit facing up. The liquid conduit is for cryogenic liquid flow and is thermally coupled to the wafer spacer. The cryogenic liquid is heat exchanged with the wafer spacer to lower the temperature of the wafer level integrated circuit to a predetermined temperature. The crimping device includes a probe element thereon. When the temperature of the wafer level integrated circuit drops to a predetermined temperature, the crimping device and/or the carrier fixture move so that the plurality of wafers of the wafer level integrated circuit sequentially contact the probe elements for testing.

Further, the cryogenic test system of the present invention also includes a test room. The carrying fixture and the crimping device are placed in the test chamber.

Further, the cryogenic test system of the present invention also includes a freezer. The freezer is placed outside the test chamber and is connected to the liquid conduit. The freezer is used to cool the cryogenic liquid.

In a specific embodiment, the crimping device comprises a heat exchange container. The heat exchange container is connected to the liquid conduit and is circulated for the cryogenic liquid. The heat conducting element portion is disposed within the heat exchange container. The cryogenic liquid exchanges heat with the heat conducting element within the heat exchange vessel. Further, the portion of the heat conducting member disposed in the heat exchange container is formed into a fin-like member.

In one embodiment, the cryogenic liquid may be water or oil to which an antifreeze is added, or may be a refrigerant.

Further, the cryogenic test system of the present invention also includes a temperature sensor. temperature The sensor is placed on the wafer spacer and is used to sense the temperature of the wafer spacer.

In one embodiment, the liquid conduit is passed through the wafer spacer. The cryogenic test system of this creation further includes a flow controller. The flow controller is mounted at the inlet of the liquid conduit to the wafer shim and is electrically connected to the temperature sensor. The flow controller is configured to adjust the flow rate of the cryogenic liquid into the wafer spacer according to the temperature sensed by the temperature sensor.

Further, the cryogenic test system of the present invention also includes an air dryer. The air dryer is placed outside the test chamber and is connected to the test chamber by a gas conduit. An air dryer is used to supply dry air to the test chamber via a gas conduit.

Further, the cryogenic test system of the present invention also includes a static eliminator. A static eliminator is coupled between the air dryer and the test chamber. A static eliminator is used to remove static electricity from the dry air supplied to the test chamber.

Further, the cryogenic test system of the present invention includes a thermoelectrically cooled wafer and a temperature controller. The thermoelectrically cooled wafer is placed within the wafer spacer and is positioned below the wafer level integrated circuit. The temperature controller is electrically connected to the thermoelectrically cooled wafer. The temperature controller is used to control the temperature of the thermoelectrically cooled wafer to micro-control the temperature of the wafer-level integrated circuit.

Compared with the prior art, the low temperature test system of the present invention has the advantages of good performance, good temperature control, convenient operation and greatly reduced cost.

The advantages and spirit of the present invention can be further understood by the following embodiments and the drawings.

Please refer to FIG. 1 , which is a schematic structural diagram of a low temperature testing system 1 according to a preferred embodiment of the present invention.

As shown in Figure 1, the low temperature test system 1 of the present invention is used to test the wafer level product. Body circuit 2. The wafer level integrated circuit 2 includes a plurality of wafers thereon (not shown in FIG. 1). The cryogenic test system 1 of the present invention comprises a carrying fixture 11 and a crimping device 10. The cryogenic test system 1 of the present invention is the same as the existing test system for testing the wafer level integrated circuit, and includes an automation device (not shown in FIG. 1), which will not be described herein.

The carrier jig 11 includes a wafer spacer 110 and a liquid conduit 10. The wafer spacer 110 is used to fix the wafer level integrated circuit 2 and to have a plurality of wafers on the wafer level circuit 2 facing upward. The wafer spacer 110 may have a vacuum line for sucking the back surface of the wafer level integrated circuit 2 in a vacuum adsorption manner. The liquid conduit 130 is for cryogenic liquid flow and is thermally coupled to the wafer shim 110. The cryogenic liquid is heat exchanged with the wafer spacer 110 to lower the temperature of the wafer level integrated circuit 2 to a predetermined temperature.

The crimping device 10 includes a probe element 102 thereon. When the temperature of the wafer level integrated circuit 2 drops to a predetermined temperature, the crimping device 10 and/or the carrier jig 11 are moved to cause the plurality of wafers of the wafer level integrated circuit 2 to sequentially contact the probe element 102, thereby performing test. Before the test, the operator first corrects the initial coordinates of the wafer spacer 110, and the image pickup device 10 (not shown in FIG. 1) can be attached to the crimping device 10 to assist in viewing the initial coordinates of the wafer spacer 110. Since the wafer level integrated circuit 2 includes thousands or even tens of thousands of wafers thereon, and these wafers are tested one by one, the spacing between the wafers is also set. After each wafer is measured, the wafer spacers 110 are To move the distance of the gap and test the next wafer.

In one embodiment, the cryogenic liquid may be water or oil to which an antifreeze is added, or may be a refrigerant.

As also shown in FIG. 1, further, the cryogenic test system 1 of the present invention also includes a test chamber 12. The load fixture 11 and the crimping device 10 are disposed within the test chamber 12, thereby allowing the test environment within the test chamber 12 to be easily maintained at an appropriate temperature.

Also as shown in Figure 1, further, the low temperature test system 1 of the present creation A freezer 13 is included. The freezer 13 is disposed outside the test chamber 12 and is connected to the liquid conduit 130. The refrigerator 13 is for cooling the cryogenic liquid, and then transporting the cooled cryogenic liquid to the carrier jig 11 via the liquid conduit 130 for heat exchange with the wafer spacer 110. In practical applications, the liquid conduit 130 is preferably made of a polymer material resistant to the test low temperature, whereby the liquid conduit 130 can be deformed during the movement of the load fixture 11.

As also shown in FIG. 1, further, the cryogenic test system 1 of the present invention also includes a temperature sensor 14. The temperature sensor 14 is disposed on the wafer spacer 110. The temperature sensor 14 is used to sense the temperature of the wafer spacer 110.

In one embodiment, as shown in FIG. 1, liquid conduit 130 passes through wafer spacer 110. The cryogenic test system 1 of the present invention further includes a flow controller 15. The flow controller 15 is mounted at the inlet of the wafer shim 110 and is electrically connected to the temperature sensor 14. The flow controller 15 is configured to adjust the flow rate of the cryogenic liquid into the wafer spacer 110 according to the temperature sensed by the temperature sensor 14.

As also shown in FIG. 1, further, the inventive cryogenic test system 1 also includes an air dryer 16. The air dryer 16 is disposed outside the test chamber 12 and is coupled to the test chamber 12 by a gas conduit 160. The air dryer 16 is used to supply dry air to the test chamber 12 via the gas conduit 160 to ensure the safety of the wafer level integrated circuit 2.

As also shown in FIG. 1, further, the cryogenic test system 1 of the present invention also includes a static eliminator 17. A static eliminator 17 is coupled between the air dryer 16 and the test chamber 12. The static eliminator 17 serves to eliminate static electricity supplied to the dry air of the test chamber 12 to ensure the safety of the wafer level integrated circuit 2.

As also shown in FIG. 1, further, the present cryogenic test system 1 also includes a thermoelectrically cooled wafer 18 and a temperature controller 19. The thermoelectrically cooled wafer 18 is disposed within the wafer spacer 110 and is positioned below the wafer level integrated circuit 2. The pyrogenic surface of the thermoelectrically cooled wafer 18 faces the liquid conduit 130, and the cooling surface of the thermoelectrically cooled wafer 18 is in contact with the top of the wafer spacer 110. Temperature controller 19 The system is electrically connected to the thermoelectrically cooled wafer 18. The temperature controller 19 is used to control the temperature of the thermoelectrically cooled wafer 18 to micro-control the temperature of the wafer-level integrated circuit 2, and even allows the wafer-level integrated circuit 2 to be tested at -60 ° C.

With the above detailed description of this creation, I believe that it can be clearly understood that the low temperature test system of this creation has the advantages of good performance, good temperature control, convenient operation and greatly reduced cost, and even allows the wafer level integrated circuit to be in the -60 ° C environment. Test it down.

The features and spirit of the present invention are more clearly described in the above detailed description of the preferred embodiments, and the scope of the present invention is not limited by the preferred embodiments disclosed herein. On the contrary, it is intended to cover all kinds of changes and equivalences within the scope of the patent application to which the present invention is intended. Therefore, the scope of the patent scope applied for by this creation should be interpreted broadly based on the above description so that it covers all possible changes and equivalence arrangements.

1‧‧‧Cryogenic test system

10‧‧‧Crimping device

102‧‧‧ probe components

11‧‧‧bearing fixture

110‧‧‧ Wafer gasket

12‧‧‧Test room

13‧‧‧Freezer

130‧‧‧Liquid conduit

14‧‧‧Temperature Sensor

15‧‧‧Flow controller

16‧‧‧Air dryer

160‧‧‧ gas conduit

17‧‧‧Static eliminator

18‧‧‧Thermoelectric cooling chip

19‧‧‧ Temperature Controller

2‧‧‧ Wafer-level integrated circuit

1 is a schematic diagram showing the architecture of a low temperature test system according to a preferred embodiment of the present invention.

1‧‧‧Cryogenic test system

10‧‧‧Crimping device

102‧‧‧ probe components

11‧‧‧bearing fixture

110‧‧‧ Wafer gasket

12‧‧‧Test room

13‧‧‧Freezer

130‧‧‧Liquid conduit

14‧‧‧Temperature Sensor

15‧‧‧Flow controller

16‧‧‧Air dryer

160‧‧‧ gas conduit

17‧‧‧Static eliminator

18‧‧‧Thermoelectric cooling chip

19‧‧‧ Temperature Controller

2‧‧‧ Wafer-level integrated circuit

Claims (9)

A low temperature test system for testing a wafer level circuit comprising a plurality of wafers thereon, the low temperature test system comprising: a load fixture comprising: a wafer spacer Fixing the wafer-level integrated circuit with the plurality of wafers on the wafer-level integrated circuit facing upward; and a liquid conduit for circulating a cryogenic liquid and thermally coupled to the wafer spacer Wherein the cryogenic liquid exchanges heat with the wafer spacer to lower a temperature of the wafer level circuit to a predetermined temperature; and a crimping device including a probe element, wherein the wafer When the temperature of the quadrature circuit drops to the predetermined temperature, the crimping device and/or the carrying fixture move the plurality of wafers of the wafer level circuit to sequentially contact the probe element for testing . The cryogenic test system of claim 1, further comprising: a test chamber, the load fixture and the crimping device being disposed in the test chamber. The cryogenic test system of claim 2, further comprising: a freezer disposed outside the test chamber and coupled to the liquid conduit for cooling the cryogenic liquid. The cryogenic test system of claim 3, wherein the cryogenic liquid system is a water or oil to which an antifreeze is added, or is a refrigerant. The cryogenic test system of claim 3, further comprising: a temperature sensor disposed on the wafer spacer for sensing a temperature of the wafer spacer. The cryogenic test system of claim 5, wherein the liquid conduit passes through the wafer spacer, the cryogenic test system further comprising: a flow controller mounted at an inlet of the liquid conduit to one of the wafer pads and electrically connected to the temperature sensor for adjusting the cryogenic liquid according to the temperature sensed by the temperature sensor The flow into the wafer shim. The cryogenic test system of claim 3, further comprising: a thermoelectrically cooled wafer disposed in the wafer spacer and located below the wafer level integrated circuit; and a temperature controller Connected to the thermoelectrically cooled wafer for controlling the temperature of the thermoelectrically cooled wafer to micro-control the temperature of the wafer-level integrated circuit. The cryogenic test system of claim 3, further comprising: an air dryer disposed outside the test chamber and connected to the test chamber by a gas conduit for supplying a dry air to the gas conduit Test room. The cryogenic test system of claim 8, further comprising: a static eliminator coupled between the air dryer and the test chamber for eliminating static electricity supplied to the dry air of the test chamber.