TWM450110U - Electronic application apparatus and master terminal connection seat connected thereof - Google Patents

Description

Electronic application device and its connected main control terminal

The present invention relates to an electronic application device and a connection terminal of the connection thereof, and more particularly to an electronic application device and a host terminal connected to transmit serial (SATA) data.

The ATA interface is an interface specification for an electronic application device (such as a flash memory card CF or a solid-state hard disk SSD), which is applied to a computer system and is mainly used as an internal electronic application device and a circuit board ( The interface between the motherboards, for example. In the past, most ATA interfaces used Parallel ATA (PATA or IDE) interface. However, due to the limitation of PATA interface transmission bandwidth, the Serial ATA (SATA) interface with high transmission performance gradually replaces the traditional PATA interface.

Although the SATA interface has the advantage of higher transmission performance than the PATA interface, there are still some shortcomings, so many industrial controllers or system vendors are still willing to choose the PATA interface as the main transmission interface of the electronic application device, as described below. :

(1). The SATA interface connector/connector is much more expensive than the PATA interface connector/connector, and the circuit design is more complicated.

(2). The standard SATA interface is standardized as a single-sided contact design. As shown in FIG. 1, the electronic application device 110 and the circuit board 120 connected to each other by the SATA interface 111/121 are susceptible to short-term separation or fall-off due to vibration of an external force, resulting in an error or loss of the transmitted signal data. Here, the single-sided contact SATA interface is less stable than the pin-type PATA interface.

In addition, in order to achieve the purpose of both SATA and PATA data transmission, the main control terminal of SATA and PATA interfaces can also be provided on the circuit board and/or the motherboard to provide the SATA interface. The connector or the electronic application device using the connector of the PATA interface is connected. However, in this way, the board will increase the cost of a master terminal block, which is very disadvantageous for circuit board or motherboard manufacturers.

One of the purposes of the present invention is to provide an electronic application device and a connection terminal thereof. The electronic application device includes a PATA interface connector, and the main control terminal is a PATA interface that can be mounted on the circuit board. The connector, the electronic application device and the circuit board are connected through the PATA interface connector and the connector, and transmit the SATA data through the PATA interface.

One of the aims of the present invention is to provide a master terminal connector, which uses a PATA interface as a connection interface between an electronic application device and a master terminal connector, and the circuit board can be inserted into the PATA specification through a flexible selection of the host connector. Electronic application devices or SATA-sized electronic applications without changing the design of the board.

One of the purposes of the present invention is to provide an electronic application device in which the PATA interface connector and the connector base are constructed by a pin jack/pin type pin. When the connector is inserted into the connector, each pin position It will have an omnidirectional contact to increase the stability between the connector and the connector, thereby improving the stability of data transmission.

To achieve the above object, the present invention provides an electronic application device comprising: a controller; at least one electronic component for storing data or an electronic application function; and a connector which is a side-by-side (PATA) interface connector , the connector of the plurality of connector pins can be divided into a real IDE The connector pin of the mode and the connector pin of the non-authentic IDE mode, wherein: the connector pin of the real IDE mode has a plurality of pins, which conforms to the specification of the parallel protocol (PATA) transmission protocol; The connector pin of the real IDE mode has a plurality of pins that conform to the specifications of the tandem (SATA) transport protocol, and the electronic application device transmits the at least one tandem using the connector pins of the non-real IDE mode. (SATA) information.

In an embodiment of the present invention, the connector is a standard connector defined by a Compact Flash Association, and the number of pins is fifty.

In an embodiment of the present invention, the connector pin is a pin jack or a pin pin.

In an embodiment of the present invention, the SATA data pin of the plurality of connectors is defined in the connector pin of the non-real IDE mode, and the electronic application device uses the SATA data pin of the connector to transmit the SATA data.

In an embodiment of the present invention, the SATA data pin of the connector includes a TX+ positive data pin, a TX-negative data pin, a RX+ positive data pin, and an RX-negative data pin. The order in which the SATA data pins are defined is chosen to comply with the specifications of the SATA protocol or different from the specifications of the SATA protocol.

In an embodiment of the present invention, the electronic application device is connected to a main control terminal through the connector, and the main control terminal is disposed on a circuit board and is a side-by-side (PATA) interface connector. The plurality of connection bases of the main control terminal can be divided into a real IDE mode connection pin and a non-real IDE mode connection pin, wherein: the real IDE mode connection pin has a plurality of The pin is a specification conforming to the PATA transfer protocol; and the non-real IDE mode pin has a plurality of pins that conform to the tandem (SATA) transport protocol. The specification device; the electronic application device and the circuit board transmit the serial (SATA) data by using the non-real IDE mode connector pin and the non-real IDE mode connection pin.

The present invention further provides a main control terminal connector, which is disposed on a circuit board, and the main control terminal connection seat is a side-by-side (PATA) interface connection seat, and the plurality of connection seat pins of the main control terminal connection seat can be divided into one The connection position of the real IDE mode and the connection position of a non-authentic IDE mode, wherein: the connection pin of the real IDE mode has a plurality of pins, which conforms to the specification of the parallel protocol (PATA) transmission protocol; And the non-real IDE mode connection pin has a plurality of pins, which conforms to the specification of the serial (SATA) transmission protocol, and the circuit board uses at least one serial port of the non-real IDE mode to transmit at least one series. (SATA) data.

In an embodiment of the present invention, the master terminal is a standard connector defined by a Compact Flash Association, and the number of pins is fifty.

In an embodiment of the present invention, the connecting seat is a pin jack or a pin pro.

In an embodiment of the present invention, the SATA data pin of the plurality of connectors is defined in the connection pin of the non-real IDE mode, and the circuit board uses the SATA data pin of the connector to transmit the SATA data.

In an embodiment of the present invention, the SATA data pin of the connector includes a TX+ positive data pin, a TX-negative data pin, a RX+ positive data pin, and an RX-negative data pin. The order in which each SATA data pin is defined is selected to conform to the specifications of the SATA protocol or to the specifications of the SATA protocol.

Referring to FIG. 2, FIG. 3 and FIG. 4, a schematic diagram of a three-dimensional structure, a schematic diagram of a pin position and a circuit structure of a preferred embodiment of the electronic application device and its connection main control terminal are shown. As shown, the electronic application device 60 (such as a flash memory card CF, a solid state drive SSD, a general hard disk HDD or other storage device) is a SATA-sized electronic application device including a connector 61 and a A Serial ATA (SATA) controller 62 and a plurality of storage elements or other electronic components 64 can be used to store data or other electronic application functions. The connector 61 and the electronic component 64 are respectively connected to the controller 62. The main control device or the host device 70 (such as a computer system, a digital camera, a mobile phone) includes a main control terminal 71 and a control unit 73. The main control connector 71 can be mounted on a circuit board (or a circuit board). On the motherboard 700, the control unit 73 can be used to process SATA type data or PATA type data. The electronic application device 60 and the circuit board 700 transmit data between the two through the connector 61 and the main control terminal 71.

The connector 61 and the main control terminal 71 are respectively a Parallel ATA (PATA or IDE) interface connector and a PATA interface connector, and the appearance dimensions thereof conform to a standard specification defined by a Compact Flash Association. The number of connector pins 611 / connector pins 711 is 50.

Referring further to Table 1, the pin definition table of an embodiment of the authoring connector and the connector is shown.

As described above, the authoring connector 61 and the master terminal connector 71 are PATA interfaces, and in order to comply with the specifications of the general PATA transmission protocol, Most of the connector pin 611 and the connector pin 711 of the connector 61 and the main control connector 71 are still defined as a plurality of pins for a true IDE mode, for example: 2nd The ~6, 21~23, 27~31, 47~49 pins are defined as PATA data pins, the 13th and 38th pins are defined as PATA power pins, and the first and 50th pins are defined as PATA ground pins...etc. Wait. In other words, the pin of the real IDE mode is used to transmit the relative position of the PATA data.

The connector pin 611 and the connector pin 711 of the author connector 61 and the connector pad 711 further include a plurality of pins 611 and 711 which are not in the real IDE mode (not defined as the real IDE mode). (For example, the 8th to 12th pins, the 14th to 17th pins, the 36th pin, etc., the ten pins), the non-real IDE mode pins 611, 711 are used to transmit at least one SATA data.

In the embodiment of the creation table 1, the 10th, 11th, 15th, and 16th pins are selected as the SATA data pins in the non-real IDE mode pins 611 and 711, and the specifications of the SATA communication protocol are complied with. For example, it is defined that the 10th pin is the positive data pin of Tx+, the 11th pin is the negative data pin of Tx-, the 15th pin is the positive data pin of Rx+, and the 16th pin is the negative of Rx-. Information pin.

Moreover, in the embodiment of the creation table 1, a part of the pin can be further defined as the SATA ground pin in the non-PATA mode pins 611 and 711. For example, define the 9th, 12th, 14th, and 17th pins as the SATA ground pin (GND). Thus, by the SATA grounding pin setting, when the connector 61 is inserted into the main control terminal 71, the electromagnetic signal on the circuit board 700 can be prevented from being interfered with the transmission between the electronic application device 60 and the circuit board 700. SATA information.

In addition, as shown in Table 2, in another embodiment of the present creation, the 8th, 9th, 10th, 11th, and 12th pins can be continuously selected as the SATA data feet in the non-real IDE mode pins 611 and 711. Bit and SATA ground pin, and comply with the SATA protocol. For example, the 8th pin is defined as the positive data pin of Tx+, the 9th pin is the negative data pin of Tx-, the 11th pin is the positive data pin of Rx+, and the 12th pin is the negative of Rx-. The data pin is defined, and the 10th pin is defined as the ground pin.

Or, as shown in Table 3, in another embodiment of the present invention, the 9th, 10th, 15th, and 16th pins are selected as the SATA data pins in the non-real IDE mode pins 611 and 711, and may be different from SATA. The specification of the communication protocol defines that the 9th pin is the negative data pin of Rx-, the 10th pin is the positive data pin of Rx+, the 15th pin is the negative data pin of Tx- and the 16th pin is Tx+. The positive data pin, and the 8th, 11th, 14th, and 17th pins are defined as the SATA ground pin (GND).

Table 1, Table 2 or Table 3 mentioned above is only an embodiment of this creation. Of course, the circuit-related designer can also use the non-real IDE mode pins 611 and 711 according to the actual consideration of the circuit wiring (for example, the 8th to 12th pins, the 14th to the 17th and the 36th). Defining any pin is SATA data pin or SATA ground pin.

Referring again to FIG. 4, the PATA interface connector 61 and the SATA controller 62 further include a wiring pin area 613, and the PATA interface main control terminal 71 and the control unit 73 further include another wiring pin. Area 713 . The respective connector pins 611 of the PATA interface connector 61 are routed to the SATA controller 62 through the single row wiring pins in the wiring pin region 613, as shown in FIG. The respective connection pins 711 of the PATA interface master terminal 71 are routed to the control unit 73 through the two-row routing pins in the wiring pin region 713, as shown in FIG.

Here, when the SATA-sized electronic application device 60 is inserted into the PATA interface (master) connection base 71 of the host device 70 through the PATA interface connector 61, the electronic application device 60 and the host device 70/the circuit board 700 can be The SATA data is transmitted through the PATA interface connector 61 and the SATA data pins (such as pins 10, 11, 15, and 16) defined in the console connector 71.

Therefore, the electronic application device 60 of the SATA specification is connected to the circuit board 700 by using a PATA interface, and can also achieve the purpose of SATA data transmission. Moreover, the PATA connection interface has a lower price advantage than the SATA connection interface, thereby reducing the manufacturing cost of the electronic application device 60 or the circuit board 700.

Referring again to FIG. 2, the connector pin 611 of the PATA interface connector 61 is a pin jack or a pin stud. The connector pin 711 of the master connector 71 is a corresponding one. The configuration of the pin or pin jack. With the pin-type configuration of the PATA interface, when the connector 61 is inserted into the main control terminal 71, each pin will have an omnidirectional contact to increase the connection between the connector 61 and the main control terminal 71. Stable, thereby improving the stability of SATA data transmission.

Please refer to FIG. 7 , which is a schematic diagram of a circuit structure of another embodiment of the electronic application device and the connected main control terminal of the present invention. As shown in the figure, the embodiment further provides a PATA specification electronic application device 80, which The electronic application device 80 includes a PATA interface connector 61, a PATA controller 82, and a plurality of storage elements or other electronic components 84. The PATA interface connector 61 is routed to the PATA controller 82 through a wiring pin area 613. Each storage element or other electronic component 84 is coupled to a PATA controller 82, respectively. The PATA-compliant electronic application device 80 can be inserted into the main control terminal connector 71 of the circuit board 700 through the PATA interface connector 61, and the PATA data can be transmitted.

According to the implementation, the circuit board 700 of the present invention can be flexibly selected to be inserted into a SATA-sized electronic application device 60 or another PATA-sized electronic application device 80 through a single master terminal connector 71 without The design of the circuit board is altered to reduce the component cost of the board 700 for data transfer purposes.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the shape, structure, characteristics and spirit described in the scope of the patent application are equally changed. Modifications shall be included in the scope of the patent application of this creation.

110‧‧‧Electronic application device

111‧‧‧ SATA interface

120‧‧‧ boards

121‧‧‧ SATA interface

60‧‧‧Electronic application device

61‧‧‧Connector

611‧‧‧Connector feet

613‧‧‧Wiring pin area

62‧‧‧ SATA controller

64‧‧‧Electronic components

70‧‧‧ host device

700‧‧‧ boards

71‧‧‧Master terminal connector

711‧‧‧Connected seat

713‧‧‧Wiring pin area

73‧‧‧Control unit

80‧‧‧Electronic application device

82‧‧‧PATA controller

84‧‧‧Electronic components

Fig. 1 is a schematic enlarged view of a three-dimensional structure in which a SATA interface is used between a conventional electronic application device and a motherboard.

Figure 2: Schematic diagram of the three-dimensional structure of the electronic application device and its connected main control terminal.

Figure 3: Schematic diagram of the structure of the connector of the author and the connector.

Fig. 4 is a schematic view showing the circuit structure of a preferred embodiment of the electronic application device and its connected main control terminal.

Figure 5: The structure of the connector of the author is a single-row wiring pin for the layout of the circuit.

Figure 6: Schematic diagram of the layout of the line of the creative connection block using double-row wiring pins.

Fig. 7 is a schematic view showing the circuit structure of still another embodiment of the electronic application device of the present invention and its connected main control terminal.

60‧‧‧Electronic application device

61‧‧‧Connector

613‧‧‧Wiring pin area

62‧‧‧ SATA controller

64‧‧‧Electronic components

70‧‧‧ host device

700‧‧‧ boards

71‧‧‧Master terminal connector

713‧‧‧Wiring pin area

73‧‧‧Control unit

Claims (10)

An electronic application device comprising: a controller; at least one electronic component connected to a controller for storing data or an electronic application function; and a connector connected to the controller, which is a side-by-side (PATA) interface connector The plurality of connector pins of the connector can be divided into a connector pin of a real IDE mode and a connector pin of a non-real IDE mode, wherein: the connector pin of the real IDE mode has a plurality of pins , which conforms to the specification of the Parallel (PATA) Transmission Agreement; and the connector pin of the non-authentic IDE mode has a plurality of pins, which conforms to the specifications of the Tandem (SATA) transmission protocol, and the electronic application device utilizes A non-real IDE mode connector pin transmits at least one serial (SATA) data. The electronic application device of claim 1, wherein the electronic application device is connected to a main control terminal through the connector, and the main control terminal is disposed on a circuit board and is a side-by-side (PATA) The interface connector, the plurality of connector pins of the main control connector can be divided into a real IDE mode connector pin and a non-real IDE mode connector pin, wherein: the real IDE mode connector The pin has a plurality of pins, which conforms to the specification of the parallel protocol (PATA) transmission protocol; and the non-real IDE mode connection pin has a plurality of pins, which conforms to the specification of the tandem (SATA) transmission protocol. The non-real IDE mode is utilized between the electronic application device and the circuit board The connector pin and the non-real IDE mode connector pin transmit the serial (SATA) data. The electronic application device of claim 1, wherein the connector is a standard connector defined by a Compact Flash Association, and the number of pins is fifty. The electronic application device of claim 1, wherein the non-real IDE mode connector pin defines a plurality of connector SATA data pins, and the electronic application device utilizes the SATA data pin of the connector To transfer the SATA data. The electronic application device of claim 4, wherein the SATA data pin of the connector comprises a TX+ positive data pin, a TX-negative data pin, and a RX+ positive data pin. RX-'s negative data pin, the SATA data pin is defined in the order of choice to comply with the SATA protocol or different from the SATA protocol. A main control terminal is disposed on a circuit board and connected to a control unit. The main control terminal is a parallel (PATA) interface connector, and the control unit connects the plurality of connection pins in the main control terminal. The bit is divided into a real IDE mode connector pin and a non-real IDE mode connector pin. The non-real IDE mode connector pin is not in the plurality of connector pins of the master connector. The connector pin defined as the real IDE mode, wherein: the connection pin of the real IDE mode has a plurality of pins, which conforms to the specification of the parallel protocol (PATA) transmission protocol; and the connection leg of the non-real IDE mode The bit has a plurality of pins, which conforms to the specification of the tandem (SATA) transport protocol, and the circuit board utilizes non- The connector of the real IDE mode transmits at least one serial (SATA) data. The master terminal is described in claim 6, wherein the master connector is a standard connector defined by a Compact Flash Association, and the number of pins is fifty. The main control terminal of claim 6, wherein the connection pin is a pin jack or a pin pro. For example, the main control terminal connector described in claim 6 wherein the non-real IDE mode connection pin defines a plurality of SATA data pins of the connector, and the circuit board utilizes the SATA data pin of the connector. Bit to transfer the SATA data. For example, the main control terminal connector described in claim 9 wherein the SATA data pin of the connector includes a TX+ positive data pin, a TX-negative data pin, and a RX+ positive data pin. The RX-'s negative data pin, the SATA data pin is defined in the order of choice to comply with the SATA protocol or different from the SATA protocol.