TWM449341U - A fault signal detecting circuit - Google Patents
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本創作涉及一種信號故障檢測電路。
This creation relates to a signal failure detection circuit.
隨著人們生活品質的不斷提高，各種新型的電子、電器產品不斷湧現，對於電子類產品設備的保護也越來越重要，因此，在電子電路設計時，都需要對一些異常情況進行監測，當出現異常時，能夠及時的進行保護。
很多電路都使用脈衝變壓器進行驅動信號的傳遞，這樣可以保證高低壓的隔離，使電路可靠工作，而脈衝變壓器傳遞的都是脈衝信號，當脈衝信號出現異常，故障信號從脈衝變壓器的副邊傳遞給原邊再傳遞給主控制部分，主控制部分進行相應處理，而主控制部分對於故障信號的處理比較慢。這樣的處理方式回應速度慢，對回應速度有苛刻要求的場合，此處理方法並不適用。
With the continuous improvement of people's quality of life, various new types of electronic and electrical products continue to emerge, and the protection of electronic products and equipment is becoming more and more important. Therefore, in the design of electronic circuits, it is necessary to monitor some abnormal conditions. When an abnormality occurs, it can be protected in time.
Many circuits use a pulse transformer to transmit the drive signal, which ensures high and low voltage isolation and reliable operation of the circuit. The pulse transformer transmits pulse signals. When the pulse signal is abnormal, the fault signal is transmitted from the secondary side of the pulse transformer. The primary side is passed to the main control part, and the main control part performs corresponding processing, while the main control part processes the fault signal relatively slowly. This kind of processing method is not applicable when the response speed is slow and the response speed is critical.
針對目前電路中對於脈衝信號故障處理回應速度慢的問題，本創作提供一種信號故障檢測電路，能夠對故障信號進行快速響應。
一種信號故障檢測電路，包括：脈衝變壓器、用於控制驅動信號的信號處理單元、用於根據驅動信號生成高電平信號以及根據故障信號生成高電平信號的高電平生成單元、用於根據驅動信號生成低電平信號的低電平生成單元，以及根據高電平生成單元輸出的信號和低電平生成單元輸出的信號監測故障信號、記憶故障信號和控制信號處理單元封鎖驅動信號的故障監測記憶單元，所述信號處理單元分別與高電平生成單元和低電平生成單元的輸入端相連，所述高電平生成單元的輸入端還與脈衝變壓器的原邊相連，高電平生成單元和低電平生成單元的輸出端均與故障監測記憶單元的輸入端相連，故障監測記憶單元的輸出端與信號處理單元相連。
進一步地，所述信號處理單元包括第一反及閘、第一二極體、第一低壓電源以及第一電阻，所述第一反及閘包括第二輸入端和用於輸入驅動信號的第一輸入端，第一反及閘的第二輸入端與第一二極體的陽極相連，第一二極體的陰極與故障監測記憶單元的輸出端相連，所述第一電阻的一端與第一二極體的陽極相連，第一電阻的另一端與第一低壓電源相連。
進一步地，所述信號故障檢測電路還包括用於增強驅動信號的推挽單元，所述推挽單元包括推挽電路、第一電容、第二電容、第一反相器、第二反相器以及第二電阻，所述第二電阻的一端與第一反及閘的輸出端相連，第二電阻的另一端與第一反相器的輸入端相連，第一反相器的輸出端與第二反相器的輸入端相連，所述第二反相器的輸出端與推挽電路的輸入端相連，推挽電路的輸出端與第一電容的一端相連，第一電容的另一端與脈衝變壓器的原邊相連，第二電容的一端連接於第二電阻和第一放大器之間，第二電容的另一端與推挽電路的輸出端相連。
進一步地，所述高電平生成單元包括穩壓管、第三電阻、第四電阻、第五電阻、第一三極管、第二低壓電源以及第三電容，所述穩壓管的陽極與第一電容的另一端相連，穩壓管的陰極與第三電阻的一端相連，第三電阻的另一端與第一三極管的基極相連，所述第一三極管的發射極與第二低壓電源相連，第一三極管的集電極與第五電阻的一端以及故障監測記憶模組相連，第五電阻的另一端接地，所述第四電阻的一端與第一三極管的基極相連，第四電容的另一端與第二低壓電源相連，所述第三電容的一端與第二低壓電源相連，第三電容的另一端接地。
進一步地，所述低電平生成單元包括第二反及閘、第三反及閘、第四電容、第五電容、第二二極體、第三二極體、第四二極體、第六電阻、第七電阻、第八電阻、第三低壓電源以及第四低壓電源，所述第二二極體的陰極與第三二極體的陰極相連，所述第二二極體和第三二極體的陽極分別與第六電阻和第七電阻的一端相連，第六電阻和第七電阻的另一端與第三低壓電源相連，第二反及閘的第一輸入端與第五電容的一端相連，第五電容的另一端與第一反及閘的輸出端相連，第二反及閘的第二輸入端與第三二極體的陽極相連，第二反及閘的輸出端與第三反及閘的輸入端相連，第三反及閘的輸出端與第四二極體的陰極相連，第四二極體的陽極與第八電阻的一端相連，第八電阻的另一端與第四低壓電源相連，第四電容的一端與第二反及閘的第二輸入端相連，第四電容的另一端與第三反及閘的輸出端相連。
進一步地，所述故障監測記憶單元包括第四反及閘、第五反及閘、第九電阻、第十電阻、第十一電阻、第五二極體、第三反相器、第五低壓電源以及第六低壓電源，所述第四反及閘的第一輸入端與第一三極管的集電極相連，第四反及閘的第二輸入端與第五二極體的陽極相連，第四反及閘的輸出端與第五反及閘的第一輸入端相連，第五反及閘的第二輸入端與第九電阻的一端相連，第九電阻的另一端與第五低壓電源相連，所述第五反及閘的輸出端與第五二極體的陽極相連，第五二極體的陰極與第一三極管的集電極相連，第五反及閘的輸出端還與第三反相器的輸入端相連，第三反相器的輸出端為故障監測記憶模組的輸出端，第十電阻的一端與第三放大器的輸出端相連，第十電阻的另一端與第六低壓電源相連，第十一電阻的一端與第三反相器的輸入端相連，第十一電阻的另一端接地。
本創作提供的一種信號故障檢測電路，高電平生成單元和低電平生成單元根據驅動信號分別生成高電平信號和低電平信號，故障監測記憶單元根據高電平生成單元輸出的信號和低電平生成單元輸出的信號監測是否有故障信號，如果產生故障信號則記憶故障信號，並在主控制部分作出回應之前封鎖驅動信號，回應速度快，適用於對回應速度有苛求的場合。
In view of the current slow response to pulse signal fault processing in the circuit, the present invention provides a signal fault detection circuit capable of responding quickly to a fault signal.
A signal fault detecting circuit comprising: a pulse transformer, a signal processing unit for controlling a driving signal, a high level generating unit for generating a high level signal according to the driving signal, and generating a high level signal according to the fault signal, for a low-level generating unit that generates a low-level signal by the driving signal, and a fault of the fault signal, the memory fault signal, and the control signal processing unit to block the driving signal according to the signal output by the high-level generating unit and the signal output by the low-level generating unit Monitoring a memory unit, wherein the signal processing unit is respectively connected to an input end of the high level generating unit and the low level generating unit, and the input end of the high level generating unit is further connected to the primary side of the pulse transformer, and the high level is generated. The output ends of the unit and the low level generating unit are connected to the input end of the fault monitoring memory unit, and the output end of the fault monitoring memory unit is connected to the signal processing unit.
Further, the signal processing unit includes a first reverse gate, a first diode, a first low voltage power supply, and a first resistor, and the first reverse gate includes a second input terminal and a first input signal for inputting a driving signal An input end, the second input end of the first anti-gate is connected to the anode of the first diode, and the cathode of the first diode is connected to the output end of the fault monitoring memory unit, one end of the first resistor and the first The anode of one diode is connected, and the other end of the first resistor is connected to the first low voltage power source.
Further, the signal fault detecting circuit further includes a push-pull unit for enhancing a driving signal, the push-pull unit including a push-pull circuit, a first capacitor, a second capacitor, a first inverter, and a second inverter And a second resistor, one end of the second resistor is connected to the output end of the first anti-gate, and the other end of the second resistor is connected to the input end of the first inverter, and the output end of the first inverter The input ends of the two inverters are connected, the output end of the second inverter is connected to the input end of the push-pull circuit, the output end of the push-pull circuit is connected to one end of the first capacitor, and the other end of the first capacitor is pulsed The primary side of the transformer is connected, one end of the second capacitor is connected between the second resistor and the first amplifier, and the other end of the second capacitor is connected to the output end of the push-pull circuit.
Further, the high level generating unit includes a Zener diode, a third resistor, a fourth resistor, a fifth resistor, a first triode, a second low voltage power source, and a third capacitor, and the anode of the Zener tube The other end of the first capacitor is connected, the cathode of the Zener tube is connected to one end of the third resistor, and the other end of the third resistor is connected to the base of the first transistor, the emitter of the first transistor and the first The low voltage power supply is connected, the collector of the first triode is connected to one end of the fifth resistor and the fault monitoring memory module, and the other end of the fifth resistor is grounded, and one end of the fourth resistor and the base of the first triode The other end of the fourth capacitor is connected to the second low voltage power supply, one end of the third capacitor is connected to the second low voltage power supply, and the other end of the third capacitor is grounded.
Further, the low level generating unit includes a second reverse gate, a third reverse gate, a fourth capacitor, a fifth capacitor, a second diode, a third diode, a fourth diode, and a a sixth resistor, a seventh resistor, an eighth resistor, a third low voltage power source, and a fourth low voltage power source, the cathode of the second diode being connected to the cathode of the third diode, the second diode and the third The anodes of the diodes are respectively connected to one ends of the sixth resistor and the seventh resistor, and the other ends of the sixth resistor and the seventh resistor are connected to the third low voltage power source, and the first input terminal and the fifth capacitor of the second back gate are connected One end is connected, the other end of the fifth capacitor is connected to the output end of the first anti-gate, the second input end of the second anti-gate is connected to the anode of the third diode, and the output end of the second anti-gate The input end of the third reverse gate is connected, the output end of the third reverse gate is connected to the cathode of the fourth diode, the anode of the fourth diode is connected to one end of the eighth resistor, and the other end of the eighth resistor Four low voltage power supplies are connected, one end of the fourth capacitor is connected to the second input end of the second reverse gate, The other end of the four capacitors is connected to the third output terminal of the NAND gate.
Further, the fault monitoring memory unit includes a fourth reverse gate, a fifth reverse gate, a ninth resistor, a tenth resistor, an eleventh resistor, a fifth diode, a third inverter, and a fifth low voltage. a power source and a sixth low voltage power supply, wherein the first input end of the fourth reverse gate is connected to the collector of the first transistor, and the second input end of the fourth reverse gate is connected to the anode of the fifth diode The output end of the fourth reverse gate is connected to the first input end of the fifth reverse gate, the second input end of the fifth reverse gate is connected to one end of the ninth resistor, and the other end of the ninth resistor and the fifth low voltage power supply Connected, the output of the fifth anti-gate is connected to the anode of the fifth diode, the cathode of the fifth diode is connected to the collector of the first transistor, and the output of the fifth anti-gate is also The input end of the third inverter is connected, the output end of the third inverter is the output end of the fault monitoring memory module, one end of the tenth resistor is connected to the output end of the third amplifier, and the other end of the tenth resistor is Six low voltage power supplies are connected, one end of the eleventh resistor is connected to the input end of the third inverter The other end of the eleventh resistor.
A signal fault detecting circuit provided by the present invention, the high level generating unit and the low level generating unit respectively generate a high level signal and a low level signal according to the driving signal, and the fault monitoring memory unit outputs a signal according to the high level generating unit and The signal output by the low-level generating unit monitors whether there is a fault signal. If the fault signal is generated, the fault signal is memorized, and the driving signal is blocked before the main control portion responds, and the response speed is fast, which is suitable for the occasion where the response speed is demanding.
為了使本創作所解決的技術問題、技術方案及有益效果更加清楚明白，以下結合附圖及實施例，對本創作進行進一步詳細說明。應當理解，此處所描述的具體實施例僅僅用以解釋本創作，並不用於限定本創作。
如附第1圖所示，一種信號故障檢測電路，包括脈衝變壓器T，還包括用於控制驅動信號的信號處理單元4、用於根據驅動信號生成高電平信號以及根據故障信號生成高電平信號的高電平生成單元1、用於根據驅動信號生成低電平信號的低電平生成單元2，以及根據高電平生成單元1輸出的信號和低電平生成單元2輸出的信號監測故障信號、記憶故障信號和控制信號處理單元4封鎖驅動信號的故障監測記憶單元3，信號處理單元3分別與高電平生成單元1和低電平生成單元2的輸入端相連，高電平生成單元1的輸入端還與脈衝變壓器T的原邊相連，高電平生成單元1和低電平生成單元2的輸出端均與故障監測記憶單元3的輸入端相連，故障監測記憶單元3的輸出端與信號處理單元2相連。
驅動信號從脈衝變壓器T的原邊傳遞到副邊，再傳遞給其他電路，而故障信號則從脈衝變壓器T的副邊傳遞到原邊。
信號處理單元包括第一反及閘U1、第一二極體D1、第一低壓電源V1以及第一電阻R1，第一反及閘U1的第一輸入端用於輸入驅動信號，第一反及閘U1的第二輸入端與第一二極體D1的陰極相連，第一二極體D1的陰極與故障監測記憶單元3的輸出端相連，第一電阻R1的一端與第一二極體D1的陽極相連，第一電阻R1另一端與第一低壓電源V1相連。
當第一反及閘U1的第二輸入端為高電平時，驅動信號才能通過第一反及閘U1傳遞給後續的單元。
信號故障檢測電路還包括用於增強驅動信號的推挽單元5，推挽單元5包括推挽電路、第一電容C1、第二電容C2、第一反相器UD1、第二反相器UD2以及第二電阻R2，第二電阻R2的一端與第一反及閘U1的輸出端相連，第二電阻R2的另一端與第一反相器UD1的輸入端相連，第一反相器UD1的輸出端與第二反相器UD2的輸入端相連，第二反相器UD2的輸出端與推挽電路的輸入端相連，推挽電路的輸出端與第一電容C1的一端相連，第一電容C1的另一端與脈衝變壓器T的原邊相連，第二電容C2的一端連接於第二電阻R2和第一放大器之間，第二電容C2的另一端與推挽電路的輸出端相連，所述推挽電路由第二三極管Q2和第三三極管Q3組成。
驅動信號從第一反及閘的第一輸入端輸入，經過推挽電路，增加驅動能力，並傳遞到脈衝變壓器T的原邊以及高電平生成單元1。
高電平生成單元1包括穩壓管D2、第三電阻R3、第四電阻R4、第五電阻R5、第一三極管Q1、第二低壓電源V2以及第三電容C3，穩壓管D2的陽極與第一電容C1的另一端相連，穩壓管D2陰極與第三電阻R3的一端相連，第三電阻R3的另一端與第一三極管Q1的基極相連，第一三極管Q1的發射極與第二低壓電源V相連，第一三極管Q1的集電極與第五電阻R5的一端以及故障監測記憶單元3相連，第五電阻R5的另一端接地，第四電阻R4的一端與第一三極管Q1的基極相連，第四電阻R4的另一端與第二低壓電源V2相連，第三電容C3的一端與第二低壓電源V2相連，第三電容C3的另一端接地。
高電平生成單元1生成高電平信號：驅動信號為正負脈衝，經過穩壓管D2、對應在驅動信號每個週期的下降沿時刻，第一三極管Q1導通，在第一三極管Q1的集電極產生一個窄寬度的高電平，此高電平的寬度可以通過設置第三電阻R3、第四電阻R4的相關參數設定。
低電平生成單元2包括第二反及閘U2、第三反及閘U3、第四電容C4、第五電容C5、第二二極體D3、第三二極體D4、第四二極體D5、第六電阻R6、第七電阻R7、第八電阻R8、第三低壓電源V3以及第四低壓電源V4，第兒二極體D3的陰極與第三二極體D4的陰極相連，第二二極體D3和第三二極體D4的陽極分別與第六電阻R6和第七電阻R7的一端相連，第六電阻R6和第七電阻R7的另一端與第三低壓電源V3相連，第二反及閘U2的第一輸入端與第五電容C5的一端相連，第五電容C5的另一端與第一反及閘U1的輸出端相連，第二反及閘U2的第二輸入端與第三二極體D4的陽極相連，第二反及閘U2的輸出端與第三反及閘U3的輸入端相連，第三反及閘U3的輸出端與第四二極體D5的陰極相連，第四二極體D5的陽極與第八電阻R8的一端相連，第八電阻R8的另一端與第四低壓電源V4相連，第四電容C4的一端與第二反及閘U2的第二輸入端相連，第四電容C4的另一端與第三反及閘U3的輸出端相連，其中第三反及閘U3還可以為反閘。
低電平生成單元2生成低電平信號：在驅動信號的每個下降沿時刻，驅動信號經過第五電容C5，根據電容兩端電壓不能突變的原理，在第二反及閘U2的第一輸入端產生一個低電平脈衝，則第二反及閘的輸出端輸出一個高電平脈衝，再經過第三反及閘U3翻轉，在第四二極體D5的陰極產生一個低電平脈衝，此低電平的脈衝可以根據第六電阻R6、第七電阻R7以及第四電容C4的相關參數設定。
故障監測記憶單元3包括第四反及閘U4、第五反及閘U5、第九電阻R9、第十電阻R10、第十一電阻R11、第五二極體D6、第三反相器UD3、第五低壓電源V5以及第六低壓電源V6，第四反及閘U4的第一輸入端與第一三極管Q1的集電極相連，第四反及閘U4的第二輸入端與第四二極體D5的陽極相連，第四反及閘U4的輸出端與第五反及閘U5的第一輸入端相連，第五反及閘U5的第二輸入端與第九電阻R9的一端相連，第九電阻R9的另一端與第五低壓電源V5相連，第五反及閘U5的輸出端與第五二極體D6的陽極相連，第五二極體D6的陰極與第一三極管Q1的集電極相連，第五反及閘U5的輸出端還與第三反相器UD3的輸入端相連，第三反相器UD3的輸出端為故障監測記憶單元3的輸出端，第十電阻R10的一端與第三反相器UD3的輸出端相連，第十電阻R10另一端與第六低壓電源V6相連，第十一電阻R11的一端與第三反相器UD3的輸入端相連，第十一電阻R11另一端接地，其中，第五反及閘U5還可以為反閘。
如附第4圖所示，正常情況下，高電平生成單元1和低電平生成單元2所生成的高、低電平在時序上是對稱的，但有一定的延時，低電平的信號寬度略大於高電平信號，低電平信號和高電平信號分別進入第四反及閘U4的第一輸入端和第二輸入端，根據邏輯關係可知，第四反及閘U4的輸出端一直為高電平，當有故障信號出現時，故障信號從脈衝變壓器T的副邊傳遞到原邊，經過高電平生成模組1，這樣，在一個週期內就會多出一個窄寬度的高電平信號，則第四反及閘U4的輸出端就會輸出一個低電平信號，此低電平信號經過第五反及閘U5翻轉成高電平信號並通過第五二極體D6回饋到第四反及閘U4的第一輸入端，使該故障信號被記憶下來；從第五反及閘U5輸出的高電平信號經過第三反相器U3翻轉成低電平信號，此低電平信號通過第一二極體D1傳到第一反及閘U1的第二輸入端，使第一反及閘U1的輸出一直為高電平，也就使驅動信號無法傳遞到後續的電路，從而封鎖了驅動信號。
本創作提供的一種信號故障檢測電路，高電平生成單元和低電平生成單元根據驅動信號分別生成高電平信號和低電平信號，故障監測記憶單元通過高電平信號和低電平信號監測是否有故障信號，如果產生故障信號則記憶故障信號，並在主控制部分作出回應之前封鎖驅動信號，回應速度快，適用於對回應速度有苛求的場合。
以上所述僅為本創作的較佳實施例而已，並不用以限制本創作，凡在本創作的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本創作的保護範圍之內。
In order to make the technical problems, technical solutions and beneficial effects solved by the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
As shown in FIG. 1, a signal failure detecting circuit includes a pulse transformer T, and further includes a signal processing unit 4 for controlling a driving signal, a high level signal for generating a high level signal according to the driving signal, and a high level according to the fault signal. a high level generating unit 1 for signals, a low level generating unit 2 for generating a low level signal according to a driving signal, and a fault according to a signal output from the high level generating unit 1 and a signal output from the low level generating unit 2 The signal, memory fault signal and control signal processing unit 4 blocks the fault monitoring memory unit 3 of the driving signal, and the signal processing unit 3 is connected to the input terminals of the high level generating unit 1 and the low level generating unit 2, respectively, and the high level generating unit The input end of 1 is also connected to the primary side of the pulse transformer T, and the output ends of the high level generating unit 1 and the low level generating unit 2 are connected to the input end of the fault monitoring memory unit 3, and the output end of the fault monitoring memory unit 3 It is connected to the signal processing unit 2.
The drive signal is transmitted from the primary side of the pulse transformer T to the secondary side and then to the other circuit, and the fault signal is transmitted from the secondary side of the pulse transformer T to the primary side.
The signal processing unit includes a first reverse gate U1, a first diode D1, a first low voltage power supply V1, and a first resistor R1. The first input terminal of the first reverse gate U1 is used for inputting a driving signal, and the first reverse The second input end of the gate U1 is connected to the cathode of the first diode D1, and the cathode of the first diode D1 is connected to the output end of the fault monitoring memory unit 3, and one end of the first resistor R1 and the first diode D1 The anode is connected, and the other end of the first resistor R1 is connected to the first low voltage power source V1.
When the second input terminal of the first reverse gate U1 is at a high level, the driving signal can be transmitted to the subsequent unit through the first reverse gate U1.
The signal fault detecting circuit further includes a push-pull unit 5 for enhancing a driving signal, and the push-pull unit 5 includes a push-pull circuit, a first capacitor C1, a second capacitor C2, a first inverter UD1, a second inverter UD2, and a second resistor R2, one end of the second resistor R2 is connected to the output end of the first anti-gate U1, and the other end of the second resistor R2 is connected to the input end of the first inverter UD1, the output of the first inverter UD1 The terminal is connected to the input end of the second inverter UD2, the output end of the second inverter UD2 is connected to the input end of the push-pull circuit, and the output end of the push-pull circuit is connected to one end of the first capacitor C1, the first capacitor C1 The other end is connected to the primary side of the pulse transformer T, one end of the second capacitor C2 is connected between the second resistor R2 and the first amplifier, and the other end of the second capacitor C2 is connected to the output end of the push-pull circuit. The pull circuit is composed of a second transistor Q2 and a third transistor Q3.
The driving signal is input from the first input end of the first anti-gate, passes through the push-pull circuit, increases the driving capability, and is transmitted to the primary side of the pulse transformer T and the high-level generating unit 1.
The high level generating unit 1 includes a voltage stabilizing tube D2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first transistor Q1, a second low voltage power source V2, and a third capacitor C3, and the voltage regulator tube D2 The anode is connected to the other end of the first capacitor C1, the cathode of the Zener diode D2 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the base of the first transistor Q1, the first transistor Q1 The emitter is connected to the second low voltage power supply V. The collector of the first transistor Q1 is connected to one end of the fifth resistor R5 and the fault monitoring memory unit 3. The other end of the fifth resistor R5 is grounded, and one end of the fourth resistor R4 Connected to the base of the first transistor Q1, the other end of the fourth resistor R4 is connected to the second low voltage power source V2, one end of the third capacitor C3 is connected to the second low voltage power source V2, and the other end of the third capacitor C3 is grounded.
The high level generating unit 1 generates a high level signal: the driving signal is a positive and negative pulse, and the first transistor Q1 is turned on in the first triode through the Zener diode D2 corresponding to the falling edge of each period of the driving signal. The collector of Q1 generates a high level of a narrow width, and the width of this high level can be set by setting relevant parameters of the third resistor R3 and the fourth resistor R4.
The low level generating unit 2 includes a second reverse gate U2, a third reverse gate U3, a fourth capacitor C4, a fifth capacitor C5, a second diode D3, a third diode D4, and a fourth diode. D5, sixth resistor R6, seventh resistor R7, eighth resistor R8, third low voltage power source V3, and fourth low voltage power source V4, the cathode of the second diode D3 is connected to the cathode of the third diode D4, and the second The anodes of the diode D3 and the third diode D4 are respectively connected to one ends of the sixth resistor R6 and the seventh resistor R7, and the other ends of the sixth resistor R6 and the seventh resistor R7 are connected to the third low voltage power source V3, and second The first input end of the gate U2 is connected to one end of the fifth capacitor C5, the other end of the fifth capacitor C5 is connected to the output end of the first anti-gate U1, and the second input end of the second anti-gate U2 is The anode of the diode D4 is connected, the output end of the second reverse gate U2 is connected to the input end of the third reverse gate U3, and the output end of the third reverse gate U3 is connected to the cathode of the fourth diode D5. The anode of the fourth diode D5 is connected to one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to the fourth low voltage power source V4, and one end of the fourth capacitor C4 is The second input end of the second gate C4 is connected to the output end of the third reverse gate U3, wherein the third reverse gate U3 can also be a reverse gate.
The low level generating unit 2 generates a low level signal: at each falling edge of the driving signal, the driving signal passes through the fifth capacitor C5, and according to the principle that the voltage across the capacitor cannot be abrupt, the first in the second reverse gate U2 A low-level pulse is generated at the input end, and a high-level pulse is outputted from the output end of the second anti-gate, and then inverted by the third reverse gate U3 to generate a low-level pulse at the cathode of the fourth diode D5. The low level pulse can be set according to the relevant parameters of the sixth resistor R6, the seventh resistor R7, and the fourth capacitor C4.
The fault monitoring memory unit 3 includes a fourth reverse gate U4, a fifth reverse gate U5, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a fifth diode D6, and a third inverter UD3. The fifth low voltage power supply V5 and the sixth low voltage power supply V6, the first input end of the fourth reverse gate U4 is connected to the collector of the first transistor Q1, and the second input end of the fourth reverse gate U4 is the fourth input The anode of the pole D5 is connected, the output end of the fourth reverse gate U4 is connected to the first input end of the fifth reverse gate U5, and the second input end of the fifth reverse gate U5 is connected to one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the fifth low voltage power source V5, the output end of the fifth counter gate U5 is connected to the anode of the fifth diode D6, and the cathode of the fifth diode D6 and the first transistor Q1 The collector is connected, the output of the fifth reverse gate U5 is also connected to the input end of the third inverter UD3, the output end of the third inverter UD3 is the output end of the fault monitoring memory unit 3, and the tenth resistor R10 One end is connected to the output end of the third inverter UD3, and the other end of the tenth resistor R10 is connected to the sixth low voltage power source V6, one end of the eleventh resistor R11 Connected to the input end of the third inverter UD3, the other end of the eleventh resistor R11 is grounded, wherein the fifth reverse gate U5 can also be a reverse gate.
As shown in FIG. 4, under normal circumstances, the high and low levels generated by the high level generating unit 1 and the low level generating unit 2 are symmetric in timing, but have a certain delay, low level. The signal width is slightly larger than the high level signal, and the low level signal and the high level signal respectively enter the first input end and the second input end of the fourth reverse gate U4. According to the logic relationship, the output of the fourth reverse gate U4 is known. The terminal is always at a high level. When a fault signal occurs, the fault signal is transmitted from the secondary side of the pulse transformer T to the primary side, and the high level generating module 1 is passed, so that a narrow width is generated in one cycle. The high level signal, the output of the fourth reverse gate U4 will output a low level signal, and the low level signal is turned into a high level signal through the fifth reverse gate U5 and passes through the fifth diode. D6 feeds back to the first input end of the fourth reverse gate U4, so that the fault signal is memorized; the high level signal outputted from the fifth reverse gate U5 is inverted to a low level signal by the third inverter U3. The low level signal is transmitted to the second input of the first reverse gate U1 through the first diode D1. At the input end, the output of the first reverse gate U1 is always at a high level, so that the drive signal cannot be transmitted to the subsequent circuit, thereby blocking the drive signal.
A signal fault detecting circuit provided by the present invention, the high level generating unit and the low level generating unit respectively generate a high level signal and a low level signal according to the driving signal, and the fault monitoring memory unit passes the high level signal and the low level signal. Monitor the fault signal. If the fault signal is generated, the fault signal is memorized and the drive signal is blocked before the main control part responds. The response speed is fast and it is suitable for occasions where the response speed is demanding.
The above description is only for the preferred embodiment of the present invention and is not intended to limit the present invention. Any modification, equivalent replacement and improvement made within the spirit and principle of the present creation should be included in the protection of the present creation. Within the scope.
1‧‧‧高電平生成單元
2‧‧‧低電平生成單元
3‧‧‧故障監測記憶單元
4‧‧‧信號處理單元
5‧‧‧推挽單元
C1、C3、C4、C5‧‧‧電容
D1、D3、D4、D5、D6‧‧‧二極體
D2‧‧‧穩壓管
Q1、Q2、Q3‧‧‧三極管
R1、R2、R3、R4、R5、R6、R7、R8、R9、R10、R11‧‧‧電阻
T‧‧‧脈衝變壓器
U1、U2、U3、U4、U5‧‧‧反及閘
UD1、UD2、UD3‧‧‧反相器
V1、V2、V3、V4、V6‧‧‧低壓電源1‧‧‧High level generating unit
2‧‧‧low level generating unit
3‧‧‧Fault monitoring memory unit
4‧‧‧Signal Processing Unit
5‧‧‧Push-pull unit
C1, C3, C4, C5‧‧‧ capacitors
D1, D3, D4, D5, D6‧‧‧ diodes
D2‧‧‧ voltage regulator
Q1, Q2, Q3‧‧‧ triode
R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11‧‧
T‧‧‧pulse transformer
U1, U2, U3, U4, U5‧‧‧ anti-gate
UD1, UD2, UD3‧‧‧ inverter
V1, V2, V3, V4, V6‧‧‧ low voltage power supply
第1圖為本創作提供的一種信號故障檢測電路一實施例的結構示意圖；
第2圖為本創作提供的一種信號故障檢測電路另一實施例的結構示意圖；
第3圖為本創作提供的一種信號故障檢測電路一實施例的電路原理圖；
第4圖為正常情況下驅動信號以及第3圖中第四反及閘的輸入端的高低電平信號時序圖；以及
第5圖為故障信號發生時驅動信號以及第3圖中第四反及閘的輸入端的高低電平信號時序圖。
FIG. 1 is a schematic structural diagram of an embodiment of a signal fault detecting circuit provided by the present invention;
2 is a schematic structural diagram of another embodiment of a signal fault detecting circuit provided by the present invention;
FIG. 3 is a circuit schematic diagram of an embodiment of a signal fault detecting circuit provided by the present invention;
Figure 4 is a timing diagram of the drive signal in the normal case and the high and low level signals at the input of the fourth reverse gate in Fig. 3; and Fig. 5 is the drive signal when the fault signal occurs and the fourth reverse gate in Fig. 3. High and low signal timing diagram for the input.
1‧‧‧高電平生成單元 1‧‧‧High level generating unit
2‧‧‧低電平生成單元 2‧‧‧low level generating unit
3‧‧‧故障監測記憶單元 3‧‧‧Fault monitoring memory unit
4‧‧‧信號處理單元 4‧‧‧Signal Processing Unit
T‧‧‧脈衝變壓器 T‧‧‧pulse transformer
Claims (6)
脈衝變壓器；
用於控制驅動信號的信號處理單元；
用於根據所述驅動信號生成高電平信號以及根據故障信號生成高電平信號的高電平生成單元；
用於根據所述驅動信號生成低電平信號的低電平生成單元；以及
根據所述高電平生成單元輸出的高電平信號和所述低電平生成單元輸出的低電平信號監測所述故障信號、記憶所述故障信號和控制所述信號處理單元封鎖所述驅動信號的故障監測記憶單元，
所述信號處理單元分別與所述高電平生成單元和所述低電平生成單元的輸入端相連，所述高電平生成單元的輸入端還與所述脈衝變壓器的原邊相連，所述高電平生成單元和所述低電平生成單元的輸出端均與所述故障監測記憶單元的輸入端相連，所述故障監測記憶單元的輸出端與所述信號處理單元相連。A signal fault detecting circuit, comprising:
Pulse transformer
a signal processing unit for controlling a drive signal;
a high level generating unit for generating a high level signal according to the driving signal and generating a high level signal according to the fault signal;
a low level generating unit for generating a low level signal according to the driving signal; and monitoring the high level signal according to the high level generating unit and the low level signal output by the low level generating unit Describe a fault signal, memorize the fault signal, and a fault monitoring memory unit that controls the signal processing unit to block the drive signal,
The signal processing unit is respectively connected to the input ends of the high level generating unit and the low level generating unit, and the input end of the high level generating unit is further connected to the primary side of the pulse transformer, The output terminals of the high level generating unit and the low level generating unit are both connected to the input end of the fault monitoring memory unit, and the output end of the fault monitoring memory unit is connected to the signal processing unit.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204766223U CN202372616U (en) | 2011-11-25 | 2011-11-25 | Signal fault detection circuit |
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| Publication Number | Publication Date |
|---|---|
| TWM449341U true TWM449341U (en) | 2013-03-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW101213752U TWM449341U (en) | 2011-11-25 | 2012-07-17 | A fault signal detecting circuit |
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| CN (1) | CN202372616U (en) |
| TW (1) | TWM449341U (en) |
Cited By (1)
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|---|---|---|---|---|
| TWI565221B (en) * | 2014-02-26 | 2017-01-01 | 全漢企業股份有限公司 | Inverting apparatus and photovoltaic power system using the same |
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| CN113782388B (en) * | 2021-01-12 | 2024-03-12 | 青岛鼎信通讯股份有限公司 | Relay switch buffer circuit applied to power industry products |
-
2011
- 2011-11-25 CN CN2011204766223U patent/CN202372616U/en not_active Expired - Lifetime
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2012
- 2012-07-17 TW TW101213752U patent/TWM449341U/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI565221B (en) * | 2014-02-26 | 2017-01-01 | 全漢企業股份有限公司 | Inverting apparatus and photovoltaic power system using the same |
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