『429131 五、新型說明： 【新型所屬之技術領域】 本創作係一種HDMI訊號偵測裝置，尤指一種同時偵 J測CEC接腳與HTPLG接腳或是加入DDC接腳組接腳進 行判斷的HDMI多重訊號偵測裝置。 【先前技術】 HDMI(High Definition Multimedia Interface)是一種全 _數位化影像和聲音傳送介面，HDM丨可使用於機上盒、 DVD播放機、電腦、電視、音響與電視遊樂器，透過一條 HDM丨電纜可以同時傳送無壓縮的音訊與視訊信號，簡化 各視聽設備之間的連接與安裝；標準的HDMI接頭有19 隻接腳，除了傳送資料（Data)與時脈（Clock)的接腳，另外 有3隻接腳可以使兩視聽設備確認其間的hdmi接頭是否 正確連接並可相互傳送溝通訊號，這3隻接腳分別為 • Consumer Electronics Contro 丨接腳（以下簡稱 CEC 接腳） 、H〇t Plug Detect)接腳（以下簡稱HTPLG接腳）與 Display Data Channel接腳組（以下簡稱DDC接腳組）， CEC接腳可傳送工業規格的av Link協定訊號，透過 單—遙控器可操作多台視聽設備，例如一訊號源（s〇urce 端）如DVD播放機、衛星接收機’與電視（Sink端）間能夠 相互的控制，當HDM丨電纜連接DVD播放機與電視時，只 要開啟DVD播放機電源並按下播放鍵後，CEC接腳會傳送 指令至電視’使電視同時開啟電源，當不想觀看DVD影片 3 M429131 時’只要關閉電視電源，r p： P# 宅，原接腳會傳送指令使DVD播放 機關閉電源。 HTPLG接腳用來侦測視聽設備的hdm 接至其他視聽設備，當DVD播㈣“ 運 … 田UVD播放機與電視連接時，電視會 從HTPLG接腳得到+5V的電壓，表示肖dvd播放機有連 接，當DVD播放機關閉電源或者是不播放影片時， HTPLG接腳應不會有+5V的電壓，但許多產品設計 PLG接腳的+5V會永遠存在，此時電視若用HTpLG接 腳判定連接的DVD播放機有傳送訊號，但實際上DVD播 放機是關閉電源或是不傳送訊號的狀態，即會產生錯誤的 判斷》 DDC接腳組包含一 SCL接腳與一 SDA接腳當sda 接腳傳送訊號時，SCL接腳會有一 1〇〇kHz時脈的丨2S訊 唬，使DVD播放機藉由DDC接腳組偵測電視的播放能力 ’送出對應的訊號’例如SD’ HD或Full HD。 如上所述，現有的HDMI裝置皆取其中一接腳做連接 偵測的判定，但是容易產生誤動作’如HTPLG接腳連接 DVD播放機，但並未傳送信號理時電視應不會進行切換動 作；又如DDC接腳組有信號傳送，但該設備不具有CEC 功能，因此CEC功能會判定是屬於無動作的設備而不傳送 訊號；該設備雖具CEC功能，但+5V或HTPLG接腳卻維 持固定電壓’因此單純判斷+5V/HTPLG接腳亦常會有誤動 作發生。 【新型内容】 M429131 如前揭所述，當透過一 HDM丨電纜連接兩視聽設備時 ，單獨偵測一 CEC接腳或一 HTPLG接腳的訊號以判斷是 否有正確連接常會發生錯誤，因此本創作主要目的在提供 一 HDMI多重訊號偵測裝置，同時偵測一個以上hdm丨埠 的CEC .接腳與HTPLG接腳或是加入偵測DDC接腳組， 藉由偵測多重接腳的連接狀態，以判斷兩視聽設備之間是 否正確連接以及正常傳送訊號。『429131 V. New Description: 【New Technology Fields】 This is an HDMI signal detection device, especially one that detects the CEC pin and the HTPLG pin or joins the DDC pin group. HDMI multiple signal detection device. [Prior Art] HDMI (High Definition Multimedia Interface) is a full-digit digital video and audio transmission interface. HDM can be used in set-top boxes, DVD players, computers, TVs, audio and TV games through an HDM. The cable can transmit uncompressed audio and video signals at the same time, simplifying the connection and installation between audio-visual equipment. The standard HDMI connector has 19 pins, except for the data and clock pins. There are 3 pins that enable the two audio-visual devices to confirm that the hdmi connectors are properly connected and can transmit the channel communication numbers to each other. These three pins are respectively • Consumer Electronics Contro pin (hereinafter referred to as CEC pin), H〇t Plug Detect) pin (hereinafter referred to as HTPLG pin) and Display Data Channel pin group (hereinafter referred to as DDC pin group), CEC pin can transmit industrial specification av Link protocol signal, and can operate multiple units through single-remote control Audio-visual equipment, such as a signal source (s〇urce) such as a DVD player, satellite receiver 'and TV (Sink) can control each other, when HDM When the cable is connected to the DVD player and the TV, as long as the DVD player is turned on and the play button is pressed, the CEC pin will send a command to the TV 'to make the TV turn on at the same time. When you don't want to watch the DVD movie 3 M429131, just turn off the TV power. , rp: P# Home, the original pin will send instructions to turn off the DVD player. The HTPLG pin is used to detect the hdm of the audio-visual equipment connected to other audio-visual equipment. When the DVD broadcast (4) "When the field UVD player is connected to the TV, the TV will get a +5V voltage from the HTPLG pin, indicating the Xiao DVD player. There is a connection. When the DVD player is powered off or the movie is not playing, the HTPLG pin should not have a voltage of +5V, but many products design the +5V of the PLG pin forever. At this time, if the TV uses the HTpLG pin. It is determined that the connected DVD player has a transmission signal, but in fact, the DVD player is in a state of turning off the power or not transmitting the signal, that is, an error judgment is generated. The DDC pin group includes an SCL pin and an SDA pin when sda When the pin transmits a signal, the SCL pin will have a 〇〇2S signal of 1 kHz clock, which enables the DVD player to detect the playback capability of the TV by the DDC pin group 'send the corresponding signal' such as SD' HD or Full HD. As mentioned above, the existing HDMI devices take the determination of one of the pins for connection detection, but it is easy to cause a malfunction. For example, if the HTPLG pin is connected to the DVD player, but the signal is not transmitted, the TV should not be performed. Switching action If the DDC pin group has signal transmission, but the device does not have CEC function, the CEC function determines that it is a non-operating device and does not transmit a signal; although the device has CEC function, the +5V or HTPLG pin remains fixed. Voltage 'so it is often judged that the +5V/HTPLG pin often has a malfunction. [New content] M429131 As mentioned before, when connecting two audio-visual equipment through an HDM cable, separately detect a CEC pin or an HTPLG The signal of the pin to determine whether there is a correct connection often causes an error. Therefore, the main purpose of this creation is to provide an HDMI multi-signal detection device and simultaneously detect more than one hdm丨埠 CEC. The pin and the HTPLG pin or join the Detector. The DDC pin group is tested to detect whether the two audio-visual devices are correctly connected and normally transmit signals by detecting the connection state of the multiple pins.
為達成前述目的所採取的主要技術手段係令前述 HDMI多重訊號偵測裝置包括有： 一接腳狀態判斷單元，具有複數接腳，包含有一個以 上的輸入埠與一輸出埠，該輸出' 入埠分設有一 CEC接 腳、一HTPLG接腳與一 DDC接腳組，該DDC接腳組包 3有SCL接腳與一 SDA接腳；且接腳狀態判斷單元内 建一接腳狀態交叉判斷模組； 一個以上的HDMI輸入埠，具有複數接腳，包含一 CEC接腳、一 HTPLG接腳與一 DDc接腳組，該接 腳組亦包含有—SCL接腳與一 SDA接腳，各接腳分別與 接腳狀態判斷單元之輸入埠的對應接腳電連接； 一 HDMI輸出埠，具有複數接腳，包含一 cEc接腳、 HTPLG接腳與一 DDC接腳組，該DDC接腳組包含有 。SCL接腳與—SDA接腳，各接腳分別與接腳狀態判斷 單元之輸出埠的對應接腳電連接； 和用則述元件組成的HDM丨多重訊號偵測裝置，當 DMI輸入蟑接收—外部設備輸入的丨訊號後接腳 狀態判斷單兀的接腳狀態交又判斷模組依照、HDMI輸入埠 M429131 中的CEC接腳與HTPLG接腳的狀態進行判斷或是加入 DDC接腳組之SCL接腳的時脈訊號進行判斷，判斷各接 腳的訊號是標準的HDMI訊號後，表示該HDM丨輸入埠正 確連接，再由HDM丨輸出璋送出對應的控制訊號或是送出 由HDMI輸入埠輸入的訊號； 該接腳狀態交叉判斷模組是當H D ΜI輸出埠與η D ΜI 輸入埠的HTPLG接腳有+5V電壓訊號時’接腳狀態交又 判斷模組會加入CEC接腳的訊號狀態進行判斷，當 HTPLG接腳與CEC接腳同時具有訊號，表示HDM丨輸出 埠與HDMI輸入埠正確連接，可相互傳送訊號，或是進— 步加入DDC接腳組之SCL接腳的時脈（i〇〇kHz)訊號進行 判斷，當SCL的接腳具有時脈，表示HDM丨輸出、入埠正 確連接且有訊號傳送；由於接腳狀態判斷單元是藉由CEc 接腳與HTPLG接腳一併判斷或是加入DDC接腳組訊號進 行判斷，利用多重接腳確認連接狀態，可避免現有單獨偵 測CEC接腳或HTPLG接腳產生誤判連接狀態的問題。 【實施方式】 關於本創作一較佳實施例的電路方塊圖’請參閱圖’ 所示’包含一接腳狀態判斷單元1〇、一 HDMI輸入蟑2〇 與一 HDMI輸出埠30 ’該接腳狀態判斷單元1〇、HDM丨輸 入埠20與HDM丨輸出埠30分別具有複數接腳，其中，接 腳狀態判斷單元1 〇包含有一個以上的輸入埠與一輸出埠 ’各輸出、入埠分設有一 CEC接腳14、11、一 HTPLG 接腳15、12與一DDC接腳組16、13 ;又HDMI輸入埠 M429131 2〇與HDMI輸出埠30則分設有一 CEC接腳21、31、一 HTPLG接腳22、32與一 DDC接腳組23 ' 33，各對應接 腳相互電連接。 § HDMI輸入埠2〇接收一 HDM丨訊號後，由接聊狀態 判斷單疋10内建的一接腳狀態交叉判斷模組依照HDMI 輸入埠20中的CEC接腳21與HTPLG接腳22的狀態進 订判斷或是加入DDC接腳組23的時脈訊號進行判斷，確 δ忍各接腳具有正確的HDM丨訊號後，令HDM丨輸出埠3〇送 出由HDMI輸入埠2〇輸入的影音訊號，或是由HDM丨輸出 埠30送訊號至HDM|輸入埠2〇。 清參閱圖2所示’係前述實施例的延伸設計，其基本 架構與圖1大致相同，仍包括接腳狀態判斷單元1〇、 HDMI輸入埠20與HDMI輸出埠30;不同處在接腳狀態 判斷單元10進一步包括一第二輸入埠，用以連接一第二 HDMI輸入埠40，該第二HDMI輸入埠40包含一 CEC接 腳41、一 HTPLG接腳42與一 DDC接腳組43，而接腳狀 態判斷單元10的第二輸入埠設有對應第二HDMI輸入埠 40的一 CEC接腳11,、一 HTPLG接腳12,與一 DDC接腳 組13’ ’各接腳分別與第二HDMI輸入埠40對應的各接腳 電連接。 請參閱圖3所示，為本實施例之HDMI輸入埠20與 第二HDMI輸入埠40的電路圖，該HDMI輸入埠20的 HTPLG接腳22標示為HTPLUG，又DDC接腳組23包含 一 SCL接腳231與一 SDA接腳232，第二HDMI輸入埠 40的HTPLG接腳42標示為HTPLUG，又DDC接腳組 7 M429131 43包含一 SCL接腳431與一 SDA接腳432。 6月參閱圖4所示，為本實施例之接腳狀態判斷單元1 〇 的電路圖，該接腳狀態判斷單元1〇之輸入埠的HTpLG接 腳12標示為HPLGO,第二輸入埠的HTpLG接腳12，標示 為HPLG1 ;該DDC接腳組13包含一 scl接腳131標示 為DSCLO與一 SDA接腳132標示為DSDAO，又第二輸 入埠的DDC接腳組13,包含一 SCL接腳131，標示為 DSCL1與一 SDA接腳132’標示為DSDA1 ;該接腳狀態判 斷單元10之輸出埠的HTPLG接腳15標示為HPLg，該 DDC接腳組16包含一 SCL接腳161標示為DSCL·與一 SDA接腳162標示為DSDA ;各接腳分別與圖3對應的接 腳電連接；如圖所示’該接腳狀態判斷單元彳〇具有四個 輸入埠’各輸入埠的對應接腳分別為HPLG0〜HPLG3、 DSCL0~ DSCL3與DSDA0~ DSDA3，表示最多可連接四 組H D ΜI輸入埠。 請參閱圖5所示，為本實施例之HDMI輸出埠30的 電路圖，該HDMI輸出埠3〇的HTPLG接腳32標示為The main technical means for achieving the foregoing purpose is that the HDMI multi-signal detecting device comprises: a pin state determining unit having a plurality of pins, comprising more than one input port and an output port, the output being in There is a CEC pin, a HTPLG pin and a DDC pin set. The DDC pin group 3 has an SCL pin and an SDA pin; and the pin state judging unit has a pin state cross determination. Module; more than one HDMI input port, having a plurality of pins, including a CEC pin, an HTPLG pin and a DDc pin set, the pin set also includes an -SCL pin and an SDA pin, each The pins are respectively electrically connected to the corresponding pins of the input port of the pin state judging unit; an HDMI output port has a plurality of pins, including a cEc pin, an HTPLG pin and a DDC pin group, and the DDC pin group Contained. The SCL pin and the -SDA pin are respectively electrically connected to the corresponding pins of the output port of the pin state judging unit; and the HDM/multiple signal detecting device composed of the components described above, when the DMI input is received - The status of the pin after the external device input is judged by the status of the pin and the status of the pin is judged according to the state of the CEC pin and the HTPLG pin in the HDMI input 埠M429131 or the SCL of the DDC pin group. The pin signal of the pin is judged, and it is judged that the signal of each pin is a standard HDMI signal, indicating that the input port of the HDM is correctly connected, and then the output signal is sent by the HDM port, or the input signal is sent by the HDMI input. The signal state cross-judging module is when the HD ΜI output 埠 and the η D ΜI input 埠 HTPLG pin has a +5V voltage signal, and the pin state is judged and the module will join the CEC pin signal state. It is judged that when the HTPLG pin and the CEC pin have a signal at the same time, it indicates that the HDM port is correctly connected to the HDMI input port, and the signals can be transmitted to each other, or the clock of the SCL pin of the DDC pin group is further added ( i 〇〇 kHz) signal to judge, when the SCL pin has a clock, it means that the HDM 丨 output, the input 埠 is correctly connected and there is signal transmission; because the pin status judgment unit is judged by the CEc pin and the HTPLG pin together Or add the DDC pin group signal to judge, use the multi-pin to confirm the connection status, can avoid the problem that the existing separate detection CEC pin or HTPLG pin misidentifies the connection state. [Embodiment] A circuit block diagram of a preferred embodiment of the present invention is shown in the figure of 'refer to the figure' and includes a pin state determination unit 1〇, an HDMI input port 2〇, and an HDMI output port 30'. The state judging unit 1 , the HDM 丨 input 埠 20 and the HDM 丨 output 埠 30 respectively have a plurality of pins, wherein the pin state judging unit 1 〇 includes more than one input 埠 and one output 埠 'each output and input points There are a CEC pin 14, 11 , a HTPLG pin 15, 12 and a DDC pin group 16, 13; and an HDMI input 埠 M429131 2 〇 and HDMI output 埠 30 are assigned a CEC pin 21, 31, a The HTPLG pins 22, 32 and a DDC pin group 23' 33 are electrically connected to each other. § HDMI input 埠2〇 After receiving an HDM signal, the status of the pin status judging module built in the acknowledgment status unit 10 is in accordance with the state of the CEC pin 21 and the HTPLG pin 22 in the HDMI input 埠20. The order judgment signal or the clock signal of the DDC pin group 23 is judged, and after confirming that each pin has the correct HDM signal, the HDM output is sent to the video signal input by the HDMI input 埠2〇. Or send the signal from HDM丨埠30 to HDM| input埠2〇. Referring to FIG. 2, the extension design of the foregoing embodiment is substantially the same as that of FIG. 1, and further includes a pin state determination unit 1 , an HDMI input port 20 and an HDMI output port 30; the difference is in the pin state. The determining unit 10 further includes a second input port for connecting to a second HDMI input port 40. The second HDMI input port 40 includes a CEC pin 41, an HTPLG pin 42 and a DDC pin group 43. The second input port of the pin state determining unit 10 is provided with a CEC pin 11 corresponding to the second HDMI input port 40, an HTPLG pin 12, and a pin of the DDC pin group 13'' respectively and the second pin. The pins corresponding to the HDMI input 埠40 are electrically connected. Please refer to FIG. 3 , which is a circuit diagram of the HDMI input port 20 and the second HDMI input port 40 of the embodiment. The HTPLG pin 22 of the HDMI input port 20 is labeled as HTPLUG, and the DDC pin group 23 includes an SCL connection. The foot 231 and an SDA pin 232, the HTPLG pin 42 of the second HDMI input port 40 is designated as HTPLUG, and the DDC pin group 7 M429131 43 includes an SCL pin 431 and an SDA pin 432. Referring to FIG. 4, a circuit diagram of the pin state determination unit 1A of the present embodiment is shown in FIG. 4. The HTpLG pin 12 of the input port of the pin state determination unit 1 is labeled as HPLGO, and the HTpLG of the second input port is connected. The foot 12 is labeled as HPLG1; the DDC pin group 13 includes a scl pin 131 labeled DSCLO and an SDA pin 132 labeled DSDAO, and a second input port DDC pin group 13 including an SCL pin 131 Marked as DSCL1 and an SDA pin 132' is labeled as DSDA1; the HTPLG pin 15 of the output port of the pin state determining unit 10 is labeled HPLg, and the DDC pin group 16 includes an SCL pin 161 labeled DSCL· And an SDA pin 162 is labeled as DSDA; each pin is electrically connected to the corresponding pin of FIG. 3; as shown in the figure, the pin state determination unit 彳〇 has four inputs 对应 'the corresponding pin of each input 埠HPLG0~HPLG3, DSCL0~DSCL3 and DSDA0~DSDA3 respectively indicate that up to four HD ΜI inputs can be connected. Please refer to FIG. 5, which is a circuit diagram of the HDMI output port 30 of the embodiment. The HTPLG pin 32 of the HDMI output port is labeled as
HTPLUG’ DDC接腳組33包含一 SCL接腳331與一 SDA 接腳332 ;各接腳分別與圖4對應的接腳電連接。 當HDMI輸入埠20或是第二HDMI輸入埠40分別連 接一 HDMI訊號時，接腳狀態判斷單元1〇先偵測htPLG 接腳12或HTPLG接腳12,是否有+5V的電壓以及ceC接 腳11或CEC接腳11’具有訊號，以確認HDM|輸入埠2〇 或是第二HDMI輸入埠4〇具有HDM丨輸入訊號，再進行接 腳狀態的判斷；當HDMI輸入埠20的HTPLG接腳12具 M429131 有+5V的電壓以及CEC接腳同時具有訊號，接腳狀態 交又判斷模組可判斷HDMI輸入埠20具有正確的連接以 及HDMI輸入訊號，亦可再加入DDC接腳組13的訊號進 * 行判斷’當DDC接腳組13的SDA接腳132傳送訊號時 ，SCL接腳131會有一 1〇〇kHz時脈的pS訊號，由上述 的接腳狀態交又判斷模組判斷為正確連接，使接腳狀態= 斷單元1〇可正確選擇具有HDM丨訊號輸入的HDM丨輸^埠 20’再送出對應的訊號至hdmI輸出蟑30。 • 由上述可知，接腳狀態判斷單元1〇藉由偵測hdmi 輸入埠20或是第二HDM丨輸入埠之CEC接腳n、扪，與 HTPLG接腳12、12’或是加入DDC接腳組13、13,時脈狀 態的多重接腳偵測，可避免現有單獨使用CEC接腳11、 ”’或HTPLG接腳12、12，產生錯誤連接狀態的偵測。、 圖式簡單說明】 圖 :係本創作—較佳實施例的電路方塊 HDMI輸入埠）e V個 (二個 圖2 :係本創作一較佳實施例的電路方塊圖 H D ΜI輸入埠）。 圖 圖3:係本創作一較佳實施例之HDM丨輪入埠 的電路 圖4 :係本創作一較佳實 電路圖。 圖 施例之接腳狀態判斷單元的 圖5 :係本創作一較佳實施例之HDMI輸出埠的 9 M429131 【主要元件符號說明】 1 0接腳狀態判斷單元1 1、1 V CEC接腳 12、12' HTPLG 接腳 13、13’ DDC接腳組 131、131’ SCL 接腳 132、132’ SDA 接腳 20 HDMI輸入埠 21 CEC接腳 22 HTPLG 接腳 23 DDC接腳組 231 SCL接腳 232 SDA接腳 30 HDMI輸出埠 31 CEC接腳 32 HTPLG 接腳 33 DDC接腳組 331 SCL接腳 332 SDA接腳 40第二HDMI輸入埠41CEC接腳 42 HTPLG 接腳 43 DDC接腳組 431 SCL接腳 432 SDA接腳 10The HTPLUG' DDC pin set 33 includes an SCL pin 331 and an SDA pin 332; the pins are electrically connected to the pins corresponding to FIG. 4, respectively. When the HDMI input port 20 or the second HDMI input port 40 is respectively connected to an HDMI signal, the pin state determination unit 1 first detects the htPLG pin 12 or the HTPLG pin 12, whether there is a voltage of +5V and a ceC pin. 11 or CEC pin 11' has a signal to confirm that the HDM| input 埠 2 〇 or the second HDMI input 埠 4 〇 has an HDM 丨 input signal, and then judge the pin state; when the HDMI input 埠 20 HTPLG pin The 12 M429131 has a voltage of +5V and the CEC pin has a signal at the same time. The pin status can be judged that the HDMI input 埠20 has the correct connection and the HDMI input signal, and the signal of the DDC pin group 13 can be added. When the DDA pin 13 of the DDC pin group 13 transmits a signal, the SCL pin 131 has a pS signal of 1 kHz clock, and the above-mentioned pin state is judged to be correct. Connect, make the pin status = break the unit 1〇, correctly select the HDM transmission with the HDM signal input and send the corresponding signal to the hdmI output 蟑30. • As can be seen from the above, the pin state determination unit 1 detects the hdmi input 埠 20 or the second HDM 丨 input CEC pin n, 扪, and the HTPLG pin 12, 12 ′ or joins the DDC pin. Group 13, 13 and multi-pin detection in the clock state can avoid the detection of the wrong connection state by using the CEC pin 11, "' or HTPLG pin 12, 12 separately. Figure, simple description] : The present invention - the circuit block HDMI input 较佳) of the preferred embodiment e V (two Figure 2: a circuit block diagram HD ΜI input 一 of a preferred embodiment of the present invention). Figure 3: This book is created FIG. 4 is a circuit diagram of a preferred embodiment of the present invention. FIG. 5 shows a HDMI output of a preferred embodiment of the present invention. 9 M429131 [Description of main component symbols] 1 0 pin status judgment unit 1 1、1 V CEC pin 12, 12' HTPLG pin 13, 13' DDC pin group 131, 131' SCL pin 132, 132' SDA Pin 20 HDMI input 埠 21 CEC pin 22 HTPLG pin 23 DDC pin group 231 SCL pin 232 SDA pin 30 HDMI output 埠 31 CEC pin 32 HTPLG pin 33 DDC pin group 331 SCL pin 332 SDA pin 40 second HDMI input 埠 41CEC pin 42 HTPLG pin 43 DDC pin group 431 SCL pin 432 SDA Foot 10