M428410 五、新型說明： 【新型所屬之技術領域】 本創作是有關一種時脈產生裝置，特別是一種應用於通用串列匯 流排裝置之時脈產生裝置。 【先前技術】M428410 V. New description: [New technical field] This creation relates to a clock generation device, in particular to a clock generation device applied to a universal serial bus arrangement device. [Prior Art]
通用串列匯流排(Universal serial Bus ’ USB)介面已成為電腦週邊設 備廣泛使用的連接介面。依據USB的規範，每一 USB系統主要由三個 π件，亦即USB主機(例如電腦主機）、USB連接介面(Inter_c〇nnecti〇n) 及USB裝置(Device)w冓成。聰裝置之種類包含鍵盤、滑鼠及印表 機等USB功能裝置以及USB集線器(Hub)。 另外USB的規範規定訊號頻率範圍必須為umHz 土 〇.25〇/0,以 使接收端能夠正確齡發送端所傳送的往為了符合聰的規 範，大多制外部且頻率精確的時脈來源，例如石英減器(c神( OscUlatoi·) ’再透過倍賴方絲翻傳送以及触卿_的功能。 如此導致USB㈣ϋ之穌較高，不適合細於聰裝置。而内建於The Universal serial Bus ’ USB interface has become a widely used connectivity interface for computer peripherals. According to the USB specification, each USB system is mainly composed of three π components, that is, a USB host (such as a computer host), a USB connection interface (Inter_c〇nnecti〇n), and a USB device (Device). The types of Cong devices include USB functions such as keyboards, mice, and printers, as well as USB hubs. In addition, the USB specification stipulates that the signal frequency range must be umHz.25〇/0, so that the receiving end can transmit the transmitted source to the correct end. In order to comply with Cong's specifications, most external and frequency-accurate sources of time, such as The quartz reducer (OscUlatoi·) 'transfers through the double-twisted wire transfer and touches the _ function. This leads to the USB (four) ϋ ϋ higher, not suitable for the Cong device.
USB控制器之㈣電路㈣受賴程、溫度、籠等條件的變化而影 響訊號頻率之精確度。 目前=二::調整内部時脈之頻率’使其符合_的規範便是 【新型内容】 本創作提供-種躺於通料龍流職置之時脈產 包含-鎖相迴路，並利用-公因數計算元件所輸出―第,: -第二調整值使輪入至鎖相迴路之參考訊號以及 及 並減少參考訊號之訊號抖動量，進而降低鎖相迴路所輪脈 訊號的訊號·量，叹__之_符合㈣的規範。 含-=生二例通用串，匯流排裝置之時脈產生繼 連接，用以接收時脈訊號以及—USB主機 所產生之週期性訊號，並輪+ _ ^ .元件盥丨觸㈣訊號之計紐。公因數計算 ^ ^ ，物_以及—數值產生騎產生一 數值之-細數，以輸出—第—調整值 用以肢辦接’ 一咚相。。尚貝訊旎以輸出—第一輸出時脈訊號。第 了頻L目迴路以及公隨計算元 ， 一The (4) circuit of the USB controller (4) affects the accuracy of the signal frequency due to changes in conditions such as temperature, temperature, and cage. At present = two:: adjust the frequency of the internal clock 'to make it conform to the _ specification is [new content] This creation provides - a kind of timeline lying in the material flow Longliu position contains - phase-locked loop, and use - The common factor calculation component outputs "first," - the second adjustment value causes the reference signal of the wheel to the phase-locked loop and reduces the amount of signal jitter of the reference signal, thereby reducing the signal amount of the pulse signal of the phase-locked loop, Sigh __ _ meets the specifications of (4). There are two general-purpose strings including -=, and the clock of the busbar device is connected to receive the clock signal and the periodic signal generated by the USB host, and the round + _ ^ component touch (four) signal New Zealand. The common factor calculation ^ ^ , the object _ and - the value of the ride produces a numerical value - to the output - the first - adjustment value is used to connect the body to a phase. . Shangbei News to output - the first output clock signal. The first frequency L-loop and the public computing unit, one
時脈訊號_第二碰值，崎_軌舰輸人鎖H 以下藉由具體實施例配合___加，當更容易瞭解本 創作之目的'技術内容、特點及其所達成之功效。 【實施方式】 本創作所提供之時脈產生裝置主要是應用於通用串列匯流排 ΓΓ:，1 Bus，咖)系統中之USB裝置，以使usb裝置與聰 =之間透過腦介面進行資料傳輸時，彼此的頻率能夠同步，進而 =所傳輸的資料得以同步而不致產生錯誤。進行通用串列匯流排傳輸 ―’ SB裝置可從傳輸的資料中可得到時間週期的資訊，例如資料封 =-開始的同步訊號(SYNC)或是訊框起始訊號(Start〇fFrame，s〇F)。 舉例而言，在USB賴範中，訊框起始職黯為每丨⑽產生一次。 ^作之日樣產生裝置即是彻USB主朗傳送之週雛訊號來鎖定 USB裝置之内部時脈之頻率。 以下以訊框起始訊號S0F為例，說明本創作之時脈產生裝置之架 構。請參照圖1，本創作之一實施例之時脈產生裝置包含一時脈產生單 元1卜一計數器12' —公因數計算元件13、一第一除頻器(divider)15、 —鎖相迴路(Phase-Locked Loop，PLL)16以及一第二除頻器17。時脈 產生單元11用以產生一時脈訊號CLK。於一實施例中，時脈產生單元 11可包含一時脈產生器111以及一倍頻器U2。時脈產生器hi用以產 生一初始時脈訊號CLKini。倍頻器112則與時脈產生器in電性連接， 用以將初始時脈訊號CLKini倍頻至頻率較高之時脈訊號CLK。舉例而 言，時脈產生器可為一環形振盪器(RC oscillator)，其可持續產生一串 穩疋之振盈訊號，且製作成本低廉，設計簡單，適合作為USB裝置之 内建時脈產生器使用。其它各種類型之習知時脈產生器均可適用於本 創作。 计數器12與時脈產生單元11電性連接，用以接收時脈產生單元 11所產生之時脈訊號CLK。計數器12並接收USB主機所產生之訊框 起始號SOF。以兩個訊框起始訊號s〇F之上升緣或下降緣作為一單 位時間’計數器I2可計數出時脈訊號CLK之脈波的對應計數值R。於 -實施例巾，計触RS-整數。料意者，義碱CLK之頻率可 大於週期性訊號之頻率，以利辨識週期性訊號。 公因數計算元件u與計數ϋ u電性連接，以取得計絲12所輸 出之計數值R。此外，公因數計算元件13亦與一數值產生器Μ電性連 接’以接收數值產生器14所產生一數值仏於一實施例中，數值_ -整數。公因數計算元件13即計算計數值R以及數值Ν之公因數 a)(C〇mm〇nf_r) ’並輸出一第一調整值以及一第二調整值，其中，第 -調整值為計數值R與公隨ω之比值；第二調整值為數值N盘公因 ί 比值。於一實施例中’公因數⑴為計數值R以及數值Ν之最大 第一除頻器15與時脈產生單元η以及公因數計算元件13電性連 接。第-除頻器15將時_生單幻i產生之雜訊號clk除以公因 數計异兀件I3所輸出之第一調整值(Κ7ω)，以輸出一參考訊號咖小 鎖i目迴路16與第—除觀15電性連接，以接收第-除頻ϋ 15所徐出 ，參考讀CLKref。触娜16另触—回細紙Kfb，以 第-輸出時脈訊號CLKouU。第二除頻器17與鎖相迴路丨】 數計算締丨3躲連接。第二除· 17將鎖相迴路16所輪= 輸出時脈訊號CLKouU除以公因數計算元件13所產生之第 = (Ν/ω)，赠到回饋訊號CLKfb ,並輸入至鎖相迴路16。 正值 於-實施例中，本創作之時脈產生裝置更包含—第三除綱Μ 其與鎖相舰丨6電性連接。第三除· 18可闕相迴路16所_ 第-輸出時脈訊號CLKmitl除以—常數因子，以輸出-第二輪出 訊號CLKout2 ’其作為傳輸資料時之操作時脈。 依據上述雜，喊m m所赶之初始報峨c 解範圍仙應± 5%内，皆可藉由本創作之架構使輪 = 之頻率符合腦的規範，亦即在12MKz ± 025%的範圍内。訊號 舉例而言’時脈產生器m所產生之初始時脈訊號江咖 為12 MHz + 5%，亦即12·6 MHZ。初始時脈訊號江臟經 四倍頻處理後輸出時脈訊號CLK，其頻率為48赃+ 5%，_ % 4 廳。而兩個訊框起始訊號S0F間之單位時間為（咖。因此 · 計數器12可計數到時脈訊號CLK之脈波數為5〇4〇〇個，亦 ms 為5_〇。數值產生器14輸出之數值N為侧〇。公因數計算3 依據計數值R以及數值料制最大公_為綱。因此，第 值_)即為21(50400/2400);第二調整值即為2〇(侧〇/2_: 依據上述資料，第-除頻器15所輸出之參考訊號CLKref :楊卿剔删丨）。由於設定翻迴路16職出之第_輸脈 訊號CLK〇Utl之頻率為48臟，因此第二除頻器17所輸出之 號CLKfb之頻率亦為2400KHZ(48_2〇)。鎖相迴路16所輸出之第 -輸出時脈《 CLKoutl經第三除_ 18除親理後即 USB的頻率規範之時脈訊號。 Τ σ 由上述可知，公因數計算元件13 所輸出之第一調整值(R/ω)以及第 二調整值(Ν/ω)使第一除頻器15以及第二除頻器17所輪出之參考訊號 CLKref以及回饋訊號CLKfb相近。此外，本創作之架構亦可減少參考 訊號CLKref之訊號抖動量，進而降低鎖相迴路16所輸出之輸出時脈 訊號的訊號抖動量。因此，使用内建之時脈產生器111所產生之初始時 脈訊號CLKini亦能夠產生符合USB的頻率規範之時脈訊號。 綜合上述，本創作之應用於通用串列匯流排裝置之時脈產生裝置 利用公因數計算元件所輸出的第一調整值以及第二調整值，使輸入至 鎖相迴路之參考訊號以及回饋訊號差距較小，且能夠減少參考訊號之 訊號抖動量，進而降低鎖相迴路所輸出之輸出時脈訊號的訊號抖°動 量。因此，本辦之時脈產生裝置個辭誤差較大之時脈訊^亦能 夠經由_祕纽符合USB峨範之時脈訊號，崎低制外部日士 脈之成本。 ^ 以上所述之實施例僅是為說明本創作之技術思想及特點，其 在使熟習此項技藝之人士能夠轉本創作之内容並據以實施，处 以之限料解之專概@，即纽依梢作示之精神所;之= 等變化或修飾，仍應涵蓋在本創作之專利範圍内。 句 M428410 【圖式簡單說明】 圖1為一方塊圖，顯示本創作一實施例之應用於通用串列匯流排 裝置之時脈產生裝置。 【主要元件符號說明】Clock signal _ second touch value, saki _ rail ship input lock H The following example with ___ plus, when it is easier to understand the purpose of this creation 'technical content, characteristics and the effect achieved. [Embodiment] The clock generating device provided by the present invention is mainly applied to a USB device in a universal serial bus bar: a bus system, so that data between the usb device and the smart device is transmitted through the brain interface. When transmitting, the frequencies of each other can be synchronized, and then the transmitted data can be synchronized without causing errors. Perform general-purpose serial bus transmission-' SB device can obtain time period information from the transmitted data, such as data seal = start sync signal (SYNC) or frame start signal (Start〇fFrame, s〇 F). For example, in USB Lai Fan, the frame start job is generated once per 丨 (10). ^ The daily generation device is the frequency of the internal clock of the USB device. The frame start signal S0F is taken as an example to illustrate the architecture of the clock generating device of the present invention. Referring to FIG. 1, a clock generation apparatus according to an embodiment of the present invention includes a clock generation unit 1 and a counter 12' - a common factor calculation component 13, a first divider, and a phase-locked loop ( Phase-Locked Loop (PLL) 16 and a second frequency divider 17. The clock generating unit 11 is configured to generate a clock signal CLK. In an embodiment, the clock generation unit 11 can include a clock generator 111 and a frequency multiplier U2. The clock generator hi is used to generate an initial clock signal CLKini. The frequency multiplier 112 is electrically connected to the clock generator in, for multiplying the initial clock signal CLKini to the clock signal CLK with a higher frequency. For example, the clock generator can be a ring oscillator (RC oscillator), which can continuously generate a series of stable vibration signals, and has low production cost and simple design, and is suitable as a built-in clock of the USB device. Used by the device. Various other types of conventional clock generators are available for this creation. The counter 12 is electrically connected to the clock generating unit 11 for receiving the clock signal CLK generated by the clock generating unit 11. The counter 12 receives the frame start number SOF generated by the USB host. The corresponding count value R of the pulse wave of the clock signal CLK can be counted by the rising edge or the falling edge of the two frame start signals s〇F as a unit time counter. In the embodiment, the RS-integer is measured. It is expected that the frequency of the base CLK can be greater than the frequency of the periodic signal to facilitate identification of the periodic signal. The common factor calculation element u is electrically connected to the count ϋ u to obtain the count value R output by the count wire 12. In addition, the common factor calculation component 13 is also electrically coupled to a value generator to receive a value generated by the value generator 14 in an embodiment, the value _ - an integer. The common factor calculation component 13 calculates the count value R and the common factor a) of the value a (C〇mm〇nf_r) ' and outputs a first adjustment value and a second adjustment value, wherein the first adjustment value is the count value R The ratio with the public ω; the second adjustment value is the value of the N disk common factor ί ratio. In one embodiment, the common factor (1) is the count value R and the maximum value of the value Ν. The first frequency divider 15 is electrically connected to the clock generating unit η and the common factor calculating element 13. The first-divider 15 divides the noise signal clk generated by the time-single-single i by the common adjustment factor (Κ7ω) output by the common factor I3 to output a reference signal coffee lock i-circuit 16 The electrical connection with the first-discrete view 15 is performed to receive the first-division frequency ϋ15, and the reference CLKref is read. Touch the other 16 touch - back to the fine paper Kfb, to the first output pulse signal CLKouU. The second frequency divider 17 is connected to the phase-locked loop. The second division 17 converts the output phase pulse signal CLKouU by the = (Ν/ω) generated by the common factor calculation element 13 to the feedback signal CLKfb and inputs it to the phase locked loop 16. In the embodiment, the clock generating device of the present invention further includes a third dividing unit, which is electrically connected to the phase locked ship 6. The third divide/18 phase loop circuit 16 _ the first output clock signal CLKmitl is divided by a constant factor to output the second round signal CLKout2 ' as the operating clock when transmitting data. According to the above-mentioned miscellaneous, the initial report 喊m 所 解 解 解 ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± ± , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , For example, the initial clock signal generated by the clock generator m is 12 MHz + 5%, which is 12·6 MHZ. The initial clock signal is processed by the quadruple frequency and outputs the clock signal CLK with a frequency of 48赃+ 5%, _% 4 hall. The unit time between the two frame start signals S0F is (coffee. Therefore, the counter 12 can count the pulse wave number of the clock signal CLK as 5〇4〇〇, and ms is 5_〇. The value generator 14 The value of the output N is the side 〇. The common factor calculation 3 is based on the count value R and the maximum value of the numerical system. Therefore, the value _) is 21 (50400/2400); the second adjustment value is 2〇 (Side 〇/2_: According to the above information, the reference signal CLKref output by the first-divider 15 is: Yang Qing 丨 丨). Since the frequency of the first _ pulse signal CLK 〇 Utl set by the flip circuit 16 is 48 dirty, the frequency of the CLKfb output by the second frequency divider 17 is also 2400 kHz (48_2 〇). The first-output clock output by the phase-locked loop 16 "CLKoutl is divided by the third division _ 18, which is the clock signal of the USB frequency specification. Τ σ As described above, the first adjustment value (R/ω) and the second adjustment value (Ν/ω) output by the common factor calculation element 13 cause the first frequency divider 15 and the second frequency divider 17 to rotate. The reference signal CLKref and the feedback signal CLKfb are similar. In addition, the architecture of the present invention can also reduce the amount of signal jitter of the reference signal CLKref, thereby reducing the amount of signal jitter of the output clock signal output by the phase-locked loop 16. Therefore, the initial clock signal CLKini generated by the built-in clock generator 111 can also generate a clock signal conforming to the USB frequency specification. In summary, the clock generation device applied to the universal serial bus device of the present invention utilizes the first adjustment value and the second adjustment value output by the common factor calculation component to make the reference signal and the feedback signal gap input to the phase locked loop It is smaller and can reduce the amount of signal jitter of the reference signal, thereby reducing the signal jitter of the output clock signal output by the phase-locked loop. Therefore, the time pulse of the clock generation device of this office can also be used to meet the cost of the external Japanese medical system through the clock signal of USB. The embodiments described above are only for the purpose of illustrating the technical idea and characteristics of the present invention, which enable those who are familiar with the art to transfer the content of the creation and implement it according to the content, The spirit of New Zealand's tip; the change or modification of the = is still covered by the scope of this creation. Sentence M428410 [Simple Description of the Drawings] Fig. 1 is a block diagram showing a clock generating apparatus applied to a universal serial busbar device according to an embodiment of the present invention. [Main component symbol description]
11 時脈產生單元 111 時脈產生器 112 倍頻器 12 計數器 13 公因數計算元件 14 數值產生器 15 第一除頻器 16 鎖相迴路 17 第二除頻器 18 第三除頻器 CLK 時脈訊號 CLKfb 回饋訊號 CLKini 初始時脈訊號 CLKoutl 第一輸出時脈訊號 CLKout2 第二輸出時脈訊號 CLKref 參考訊號 R 計數值 N 數值 SOF 訊框起始訊號 ω 公因數11 clock generation unit 111 clock generator 112 frequency multiplier 12 counter 13 common factor calculation element 14 value generator 15 first frequency divider 16 phase locked loop 17 second frequency divider 18 third frequency divider CLK clock Signal CLKfb feedback signal CLKini initial clock signal CLKoutl first output clock signal CLKout2 second output clock signal CLKref reference signal R count value N value SOF frame start signal ω common factor