M428406 五、新型說明： 【新型所屬之技術領域】 本新型係有關一種電源管理電路，特別是指一種在供電給 負載電路時又能對電池充電的電源管理電路。 【先前技術】 第1圖顯示先前技術電源管理電路之示意圖。請參閱第1 圖，攜帶式電子裝置中通常需要自外部對電池14充電，電力 可透過電源轉接器或USB端子（外部電力輸入節點）來接收， 故此形成一輸入電壓Vin。在某些應用場合，在電池無電或無 電池的情況下，需要電力供應的系統係直接使用外部電力來 操作。因此電路結構乃設計成如圖所示，系統端可自電源轉 接器或USB端子接受輸入電壓Vin或自電池Η接受電力。外 部電力的供應路徑受功率電晶體Q1控制，該功率電晶體可受 控於控制電路10以產生系統電壓Vsys。控制電路1〇會摘測 輸入電壓Vin、系統電壓Vsys及電池電壓vbat，以產生控制 功率電晶體Q1及Q2之訊號’從而維持適當之系統電壓vSyS 及電池電壓Vbat。外部電力可同時供應給系統及電池14，意 即於電池14電力不足時對其一併充電。 上述控制電路10會根據電池14之充電狀態，選擇定電流 (Constant Current; CC)或定電壓(Constant Voltage ; CV)模式對 電池14充電。當系統之負載過重，則外部電力無法提供足夠 之電流給系統及電池14之充電，則控制電路會切換至自動 電力路控管理(Auto Power Path Manager ; APPM)模式，並將 系統電壓Vsys由4.4伏特降至及固定於電壓胃!)]^ (一般將 VAPPM設為4.2伏特以上’.大於或等於電池飽和電壓又當 3 M428406 輸入電壓Vin低於VAPPM，則電池14之充電電流將減至〇A。 另外，當電池14之充電電流設定值高於輸入端之電流上限， 則控制電路10亦會切換至上述自動電力路徑管理模式。 當VAPPM設為4.2伏特時’又輸入電壓Vin因線損而降 至4.3伏特’則經過功率電晶體Q1(假設其導通電阻為〇 3 〇mh) 之電流則為333mA。若系統之負載過重或希望對電池14以較 高電流設定值來充電，則333mA之電流顯然無法滿足前述需 要。 有鑑於以上缺點，因此有必要提出一種電源管理電路，可 以避免上述問題。 【新型内容】 本創作提供了一種電源管理控制電路，用以控制一第一功 率電晶體以接收一輸入電壓並產生一輸出電壓，以及控制一 第一功率電晶體以自該輸出電壓對一電池充電，其中該第一功 率電晶體耦接於該輸入電壓與該輸出電壓之間，且該第二功 率電晶體耦接於該輸出電壓與該電池之間，該電源管理控制 電路包含：一偵測電晶體，偵測通過該第二功率電晶體之電鲁 流並產生一充電代表電壓；一放大器，比較該輸出電壓與該 電池之電壓，以產生一放大訊號，用以控制該充電代表電壓； 一比較器，比較一參考電壓及該充電代表電壓，以產生一充 電截止訊號，用以決定是否停止充電；及一偏移電壓補償元 件，補償該放大器之輸入偏移電壓。 在其中一種實施型態中，該偏移電壓補償元件係一電 阻’又該電阻耦接於該放大器之正輸入端。 在其中一種實施型態中，該偏移電壓補償元件包括偏移 4 電壓偵測電路和與偏移電壓個電路祕的補償電壓產生電 路，以自動偵測輸入偏移電壓而產生對應的補償電壓。 在其中—種實施型態中，該偏移電壓補償元件使得該放 大器之等效負輸入偏移電壓為零或小於零。 在其中一種實施型態中，該電源管理控制電路另包含一 CC/CV/APPM(定電流/定電壓/自動電力路徑管理)迴路控制電 路，以選擇控制該第二功率電晶體之模式。 在上一種實施型態中，在該APPM (自動電力路徑管理) 模式，該輸出電壓之設定值係低於該電池之飽和電壓。 底下藉由具體實施例詳加說明，當更容易瞭解本創作之 目的、技術内容、特點及其所達成之功效。 【實施方式】 如刖所述，當VAPPM設為4.2伏特時，又輸入電壓vin 因線損而鞋4.3伏特’職過功率電晶體φ(假設其導通電 阻為0.3 Omh)之電流則為333mA。若系統之負載過重或希望 對電池14以較高電流設定值來充電，則333mA之電流顯然無 法滿足别述需要。因此，本新型創作人認為，可將VAppM之 设定值(偵測點)降為3.95伏特，如此經過功率電晶體Q1之電 流就會增加。然而，當此VAPPM之設定值降為‘3 95伏特時， 有時會因控制電路ig内m有之輸人偏移*壓㈣ut offset voltage)，從而造成電池電壓Vbat達到3 95伏特就停住而 無法再繼續上升至規定之上限4 2伏特，故使得電池14之蓄 電量無法充分_。兹以下圖轉輸人偏移電壓造成電池14 之畜電量未達飽和就己停止充電。 第2圖顯不電源管理電路之示意圖。第3圖係第2圖中各 電壓及電流之波形圖。如圖所示，電晶體Q3為感測電晶體， 债測通過功率電晶體Q2的電流(約等於充電電流Ibat)而產生 電流Iseta。放大器24包括電晶體Q4及Q5。因製程造成Q4 及Q5的匹配不精準.，可能在放大器24的兩輸入端之間產生 輸入偏移電壓’一般約為±40mV，此輸入偏移電壓v〇s若位於 負輸入端且大於0伏特就將造成上述電池未達飽和就已停止 充電的問題。假設放大器24負輸入端之輸入偏移電壓v〇s大 於.0伏特(圖中為顯示此輸入偏移電壓，以連接於放大器24負 輸入端之電壓源元件Vos來表示’事實上此輸入偏移電壓不必 須為一個實體的元件），當電池電壓Vbat相當接近3.95伏特 時，因系統電壓Vsys鎖定在VAPPM之設定值(3.95伏特）， 故會造成通過之電晶體Q6之電流Iseta變得很小，亦即電池充 電電流Ibat被誤認已趨近於0(舉例而言，正常狀態下，Ibat/Iseta 約為1/300，但此誤認情形下，ibat/Iseta約為1/3000，造成被 誤認已趨近於0)。磁滯比較器23比較電壓Vseta及一參考電 壓Vref ’例如66mV後，若電壓Vseta小於參考電壓，則停止 充電訊號(End of Charge; EOC)由低位準改為高位準。邏輯控制 電路22接受該改變之停止充電訊號後，會控制 CC/CV/APPM(定電流/定電壓/自動電力路經管理)迴路日控&電 路Μ以關閉功率電晶體Q2，故電池Μ之電壓未達飽和電壓 4.2伏特就已停止充電。其中，cc/cv/AppM迴路控制電路 的作用是選擇控制功率電晶體Q2之模式(可為定電流、定電 壓或自動電力路徑管理模式）。 為解決電池電壓被誤認已達飽和電壓之問題，第4圖顯示 本創作電源管理電路之健實施例示意圖。外部電力的供應路 徑受功率電晶體Q1控制，該功率電晶體可受控於第—驅動電 路45以產生系統電壓Vsys。第一驅動電路45會偵測輸入電 壓Vin及系統電壓Vsys’以產生控制功率電晶體qi之訊號， 從而維持適當之系統電壓Vsys。又第二驅動電路46控制功率 電晶體Q2，並偵測充電.電流Ibat及電池電壓Vbat，以產生控 制功率電晶體Q2之訊號，從而維持適當之電池電壓Vbat。外 部電力可同時供應給系統電壓Vsys及電池電壓Vbat，意即於 電池電力不足時對其一併充電。 如前所述，當放大器24的負輸入端具有大於〇伏特的正 輸入偏移電壓Vos時(以連接於放大器24負輸入端的電壓源元 件Vos表示，但不必須為實體元件），會造成電池過早停止充 電的問題。但在本實施例中’如圖所示，因放大器24之正輸 入端設置有偏移電壓補償元件V〇sl，以補償前述輸入偏移電 壓Vos ’故不會造成通過電晶體Q6之電流iseta變得很小。磁 滯比較器23比較電壓Vseta及一參考電壓Vref，例如66mV 後，此電壓Vseta仍大於參考電壓，則停止充電訊號(E〇c)仍 維持低*位準，因此充電電流仍持續對電池14充電/當電池電 壓Vbat達到3.95伏特後，電源管理電路4〇會改為定電壓(cv) 模式，而電池電壓Vbat會繼續升高至42伏特。當邏輯控制 電路22接受停止充電訊號後’會控制^/^/^^从迴路控制 電路21以關閉功率電晶體Q2，故電池14之電壓達飽和電壓 4.2伏特才會停止充電。 本實施例中將偏移電壓補償元件Vosl繪示為放大器24 的内部疋件’但事實上此偏移電壓補償元件VqsI不必須設置 在放大器24的内部；而且’偏移電壓補償元件Vosl可以為 實體的元贱不為實制元件。#偏移電壓補償元件Vosl為 實體的元件時，如第5賊示，偏移電麵償元件Vgs1例如 為放大器2Λϋ24的外部或内部電阻Ri (電阻ri可視 不為實體的-杜吐部或外部元件）。當偏移電壓補償元件v〇si 輸1端之例如可以在製程上刻意控制放大器24兩 J S電壓差，例如但不限於可以刻意控制電晶體Q5 =寸及/或其與電壓點編之間㈣線阻值 位於負輪人端之正輸人偏移電壓僅為例示，輸入偏移^ Ϊ1ΙΪΓ生於正輸入端，但可等效視為發生於負輸入端（正 負值相反），因此偏移電壓補償元件vqs1 _ 輸入端，故實施例所純不應關本創作之申請專利^圍。、總 之’本創作係藉由提供實體或非實_偏移電壓補償元^M428406 V. New Description: [New Technology Field] This new type relates to a power management circuit, in particular to a power management circuit that can charge a battery when it is supplied to a load circuit. [Prior Art] Fig. 1 shows a schematic diagram of a prior art power management circuit. Referring to FIG. 1 , in a portable electronic device, the battery 14 is usually externally charged, and the power can be received through a power adapter or a USB terminal (an external power input node), thereby forming an input voltage Vin. In some applications, systems that require power supply operate directly from external power when the battery is dead or battery-free. Therefore, the circuit structure is designed as shown in the figure, and the system terminal can receive the input voltage Vin from the power adapter or the USB terminal or receive power from the battery pack. The supply path for external power is controlled by power transistor Q1, which can be controlled by control circuit 10 to generate system voltage Vsys. The control circuit 1 will measure the input voltage Vin, the system voltage Vsys, and the battery voltage vbat to generate a signal to control the power transistors Q1 and Q2 to maintain the appropriate system voltage vSyS and the battery voltage Vbat. External power can be supplied to both the system and the battery 14, i.e., when the battery 14 is low in power. The control circuit 10 selects a constant current (CC) or a constant voltage (CV) mode to charge the battery 14 according to the state of charge of the battery 14. When the load on the system is too heavy, the external power cannot supply enough current to charge the system and the battery 14. The control circuit will switch to the Auto Power Path Manager (APPM) mode and the system voltage Vsys will be 4.4. Volt is reduced and fixed to the voltage stomach!)]^ (Generally VAPPM is set to 4.2 volts or more.) Greater than or equal to the battery saturation voltage. When the 3 M428406 input voltage Vin is lower than VAPPM, the charging current of the battery 14 will be reduced to 〇 In addition, when the charging current setting value of the battery 14 is higher than the current upper limit of the input terminal, the control circuit 10 also switches to the above automatic power path management mode. When the VAPPM is set to 4.2 volts, the input voltage Vin is caused by the line loss. At 4.3 volts, the current through the power transistor Q1 (assuming its on-resistance is 〇3 〇mh) is 333 mA. If the system is overloaded or if it is desired to charge the battery 14 at a higher current setting, then 333 mA The current obviously cannot meet the aforementioned needs. In view of the above shortcomings, it is necessary to propose a power management circuit to avoid the above problems. [New content] A power management control circuit is provided for controlling a first power transistor to receive an input voltage and generating an output voltage, and controlling a first power transistor to charge a battery from the output voltage, wherein the first The power transistor is coupled between the input voltage and the output voltage, and the second power transistor is coupled between the output voltage and the battery, the power management control circuit includes: a detecting transistor, detecting Passing the electric current of the second power transistor and generating a charging representative voltage; an amplifier comparing the output voltage with the voltage of the battery to generate an amplifying signal for controlling the charging representative voltage; a comparator, comparing a reference voltage and the charge representative voltage to generate a charge cutoff signal for determining whether to stop charging; and an offset voltage compensating component to compensate an input offset voltage of the amplifier. In one embodiment, the bias The shifting voltage compensating component is a resistor and the resistor is coupled to the positive input of the amplifier. In one embodiment, The offset voltage compensating component comprises an offset 4 voltage detecting circuit and a compensation voltage generating circuit with an offset voltage circuit to automatically detect the input offset voltage to generate a corresponding compensation voltage. The offset voltage compensating element causes the equivalent negative input offset voltage of the amplifier to be zero or less than zero. In one embodiment, the power management control circuit further includes a CC/CV/APPM (constant current/fixed current) a voltage/automatic power path management circuit control circuit for selectively controlling a mode of the second power transistor. In the last embodiment, the output voltage is set low in the APPM (Automatic Power Path Management) mode. The saturation voltage of the battery. The details of the creation, the technical content, the features and the effects achieved by the present invention are more easily explained by the detailed description of the specific embodiments. [Embodiment] As described in the figure, when VAPPM is set to 4.2 volts, the input voltage vin is 333 mA due to line loss and the 4.3 volts of the shoe's power transistor φ (assuming its conduction resistance is 0.3 Omh). If the system is overloaded or if it is desired to charge the battery 14 at a higher current setting, then the 333 mA current clearly does not meet the need. Therefore, the creator of the present invention believes that the set value (detection point) of the VAppM can be reduced to 3.95 volts, so that the current through the power transistor Q1 increases. However, when the set value of this VAPPM is reduced to '3 95 volts, sometimes the input voltage of the control circuit ig is offset by 4 ut offset voltage, causing the battery voltage Vbat to reach 3 95 volts to stop. However, it is no longer possible to continue to rise to the upper limit of 4 2 volts, so that the battery 14 is not fully charged. The following figure shows that the human offset voltage caused the battery 14 to be charged less than saturation. Figure 2 shows a schematic diagram of the power management circuit. Figure 3 is a waveform diagram of each voltage and current in Figure 2. As shown, the transistor Q3 is a sensing transistor, and the current measured by the power transistor Q2 (approximately equal to the charging current Ibat) produces a current Iseta. Amplifier 24 includes transistors Q4 and Q5. Due to the inaccurate matching of Q4 and Q5 due to the process, an input offset voltage 'generally about ±40mV may be generated between the two inputs of the amplifier 24, and the input offset voltage v〇s is located at the negative input terminal and greater than 0. Volt will cause the above battery to stop charging when it is not saturated. Assume that the input offset voltage v s s of the negative input of the amplifier 24 is greater than .0 volt (the input offset voltage is shown in the figure to be connected to the voltage source component Vos of the negative input of the amplifier 24 to indicate 'the fact that the input is biased The shift voltage does not have to be a physical component. When the battery voltage Vbat is quite close to 3.95 volts, the system voltage Vsys is locked at the set value of VAPPM (3.95 volts), which causes the current through the transistor Q6 to become very high. Small, that is, the battery charging current Ibat is misidentified to have approached 0 (for example, under normal conditions, Ibat/Iseta is about 1/300, but in this case of misidentification, ibat/Iseta is about 1/3000, causing Misunderstanding has approached 0). After the hysteresis comparator 23 compares the voltage Vseta and a reference voltage Vref', for example, 66 mV, if the voltage Vseta is less than the reference voltage, the end of charge (EOC) is changed from the low level to the high level. After receiving the changed stop charging signal, the logic control circuit 22 controls the CC/CV/APPM (constant current/constant voltage/automatic power path management) loop day control & circuit to turn off the power transistor Q2, so the battery Μ The voltage has stopped charging at a voltage of 4.2 volts. Among them, the function of the cc/cv/AppM loop control circuit is to select the mode of controlling the power transistor Q2 (which can be constant current, constant voltage or automatic power path management mode). In order to solve the problem that the battery voltage has been mistakenly recognized to have reached the saturation voltage, FIG. 4 shows a schematic diagram of a robust embodiment of the present power management circuit. The supply path of the external power is controlled by the power transistor Q1, which can be controlled by the first drive circuit 45 to generate the system voltage Vsys. The first driving circuit 45 detects the input voltage Vin and the system voltage Vsys' to generate a signal for controlling the power transistor qi, thereby maintaining an appropriate system voltage Vsys. Further, the second driving circuit 46 controls the power transistor Q2 and detects the charging current Ibat and the battery voltage Vbat to generate a signal for controlling the power transistor Q2 to maintain an appropriate battery voltage Vbat. The external power can be supplied to the system voltage Vsys and the battery voltage Vbat at the same time, which means that the battery is charged when the battery power is insufficient. As previously mentioned, when the negative input of the amplifier 24 has a positive input offset voltage Vos greater than 〇 volts (represented by the voltage source element Vos connected to the negative input of the amplifier 24, but not necessarily a physical component), the battery is caused Stop charging too early. However, in the present embodiment, as shown in the figure, since the positive input terminal of the amplifier 24 is provided with the offset voltage compensating element V〇sl to compensate the aforementioned input offset voltage Vos', the current through the transistor Q6 is not caused. It gets very small. After the hysteresis comparator 23 compares the voltage Vseta and a reference voltage Vref, for example 66mV, the voltage Vseta is still greater than the reference voltage, the stop charging signal (E〇c) remains at the low level*, so the charging current continues to the battery 14 Charging / When the battery voltage Vbat reaches 3.95 volts, the power management circuit 4 will change to constant voltage (cv) mode, and the battery voltage Vbat will continue to rise to 42 volts. When the logic control circuit 22 accepts the stop charging signal, it will control the circuit control circuit 21 to turn off the power transistor Q2, so that the voltage of the battery 14 reaches the saturation voltage of 4.2 volts to stop charging. In this embodiment, the offset voltage compensating element Vos1 is illustrated as an internal component of the amplifier 24, but in fact the offset voltage compensating element VqsI does not have to be disposed inside the amplifier 24; and the 'offset voltage compensating element Vosl can be The entity's element is not a real component. # When the offset voltage compensating element Vosl is a solid component, as shown in the fifth thief, the offset electrical compensation component Vgs1 is, for example, the external or internal resistance Ri of the amplifier 2Λϋ24 (the resistance ri may not be a solid-dump or external element). When the offset voltage compensating element v〇si is connected to the 1st terminal, for example, the JS voltage difference between the amplifiers 24 can be deliberately controlled on the process, for example, but not limited to, the transistor Q5 = inch and/or its voltage point can be deliberately controlled (4) The line resistance value is located in the negative wheel human terminal. The positive input offset voltage is only an example. The input offset ^ Ϊ1 is generated at the positive input terminal, but can be equivalently regarded as occurring at the negative input terminal (positive and negative values are opposite), so the offset The voltage compensating component vqs1 _ input terminal, so the embodiment should not be closed to the patent application. , in general, this creation is by providing physical or non-real _ offset voltage compensation elements ^
Vosl ’使放大n 24的等效負輸人端偏移電壓為零或小於 效正輸入端偏移電壓為零或大於零），贿決過早停止充電的 問題。 此外，偏移電壓爾元件Vgs1亦可不為單純的電阻幻， 而以為自動偏移(aut〇matic 〇ffset)電壓產生電路、自動偏移 電壓消除(automatic offset canceiiation)電路或自動調零 (automatic細adjustment)電路；以上電路例如如第6圖所 示，可包含偏移電壓偵測電路61和補償電壓產生電路纪，以參 自動偵測輸入偏移電壓而產生對應的補償電壓。又，如圖所 不，除功率電.晶體Qi及Q2外，其他電路可以整合於一;源 管理控制電路47内；當然，如製程整合可行，亦可以將功率 電晶體Q1及Q2—併整合於該電源管理控制電路47内。 ^ 以上已針對較佳實施例來說明本創作，唯以上所述者，· 僅係為使熟悉本技術者易於了解本創作的内容而已，並非用 來限定本創作之權利範圍。在本創作之相同精神下，熟悉本 技術者可以思及各種等效變化。例如，實施例中圖示直接連 M428406 接的兩電路或元制，可插置;ϊ；辟主要魏的其他電路或元 件；又如，放大器或比較電路之輸入端正負號可以互換，只需 在電路中_應的修改等。本創作的翻應涵蓋上述及其他 所有等效變化。 ^ 【圖式簡單說明】 第1圖顯示先前技術電源管理電路之示意圖。 第2圖顯示先前技術電源管理電路之示意圖。 第3圖係第2圖中各電壓及電流之波形圖。Vosl ' makes the equivalent negative input offset voltage of the amplified n 24 zero or less than the positive input offset voltage is zero or greater than zero), bribing the problem of prematurely stopping charging. In addition, the offset voltage component Vgs1 may not be a simple resistor illusion, but an automatic offset (aut〇matic 〇 ffset) voltage generating circuit, automatic offset voltage cancellation (automatic offset canceiiation) circuit or automatic zero adjustment (automatic fine The above circuit, as shown in FIG. 6, may include an offset voltage detecting circuit 61 and a compensation voltage generating circuit to automatically detect the input offset voltage to generate a corresponding compensation voltage. Moreover, as shown in the figure, in addition to the power, crystal Qi and Q2, other circuits can be integrated into one; the source management control circuit 47; of course, if the process integration is feasible, the power transistors Q1 and Q2 can also be integrated. In the power management control circuit 47. The above description has been made with respect to the preferred embodiments, and the above descriptions are merely for the purpose of making the present invention easy to understand the content of the present invention, and are not intended to limit the scope of the present invention. In the same spirit of the creation, those skilled in the art can think of various equivalent changes. For example, in the embodiment, the two circuits or elements directly connected to the M428406 can be inserted, and the other circuits or components of the main Wei can be inserted; for example, the input and the negative signs of the amplifier or the comparison circuit can be interchanged. In the circuit _ should be modified, etc. The translation of this creation covers all of the above and all other equivalent changes. ^ [Simple Description of the Drawings] Figure 1 shows a schematic diagram of a prior art power management circuit. Figure 2 shows a schematic diagram of a prior art power management circuit. Figure 3 is a waveform diagram of each voltage and current in Figure 2.
第4圖顯示本創作電源管理電路之示意圖。 第5圖顯示本創作另一電源管理電路之示意圖。 第6圖顯示本創作偏移電壓補償元件的另一實施例，其可自 動偵測輸八偏移電壓而產生對應的補償電壓。 【主要元件符號說明】 10控制電路 14電池Figure 4 shows a schematic diagram of the author's power management circuit. Figure 5 shows a schematic diagram of another power management circuit of the present invention. Figure 6 shows another embodiment of the present offset voltage compensating element that automatically detects the input offset voltage to produce a corresponding offset voltage. [Main component symbol description] 10 control circuit 14 battery
63補償電壓產生電路 EOC停止充電訊號 Ibat' Iseta 電流 Q1〜Q2功率電晶體 Q3〜Q6電晶體 R1電阻 Vbat電池電壓 Vin輸入電壓 Vos輸入偏移電壓 Vosl偏移電壓補償元件 Vref參考電壓 Vseta電壓 21 CC/CV7APPM迴路控制電 路 22邏輯控制電路 23磁滯比較器 24放大器 40電源管理電 45第一驅動電路 46第二驅動電路 47電源管理控制電路 61'偏移電壓彳貞測電路 M42840663 compensation voltage generation circuit EOC stop charging signal Ibat' Iseta current Q1~Q2 power transistor Q3~Q6 transistor R1 resistance Vbat battery voltage Vin input voltage Vos input offset voltage Vosl offset voltage compensation component Vref reference voltage Vseta voltage 21 CC /CV7APPM loop control circuit 22 logic control circuit 23 hysteresis comparator 24 amplifier 40 power management power 45 first drive circuit 46 second drive circuit 47 power management control circuit 61 'offset voltage detection circuit M428406
Vsys系統電壓Vsys system voltage