TWM421590U - Multi-chip package structure with an inductor die - Google Patents

Abstract

A multi-chip package structure comprises a packaging substrate, a first die, a second die and a first conducting wire. The first die is located on a face of the packaging substrate and has an upper surface with a first conductive connection point. A second die is also located on the face of the packaging substrate and has a first inductance pattern. The first inductance pattern has at least three second conductive connection points which define at least two different inductance values on the first inductance pattern.

Description

M421590 V. New description: [Technical field of creation] Kind of inductor crystal === package structure 'Specially about - [Prior Art] Electricity: City ίίΐ Electricity: Light and thin for a short time, its internal volume and weight are reduced The page design of t. Therefore, in order to achieve the concept of 'so only use a single package: integrated into the integration can also reduce the cost of packaging _ day _ work f, multi-vendor design and development direction.曰片包装,,,. Structure, has been Xu, is currently on the market, the development of multi-chip wafers, the vertical direction of the multi-chip integration of the two crystal layers of each layer, the increase of ==== meter has a constant D two = map The product is tender and tender (b..). The connection point between the inductor L and the switch member M and the capacitor c?: When the switch device is turned on (0N), the function of the sense L is charged 曰f C rises. . Therefore, in order to increase the value of wafer integration, look for a practical inductor crystal $' and fine-type can simplify the integration of the county's inductor chip integrated into the county of the Qing element, for the current important class of wafers, hungry Characteristics, the current is still maintained in the original flow direction, here in the release (10) (four) 'county · storage amount conversion M421590 title [new content] film, the main goal of providing - kind of inductor crystal core r increase to achieve the above purpose, this The creation provides a content ^ chip domain structure including: - carrier board, 1 3 S S chip zip structure. The multi-wire, wherein the first wafer is located on the surface of the carrier, and: the upper surface has a first electrical connection - 曰:, a table, the same carrier surface, and has a first electrical 5; ': has at least nf 纽 layer with the first wafer. The first-inductive pattern layer and the first electrical connection point of the king are used to define at least two different inductance values. On the pattern of the thief's pattern, the pattern of the 疋 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ V four corners. The at least one second electrical connection point is located in the spiral circle & the first implementation, the aforementioned (4) layer has at least one electric/life connection point between the two corners of the spiral circle. The first guide In one embodiment of the present creation, the aforementioned _曰. The first conductive pad (c〇ndu~• is located at the 笫: the connection is the 43th edge. The second electrical connection point is transmitted through the first-wire structure”

In an embodiment, the second wafer further includes a -th-ray pattern layer located under the first inductor pattern layer, and the second inductor pattern 忿J-2(2) is through the third electrical connection The point further includes an electrical connection of a package pin f^TMJt'--the actual chip system, which is a metal oxide half field effect crystal (MOSFET) layer, and the second chip further includes a spacer , 'Multiple; Difficult to knot contains a load plate in the first one』; Plate and according to ^ ^ Inductive sense ^^^^ (10) Delete - paste layer material can be simplified (4) under (4) material and the drawing M421.590 [ Embodiments Fig. 2 shows a preferred embodiment of the present invention. The inductor chip 200 includes a substrate 210 and a first inductor pattern layer 22A. The first inductive pattern layer 220 is on the substrate 210 and has at least three second electrical connection points 221 222, 223. This _inductor_layer 22() is exemplified by a spiral pattern layer, but this creation does not relate to a spiral pattern layer. Secondly, this embodiment adopts a quadrilateral job as a touch with the layer _, but the creation is not limited thereto. The first inductor pattern layer can also be designed in different shapes such as a circle, a triangle, a pentagon, and a hexagon. In addition, the two first electrical connection points 221, 223 on the first inductive pattern layer 22G of the present embodiment are respectively located at their end points, and at least one second electrical connection point 222 is distributed between the end points. The user can select two of the second electrical connection points, _^ points and output points, among the electrical connection points 221, 222, 223. Record the number of laps of the 杂 杂 与 与 与 丨 丨 ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ In other words, if three second electrical connection points 221, 222, 223 are provided, two different number of turns (two electrical connection points 223 and second electrical connection points 221) can be deduced. 222, the second electrical connection points 223 and 22 are illusory to raise two different inductance values. Accordingly, if the number of second electrical connection points 221, 222, 223 disposed on the first inductance pattern layer is increased, Define more sets of different inductance values. Therefore, according to the inventive inductor chip 2〇〇, multiple sets of inductance values can be obtained without increasing the volume of one, in order to meet the designer's requirements. Secondly, the second electrical connection points 221, 223 of the embodiment are respectively located at the two ends of the inductor pattern layer 220. However, the present invention is not limited thereto, and is formed on each of the second inductive pattern layers 220. The electrical connection points 221, 222, 223 are not necessarily located at the end of the first inductor pattern layer 220. However, by providing the second electrical contacts 221, 223 at the end of the first inductor pattern layer 220, the first inductor pattern layer can be provided. 220 has the largest inductance value. ', 6 M421590 Figure 4; layer four camps in order to = better empty this = shape layer of the two end points are located in 2 Luo: Γ 在 in the innermost second electrical connection please = the first electrical connection point 223 The spiral trace between the two electrical connection points 222 'is located in different spiral circles'

= The distance becomes smaller, in order to effectively utilize the inductor chip 2. J, J J J J Next, the position of the second electrical connection point 222 can also be located: as shown in the first figure, this embodiment is to arrange the second electric S3 horizontally to facilitate the wire connection step Into ί. Ί-ί - , ^ 排 歹 1 接 2, in a staggered manner along the horizontal direction of the wafer 3A shows the creation of an inductor chip T shown in the figure T snow figure / 曰 inductor chip 2 〇 0, along The dotted line from ^安\思='匕Inductance Crystal Moon has an upper conductive pattern and a lower layer conductive pattern factory. The layer conductive pattern includes the first inductive pattern layer 220 and the plurality of second elements; the ohmic field is prevented from affecting the electromagnetic induction of the inductor chip. The first conductive pattern ΐ 220 is connected to one end of the first conductive structure (10) through the insulating layer. The first wire structure 7 M421590 is electrically connected to the corresponding other end through the first first conductive structure 340 of the first conductive pad 370. Similarly, the second electrical connection point 221 located at the innermost side of the first inductor pattern layer 22 can also utilize the first conductive structure 34 and the first conductive connection = the first conductive pad, on the wafer 4 The H 〒 pad 3_ ' can be used as the current input point and output of the inductor chip 2 . to facilitate the subsequent wire bonding and test process of the inductor chip 200. The position of the first conductive pads 360, 370 is located on opposite sides of the inductor chip 2, so as to facilitate the connection between the wafer and the sealing foot when the subsequent county is wired, and the metal wires are prevented from contacting each other. However, the relative position can also be changed according to the space paste on the wafer, the inductance value design and the requirements of subsequent processes. ^ For example, these conductive pads can be placed around the thin sides of the inductor wafer, and on the opposite side. 4A to 4C show a preferred embodiment of the present invention. The inductor chip has a plurality of inductor pattern layers stacked on the substrate to increase the inductance of the inductor chip 200. This embodiment is described by taking a two-layer inductor pattern layer as an example. Fig. 4A shows the second inductance pattern layer ϋ' located in the lower layer, and the fourth figure shows the first inductance pattern layer 22 位于 located in the upper layer. Fig. 4C is a cross-sectional view of the inductor wafer 200 of Fig. 4B, which is extended by a broken line bb. As shown in the figure, the second inductor pattern layer 420 has a second electrical connection point 421 and a second electrical connection point 423. The second electrical connection point 421 is used to connect the first inductor pattern layer 220. In this embodiment, the second electrical connection point 421 is located at the innermost side of the second inductor pattern layer 420, and the third electrical connection point 423 is located at the outermost side of the second inductor pattern layer 420. However, this creation is not limited to this. The first inductor pattern layer 420 can also be connected to the first inductor pattern layer 220 through electrical connection points disposed at other locations. The electrical structure 440 is electrically connected to the second second conductor 42. In addition, it is located outside the red electrical connection point of the wafer thin layer for wire connection. Thus, % 423 is exposed to the output point, and the ti value input point of the 峨 峨 domain W _ in this embodiment, the first inductance pattern layer 22 〇, the spiral of the system 221 : the second electrical connection of the inner side The connection point 421 ^h layer fG ' is rotated by the inner second contact point 423. When the second electrical connection j 423 on the outer side of j is out of the second electrical connection 423 423, the current direction is the first polarity == when the inductance (10). The electrical connection points of the layers are connected so that the inductance chip (4) senses the value, which can be added according to the designer's needs. At the same time, 'the integrated wafer can also be overcome. According to the above-mentioned inductor chip, the present invention also provides a preferred embodiment, as shown in Fig. 5. This multi-chip package-carrier board 5. 2. at least one and carrier board 5.2 phase separation package Ί 一 M M421590 first-wafer 50-inductor chip and a package 5〇7. As shown in the figure, the carrier 502 also has a package pin 5〇6 standing on the load The upper surface of the plate 502. The upper surface of the first wafer 5〇1 has a first electrical connection point 5011. The package 5〇7 will be the first wafer 5〇i, the electric film 2〇〇, the carrier board 5〇2 and sealing pins 5〇6, package pins 5〇5 are packaged inside to protect the functions of these components. ^ The first crystal sa-mounting chip 1 can be a switching element chip or a control circuit chip Because the switch element* is used in conjunction with the Wei piece, here the switching element is taken as an example, but not for the two-purpose range. The second chip is the above-mentioned inductor chip · 'and ίίΐ connection point to choose. Figure 5 Show two of them are connected by ί ΓΤ 521 521, 522. As shown in the figure, the inductor chip 2 同一 is on the same side as the panel 5 〇 2, and the Electrical connecting point

The first wire 503 is electrically connected to the first electrode of the first wafer, and the connection point 5011. The inductor chip 2 has a 522, ^ 5 〇 4. Next, the carrier 502 is usually made of a conductive material. If the first wafer has an electrical connection point, it is also connected to the carrier 5〇2 to receive or input the number. Next, the package pins 5〇6 connected to the carrier 502 can also be used as a reference potential. The package body 507 can expose the unexposed surface of the carrier 502 as a heat sink to enhance the heat dissipation capability of the multi-pack package structure 500. The setting of the first wafer 5〇1 and the inductor chip 曰?^ can also be interchanged. Inductive 曰 曰 路 ( b b 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 请 521 521 521 521 521 521 521 521 521 521 521 521 It is electrically connected to the package pin 5G5 to the power supply 10 M421590 input terminal Vin. In addition, depending on the application requirements of the inductor chip 2GG, the polycrystalline 500 is also used to package more than three chips in a single one, and the second electrical connection point on the inductor crystal lion is selected. = two wafers (not shown). Accordingly, the second inductive chip 2 of the present invention is selected to be connected to the second electrical connection point 521 52 ancient # + Guang Bulian

To the package pin 505, the two second ^^^=^ connections can also be connected to other above-mentioned new connection points, and the H-average of the end-view circuit is limited to the preferred implementation of the present implementation. For example, when you can't explain the content clearly! *®, which is within the scope of the patent application and coverage of New Zealand. The other equivalent changes and modifications are still the invention patents. Any embodiment or patent application scope that is created by the creation of this creation is not required and the title is only used for all purposes or advantages or features of g. In addition, the scope of the rights in the summary section. The use of patent documents for searching is not intended to limit the creation of this document. M421590 [Simple Description] The first is a circuit diagram of a typical boost circuit. Figure 2 shows a preferred embodiment of an inductive chip of the present invention. Fig. 3A shows another preferred embodiment of an inductor chip of the present invention. In the third embodiment, the inductor chip of FIG. 3A is not shown in FIG. 3A, and the cross-sections of FIG. 4 to FIG. 4C show that one of the multilayer inductor chips is preferably.

example. I Figure 5 shows the present invention - a multi-chip package structure - a preferred embodiment (

[Main component symbol description] Inductor L diode element D Capacitor C Switching element 电感 Inductor chip 200 Substrate 210 First inductance pattern layer 220 Second electrical connection point 221, 222, 223, 421, 521, 522 First wire structure 330 First conductive Structure 340 Channel 350 First conductive pad 360, 370 Isolation layer 380 Second inductance pattern layer 420 Third electrical connection point 423 Second conductive structure 440 Opening 450 Multi-chip package structure 500 First wafer 501 First electrical connection Point 5011 12 Μ42Γ590 Carrier 502 Carrier Surface 5021 First Conductor 503,504 Package Pin 506, 505 Package 507

Claims (1)

Patent application scope: 1. A multi-chip package structure, comprising: a carrier plate; a first wafer on one side of the carrier plate, having a first electrical connection point; /, an upper surface, the upper surface a second wafer on the side of the carrier, the first inductive pattern layer having at least: a first-first inductor pattern layer, a different inductance value; and two electrical contacts. connection. "The first electrical connection point and one of the second. The polycrystalline inductive pattern layer system of the scope of claim 1 - spiral_layer' wherein 'the first 3. as claimed in claim 2 A plurality of the second electrical connection points are located at the corners of the at least two or two wafers. Throwing, rotating, and corresponding to the fourth electric/graph, wherein the first, each of the spirals has at least four electric connection points of the two corners of the spiral ring . The multi-chip package structure of the first paragraph of the first patent of the ninth patent, wherein the second crystal H-line structure is located below the first-inductive pattern layer and ^ (conductive pad), the ;; = second electrical connection point By ^^ M421590 7曰片^: The first multi-chip package structure of the first item, wherein the second inductive pattern layer and the first-electrode layer are downward, and the second The inductor pattern layer is transmitted through a second rotating square-inductive pattern layer. Waiting for electricity, ,,. The electrically connected structure is 8. The multi-chip inductor pattern layer of claim 7 further includes a third electrical connection point. The second electrical connection point of the younger brother is bare. 9. If the multi-chip seal is applied for in the scope of patent application, the second electrical connection point is electrically connected. .八中'At least one 10. As claimed in the patent, the multi-chip package structure of the i-th item of the patent range is a metal oxide half field effect transistor (M0SFET). , k曰日片 11. The multi-chip package structure of claim i, wherein the chip further comprises an isolation layer over the first inductor pattern layer. Μ第一Μ12. If the multi-wafer sealing structure of the scope of the patent application is further included, the carrier, the first wafer, the second wafer=, the first wafer is exposed The surface of the multi-chip package structure of claim i, further comprising: 'a second wafer; and a second wire electrically connecting the third chip to the second chip Electrical connection point. An inductive wafer 14 includes: a substrate; and a first inductive pattern layer on the substrate and having at least three second electrical connection points to define on the first inductive pattern layer At least two different inductance values. The inductor chip of claim 14, wherein the first inductor layer is a spiral pattern layer, the spiral pattern layer having at least two turns: a coil has at least four The corner 'and at least one of the second _ transport points' are located at the corner of the spiral. 15 shape Cheng (9) 'the towel, at least two of the difference, is different from the spiral circle, and corresponds to a second wafer 1 Figure 7 fortunately the 14th inductor chip '*, the first inductance Circle: ί ί 旋 图案 图案 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' .7 The first electrical property 18·=Application for the patent range 帛17 of the inductor chip, in which at least 忑isheng is located in the different spiral circle, and presents a staggered arrangement of two-junction such as the inductance of the 14th patent The wafer further includes: 'below the first-inductive pattern layer; and, at least one of the two 0r:c:r, epad), strictly: the first conductive "." connection on the upper surface edge of the second wafer Point system, through the first-wire structure electrical connection 20. As claimed in the patent model 14 of the inductor chip electric port: ίίΐίΓ below the layer, the second inductor ί ! ! ί ί ί ί ί ί ί ί ί ί ί ί The second inductor pattern layer is electrically connected to the first inductor pattern layer. The inductor layer of the item 20 of the patent range further includes H-links. Above the first inductor pattern layer, and the day and day, including an isolation layer