TWM419967U - Multi-phase switching regulator and droop circuit therefor - Google Patents

Description

M419967

V. New description: [New technical field] This creation is related to a multi-phase switching power supply and a falling signal generating circuit for the same, especially a kind of >[measurement of the complex switch group] The total current 'to adjust the output voltage of the multi-phase switching power supply and the falling signal generating circuit therefor. [Prior Art]

Figure 1 shows a circuit diagram of a Dober switched power supply of U.S. Patent No. 6,683,441. As shown in Fig. 1, the sum circuit 25 includes two resistors Rp, one end of which is connected to the corresponding phase node, and the other end is connected to the sum node 26. Amplifier circuit 28 includes amplifier A1' having an inverting input coupled to sum node %; and a non-inverting input coupled to output voltage V〇ut. The feedback resistor sets the gain of amplifier A1, and the wave capacitance ces is connected in parallel with the feedback resistor core. The output voltage Vcs of amplifier A1 can be expressed as:

—AJ

Where R1 is the parasitic series resistance of each inductor, s is the variable symbol in the Laplace Transform, and lQut is the total output current. First, adjust the capacitance time constant 仏 to make it equal to the total inductance time constant. In addition, by the adding circuit 3 (), the output voltage vcs of the amplifier Ai is subtracted from the output voltage v 〇 ut, as shown in the figure, to generate a droop voltage Vdro 叩 as follows: 3 RP (10) Therefore, a falling voltage is obtained Vdr〇〇p is proportional to the total output current u. The falling voltage Vdroop can provide various functions, for example, to detect the total current and perform over current protection (OCP), or in some applications, it is necessary to control the relationship between the output current and the output voltage. The falling voltage vdraQp adjusts the output voltage for dr 〇〇p control. In this prior art, the filter capacitor Ces and the feedback resistor are too large to be integrated into an integrated circuit in a typical application. (Integrated circuit, IQ chip. Therefore, the redundant chip must be added to the pin to be coupled with the filter capacitor Ccs and the feedback resistor & also increase the manufacturing cost. Figure 2 shows the US Patent No. 7, 〇 The falling signal generation circuit of No. 64, 528 shows the schematic diagram. As shown in Fig. 2, the complex phase node ρΗ1·ρΗΝ is connected to the corresponding electric HER1-RN end #, and the other of the resistor phantom-Xin and the amplifier A2 are non-reverse. The phase input terminal is lightly connected. The output voltage is lightly connected to the inverting input terminal of the amplifier A2 via the resistor RA; the capacitor CA is lightly connected to the non-inverting input terminal of the amplifier A2 and the output voltage ν〇υτ, ' The resistance RB is lightly connected between the inverting input terminal of the amplifier A2 and the output end of the amplifier A2; the feedback resistor Rc is coupled to the non-inverting input of the amplifier, and is still input (four) voltage v〇UT H capacitance CB secret output VOUT and Amplify the output between n A2. The output of amplifier A2 is used as the red terminal of the falling power_VDROOP, and the output voltage ν〇υτ is used as the negative terminal of the falling voltage signal VDROOP. The same 'by setting the parameters of each component appropriately, The signal VDROOP can be compared with the readout (four) f-dimensional current protection and descent control. The third figure shows the declining signal generation circuit of US Patent Application No. 2009/0051334. The PHUHN is correspondingly shown in Figure 3. The new leg is deleted: the other end of the resistor RPm-RPHN is connected to the amplifier 52. The output voltage is biased via the resistor RCS _ to the amplifier 52 〇 $ phase input terminal; the capacitor C1 is connected to the non-inverting input of the amplifier 52 〇 The output voltage of the terminal disc is between Vbut. The output of the amplifier 52〇 provides a falling current signal 1*.

I(10)乂 DCR T - N * droop ~Γ one -

RCS where Ν is the number of phase nodes, J(10) is the total output current, and ^^ is the individual parasitic resistance of the inductors L1-LN. Falling current signal ^.叩 is proportional to the output total current IQut, and the rib axis can be protected and lowered. In the prior art of Figures 2 and 3, 'each phase node requires a connection-resistance, and the other end of the resistor must be connected to the non-reverse terminal (two impedance terminals) of the amplifier to maintain the total current. The formula for sensing. In addition, the output voltage Vbut must be connected first to the -resistor and then to the inverting terminal of the amplifier, ie the amplifier cannot be directly connected to the output voltage v〇ut. This arrangement limits the circuit design flexibility of both prior art. In view of the above, this creation is directed to the deficiencies of the prior art, and proposes a multi-phase switching power supply and a falling signal generating circuit therefor; the falling signal generation can reduce the pins of the Ic chip and increase the circuit. Design flexibility. [New content] The purpose of this creation is to provide a multi-type (four) conversion power supply and a falling signal generation circuit therefor. For the above purposes, in one of the points of view, the present invention provides a multi-phase switching power supply comprising: a plurality of switch groups for generating: an output voltage at an output node 'each of which includes a phase a node, the plurality of switch groups respectively receive a corresponding driving signal to switch at least one of the power switches to generate the output voltage; a plurality of output inductors respectively coupled between the phase node and the output node; a pulse width modulation ( a pulse width modulation (PWM) circuit for generating a plurality of PW1Vs [signals, controlling the plurality of switch groups; and a down signal generating circuit for providing a down signal, the down signal being related to a current generated by the plurality of phase nodes The sum of the falling signal generating circuit includes: a plurality of first resistors respectively coupled to the corresponding phase node to sense a current generated by the corresponding phase node; a second resistor coupled to the plurality of first resistors An error amplifier 'haves an inverting input and a non-inverting input, the inverting input and the second The resistor is coupled to the output of the error amplifier, and the non-inverting input of the error amplifier is coupled to the output node; and a falling capacitor is coupled between the second resistor and the output node; The falling signal generating circuit provides the falling signal according to the voltage drop or current on the second resistor. In order to achieve the above purpose, in another aspect, the present invention provides a descent signal generating circuit for a multi-phase switching power supply, comprising: a plurality of first resistors respectively coupled to corresponding nodes for sensing Corresponding current; a second resistor coupled to the plurality of first resistors; an error amplifier having an inverting input and a non-inverting input, the inverting input coupled to the second resistor, and The non-inverting input of the error amplifier is coupled to the output node; and a falling capacitor is coupled between the second resistor and an output node; wherein the falling signal is The generating circuit provides the falling signal according to the voltage drop or current on the second resistor, and the falling signal is related to the sum of the currents sensed by the plurality of first resistors. In one embodiment, the current on the second resistor and the voltage drop across it should have a relationship of 卞: V^=in{sL^DCRx)-Vcx^I12{sL2 + DCR^_v^ I, AsL ^DCRn)-V„

R: R»' ~ . Tpn sC where ' ι is the current on the second resistor, the heart and Vcx are the resistance of the second resistor and the voltage drop thereof, iL1, I12, lLn are the phase nodes The resulting inductor currents 'Li, L2, Ln are the output inductors 'DCR', DCR2, DCRn are the parasitic resistances of the respective output inductors, Rp丨, Rp2, Rpn are the resistance values of the first resistors 'Cx is the falling capacitor, and s is the sign of the Laplace Transform and η is the number of phases of the switch group. In another preferred embodiment, the complex output inductor has the same inductance value L; and the complex output inductor parasitic resistance also has the same resistance value DCR; further, the plurality of first resistors also have the same resistance value Rp; Vc _ 1 total {sL + DCR)-nV_. R ~R sCxV〇x

The relationship between x P and current reduction is: Where 'Itotal is the sum of the currents generated by the phase nodes. In another preferred embodiment, the resistance values of the falling capacitor 匕 and the second resistor Rx are respectively set to be: 1 + i - L - _ DCR 1

Rd

~ + n + sCxRp K

Eight X c x DCRRp

Rx=-^~ K-n The details of the creation, the technical content, the features and the effects achieved by the present invention are more easily explained by the specific embodiments. [Embodiment] Please refer to Fig. 4' to show an embodiment of the present creation. As shown, the multi-phase switching power supply 10 includes a complex switch group 11, a complex output inductor Li_Ln, a complex drive circuit 12, a pulse width modulation (PWM) circuit 13, and a down signal generation circuit 20. The PWM circuit 13 generates a plurality of PWM signals according to the output voltage v〇ut and the falling current 以 to input the complex driving circuit 12, respectively, so that the complex driving circuit 12 respectively generates driving signals to respectively operate the complex switch group 11. The driving circuit 12 functions to generate a driving voltage sufficient to drive the switch group u. If the PWM circuit 13 itself outputs a signal having a sufficient level of electrical waste, the driving circuit 12 can be omitted or integrated in the pwm circuit 13. Each switch group 11 includes, for example but not limited to, an upper bridge switch Qi and a lower bridge switch Q2 (the lower bridge opens M Q2, which can also be changed to a diode element); each switch group 11 inputs the input voltage Vin according to the corresponding drive signal. Converted to an output voltage V〇ut; wherein each switch group 11 includes phase nodes PH!, PH2, or PHn, and the like. And the plurality of output inductors are respectively reduced between the phase node PHrPHn and the output node ν〇ω; and the output inductor L mountain respectively includes the parasitic resistance DCR^DCRn 〇 and the falling signal generating circuit 20 is lightly connected to the complex phase node PHrPHn for Sensing the current generated by the complex phase node to provide the falling current as a falling signal, which may be provided, for example, to the PWM circuit .13 (as shown) or to other circuits, such as to the load circuit ( Not shown). Wherein, the falling current ι is related to the sum of the currents generated by the complex phase nodes ΡΗι_ΡΗη. Fig. 5 shows a more specific embodiment of the present descending signal generating circuit 2. As shown in Fig. 5, the down signal generating circuit 2A includes a plurality of first resistors RprRpn, a second resistor rx, an error amplifier A, and a falling capacitor cx. The plurality of first resistors Rpl_Rpn are respectively coupled to the corresponding phase nodes PH1-PHn to sense the current generated by the corresponding phase node PHrPHn. The second resistor Rx is coupled between the plurality of first resistors Rpi_Rpn and the inverting input terminal of the error amplifier A (that is, the sensing sum current CS-SUM contact). The inverting input of the error amplifier a is selected in addition to the first resistor Rx and is coupled to the output of the error amplifier A. The non-inverting input of the error amplifier A is coupled to the output node v〇ut. The falling valley Cx is consumed by the second resistor Rx and the output node \^. In the middle of the hunger, the falling signal generating circuit 20 provides the falling current Ix' and the falling current Ix is related to the sum of the currents generated by the complex phase node ΡΗη according to the second resistor Rx and the voltage drop v thereon. In detail, according to the working principle of the error amplifier, the voltage drop across the second resistor and the falling capacitor is the same as Vex. Therefore, the falling current Ix flowing through the second resistor Rx can be expressed as: Υ_α - Ili (sL' + DCR ', — vj ( τ r>r*r> Λ , / Τ--R~~+ ...)-κ χ JVpI D π ----< Ρ2 % /, respectively, indicating the first resistance The resistance of the two resistors, L, II2, ILn are the currents generated by the phase nodes pHrpHn, DC% DCR_2, 〇CRn are the parasitic resistances of the output inductors L "Ln, and s is the Laplace transform (Lapiace Transf The variable symbol in 〇rm), n is the number of phases of the switch group. Consider that the complex output inductor LrLn has the same inductance value L; and the parasitic resistance DCRrDCRn of the complex output inductor LrLn also has the same resistance value DCR; The resistance also has the same resistance value Rp; then the relationship of the falling current ιχ is: where Itotal is the sum of the currents generated by the phase nodes. I —匕_ ^total' DCR) — n Va where, such as 1 + ί 丄, a DCR 1 Έ =7 ^- + n + sCxRp can simplify the total

•DCR

K, that is, the crossover vcx of the second resistor Rx can be used to provide a total current or a falling current Ix (=Vex/Rx 'Rx is a known constant) or can be used to provide information on the total current. According to the desired K value, the resistance values of the falling capacitor 匕 and the second resistor core can be respectively set as: c x DCR Rp

Rx=-^~ Kn Compared with the multi-phase switching power supply of the prior art, US Patent No. 6,683,441 'Because of the prior art, the filter capacitor Ccs and the feedback resistor 5 have a large area and cannot be integrated into 1C. In the chip, therefore, it is necessary to add a pin to be coupled with the filter capacitor Ccs and the feedback resistor, and this creation does not require this, thereby reducing the pin, reducing the manufacturing cost, and increasing the application range of the circuit. Compared with the falling signal generating circuit of US Patent Application No. 2009/0051334, the advantage of this creation is that the non-inverting input of the error amplifier A is directly and outputted in the present creation. The voltage Vout is connected, and all of the foregoing prior art must first be connected to a resistor to reconnect to the output voltage Vout. Since the switching power supply's control 1C chipbook needs to provide a pin that is connected to the output voltage, this creation can utilize the existing pin, which requires an additional pin and resistor RA compared to the prior art. Or RCS connection (that is, the prior art requires two pins of the error amplifier and the output voltage v〇ut three pins, and this creation only requires two pins of CS-SUM and output voltage Vout), this creation can reduce the pin to Reduce manufacturing costs and increase the range of applications for the circuit. The present invention has been described above with reference to the preferred embodiments, and the above-mentioned escaping is only for making it easy for those skilled in the art to understand the contents of the present invention, and is not intended to limit the rights of the present invention. In the same spirit of the creation, those skilled in the art can think of various equivalent changes. For example, Figure 4: Paint = Supply the falling current Ιχ to the PWM circuit 13 as a falling signal, ^ If the voltage across the voltage Vcx of the second resistor Rx can also be used to provide information about the total power ^ The cross-voltage % of the two resistors Rx is supplied to pwM = way 13 as a down signal. As another example, in the circuits of the various embodiments shown, components that do not affect the primary meaning of the signal, such as other switches, etc., can be broadcast. Therefore, all of the various equivalent changes should be included in the scope of this creation. [Simple description of the diagram] Figure 1 shows the circuit diagram of the multi-phase switching power supply of the US patent case No. Figure 2 shows a schematic diagram of the falling signal generating circuit of U.S. Patent No. 7,064,528. Figure 3 shows the schematic diagram of the falling signal generation circuit of the US Special Case No. _5丨 334. Figure 4 shows an embodiment of the present creation. Fig. 5 shows a more specific embodiment of the present descending signal generating circuit 2(). [Main component symbol description] 28 amplifier circuit 520 amplifier A, A1, A2 error amplifier C1, CA, CB capacitor Ccs filter capacitor CS_SUM sense sum current Cx drop capacitor 10 multi-phase switching power supply 11 switch group 12 drive circuit B PWM circuit 20 down signal generating circuit 25 sum circuit 26 sum node 12

Claims (1)

9 Touching the first month of the month, the application of the amendment page (no underline version) VI. Patent scope: 1. A multi-phase switching power supply, comprising: a plurality of switch groups for generating an output voltage An output node, wherein each of the -on_including-her nodes' receives a corresponding driving signal to switch at least one of the power switches to generate the output voltage; the plurality of output inductors are coupled to the phase node and the Between the output nodes; a pulse width modulation (PWM) circuit for generating a complex PWM signal to control the plurality of switch groups; and a down signal generating circuit for providing a down signal, the down signal The falling signal generating circuit includes: a plurality of first resistors coupled to the corresponding phase nodes to sense a current generated by the corresponding phase node; a second resistor coupled to the plurality of first resistors; an error amplifier having an inverting input and a non-inverting input The inverting input is coupled to the second resistor and coupled to the output of the error amplifier, the non-inverting input of the error amplifier is coupled to the output node; and a falling capacitor coupled to the second Between the resistor and the output node; wherein the falling signal generating circuit provides the falling signal according to the voltage drop or current on the second resistor. 2. The multi-phase switching power supply according to claim 1 The current on the second resistor and the voltage drop thereon have the following relationship: 乂M419967 Patent Revision No. 1002丨3209 (without scribe line) I == ”L2(sL,+ DCR,, -V z R, R, ~ ^ tifo fvna supplement; + R ^{sL^DCR )-17 ~~J~nJ—^-sCxVcx where lx is the current on the second resistor, rx and Vcx are respectively The resistance of the two resistors and the voltage drop on them, ili, ils, iLn are the inductor currents generated by the phase nodes, L, L2, Ln are the output inductors, and DCR丨, DCR2, DCRn are the parasitic outputs of the output inductors. Resistor, Rpi, RP2, Rpn are the resistance values of the first resistors, Cx is the falling capacitor, and s is the pull The variable symbol in the Laplace Transform, where n is the number of phases of the switch group. 3. The multi-phase switching power supply of claim 2, wherein the complex output inductor has the same inductance value L; and the complex output inductor parasitic resistance also has the same resistance value DCR; The resistor also has the same resistance value Rp; the relationship of the falling current is: 4 = 1 Mai {sL + DCR) - nVa Rx p sCxVcx P where Itotal is the sum of the currents generated by the phase nodes. 4. For the multi-phase switching power supply of claim 3, where 1 + 5~-- __DCR 1 IP = J f + n + sCxRp K and the resistance values of the falling capacitor Cx and the second resistor Rx are respectively set to: c = ruler I p Rp R, six. 5. A falling signal generating circuit comprising: a plurality of first-resistors' coupled to respective nodes to sense a corresponding current; a second resistor coupled to the plurality of first resistors; an error amplifier having an inverting input and a non-inverting input coupled to the second resistor and the error amplifier The output terminal is lightly connected, the non-inverting input terminal of the error amplifier is coupled to the output node; and a falling capacitor is coupled between the second resistor and an output node; wherein the falling signal generating circuit is configured according to the The voltage drop or current on the second resistor provides the falling signal, and the falling signal is related to the sum of the currents sensed by the plurality of first resistors. 6. The descent signal generating circuit of claim 5, wherein the descent signal is used to control a multi-phase switching power supply, each phase of the multi-phase switching power supply comprises a switch group and an output The inductor is configured to generate an output voltage at an output defect, and the switch group and the output inductor are connected to the node corresponding to the first resistor, and the current on the second resistor and the voltage drop thereon have the following relationship: "'(sl' + dcr^-v-1 L2(SL2 + DCR - V. λ" -+ · -f -Ln + v 1 --------- cx t F sC^ where ' Ix is The currents 'Rx and Vcx' on the second resistor are respectively the resistance value of the second resistor and the voltage drop thereof, and IL1, lL2, and lLn are currents sensed by the nodes corresponding to the first phase, L, L2, Ln are the output inductors, DCRi, DCR2, DCRn are the parasitic resistances of the output inductors, Rpi, Rp2, R ^ are the resistances of the first-resistors, Cx is the falling capacitor' and s is the lap: s; The variable symbol in Laplace Transform, where n is the number of phases of the switch group. For example, the falling signal generating circuit of claim 6 of the patent scope, wherein The complex output inductor has the same inductance value L; and the complex output inductor parasitic resistance also has the same resistance value DCR; in addition, the complex first-resistance also has 16 7. M419967 Patent No. 100213209 Patent Application Revision (without scribe line) The same resistance value Rp; the relationship of the falling current is Φ Ό "Correction | October 曰 Supplement 丨 ^ cx _ ^ total ~ R ~ a _ (sL + DCR) - nVa ^ χ να where Ifotal is the first resistance of the complex The sum of the measured currents. 8. The falling signal generating circuit of claim 7 wherein 1 + 5- L DCR Rn K ~^ + n + sCxRP R, and the resistance of the falling capacitor Cx and the second resistor Rx Set to KL DCRRP R RP κ 17