TWM416197U - Packaged power integrated circuit - Google Patents

Packaged power integrated circuit Download PDF

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Publication number
TWM416197U
TWM416197U TW100210836U TW100210836U TWM416197U TW M416197 U TWM416197 U TW M416197U TW 100210836 U TW100210836 U TW 100210836U TW 100210836 U TW100210836 U TW 100210836U TW M416197 U TWM416197 U TW M416197U
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Taiwan
Prior art keywords
chip
printed circuit
circuit board
integrated circuit
power supply
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Application number
TW100210836U
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Chinese (zh)
Inventor
Ming-Heng Yang
Ching-Hsiang Hung
Jen-Tsung Hsu
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Abomem Technology Corp
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Priority to TW100210836U priority Critical patent/TWM416197U/en
Publication of TWM416197U publication Critical patent/TWM416197U/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Semiconductor Integrated Circuits (AREA)

Abstract

A packaged power integrated circuit is provided in this application. The packaged power integrated circuit comprises a printed circuit board, a multilayer inductor chip, a power chip and connectors. The printed circuit board comprises several circuit connecting pads. The multilayer inductor chip is mounted above the printed circuit board and comprises a multilayer ceramic capacitor structure and an internal wire which is arranged to encircle the multilayer ceramic capacitor structure for forming the inductance. The power chip is mounted above the printed circuit board. The connectors are utilized to electrically connect the multilayer inductor chip with the printed circuit board and the power chip with the printed circuit board.

Description

M416197 五、新型說明： 【新型所屬之技術領域】 本新型是有關於一種封裝電源積體電路，且特別是有 關於一種包含多層電感晶片之封裝電源積體電路。 【先前技術】 現有電源晶片常因電路架構需要而與各種被動元件在 印刷電路板上配合使用，像是電感器、電容器及電阻器等 • 等。請參考第6圖，第6圖是先前技術中繞線電感與電源 晶片共同封裝之積體電路結構示意圖。印刷電路板110上 面為了達到電路設計中的電感效應，多使用金屬繞線電感 160產生線圈效應，再結合打線與印刷電路板走線方式來 協助實現所需的電感值，然後再利用接合件150與電感晶 片140電性連接或與電源晶片130電性連接等等。可以發 現繞線的電感器實在增加了印刷電路110整體之使用面積 並具有十分複雜的佈局線路和不當的空間配置。 【新型内容】 因此，本新型之一實施態樣是在提供一種封裝電源積 體電路，包含印刷電路板、多層電感晶片、電源晶片及複 數個接合件。印刷電路板包含複數個電路連接點。多層電 感晶片係配置於印刷電路板上方，且包含積層陶瓷電容器 結構及内部繞線，内部繞線配置以圍繞積層陶瓷電容器結 構形成電感效應。而電源晶片係配置於印刷電路板上方。 複數個接合件係用以將多層電感晶片與印刷電路板之電路 4 M416197 連接點電性連接及將電源晶片與印刷電路板之電路連接點 電性連接。接合件可以為焊線或者是導電膏。 依據本新型一實施例，上述封裝電源積體電路中，多 層電感晶片可直接設置於電源晶片之上’電源晶片直接设 置於印刷電路板之上。 依據本新型另一實施例，上述封裝電源積體電路中， 電源晶片直接設置於多層電感晶片之上*多層電感晶片直 接設置於印刷電路板之上。 φ 依據本新型再一實施例，上述封裝電源積體電路中， 多層電感晶片與電源晶片以無重疊之方式直接設置於印刷 電路板之上。 藉此，本新型提出之封裝電源積體電路可以消除傳統 上利用印刷電路板上繞線以形成電感效應之製程，而大幅 地精簡空間配置達到輕薄化、低成本的效果。 【實施方式】 • 請參照第ΙΑ、1B圖，其分別繪示依照本新型第1實 施例的一種封裝電源積體電路的結構示意圖與結構剖面 圖。第1實施例之封裝電源積體電路，包含印刷電路板 110、多層電感晶片120、電源晶片130及複數個接合件 150。印刷電路板包含複數個電路連接點153。多層電感晶 片120係配置於印刷電路板110上方，且包含積層陶瓷電 容器（multilayer ceramic capacitor，MLCC)結構及内部繞 線，内部繞線配置以圍繞積層陶瓷電容器結構形成電感效 應。使用積層陶瓷電容器結構及内部繞線的多層電感晶片 5 1 高2!j以相對的減少傳統式的兩端電極，還可以輕易實現 电感值’也明顯可以減少整體的體積。 個接曰片130係配置於印刷電路板110上方。複數 Q 係用以將多層電感晶片120與印刷電路板11〇 電路連接點電性連接及將電源Μ 13()與印刷電路板 之電路連接點電性連接。接合件150可以為焊線152 2者是導電膏154。焊線152包含打金線、鋁線、銅線等 種金屬線材，而導電膏154包含锡膏、導電膠等各種導 電材料。 細言之，第1實施例之封裝電源積體電路中，電源晶 片130直接設置於多層電感晶片12〇之上，多層電感晶片 12〇直接設置於印刷電路板11〇之上。而多層電感晶片12〇 與印刷電路板110係藉由導電膏154進行電性連接，又電 源晶片130與印刷電路板no係藉由焊線152電性連接各 自之電路連接點151、153。且多層電感晶片120與電源晶 片130間也會因應電路設計而利用焊線152電性連接。也 就是說’接合件150可以利用焊線152達成效果，也可以 利用導電膏154達成效果。依據第1實施例製作之封裝電 源積體電路，其整體尺寸約為5±0.1mm X 3±0.1 mm X 1.85+0.05 mm ，比現有市面上之晶片（如：EN6337QI) 減少7成體積。 請參考第2圖，其係依照本新盤第2實施例的一種封 裝電源積體電路結構剖面圖。 第2實施例之封裝電源積體電路中，與第1實施例不 同的是：電源晶片130直接設置於多層電感晶片120之上， M416197 多層電感晶片120直接設置於印刷電路板110之上。而多 層電感晶片120與電源晶片130間，還有多層電感晶片120 與電源晶片130都是利用焊線來與印刷電路板110進行電 性連接，以符合各種電路設計之需求。 請參考第3圖，其係依照本新型第3實施例的一種封 裝電源積體電路結構剖面圖。 第3實施例之封裝電源積體電路中，與第1實施例不 同的是：多層電感晶片120直接設置於電源晶片130之上， φ 電源晶片130直接設置於印刷電路板110之上。而多層電 感晶片120與電源晶片130間，還有多層電感晶片120與 電源晶片130都是利用焊線來與印刷電路板110進行電性 連接，以符合各種電路設計之需求。當然，可想見另一種 實施態樣便是使直接設置於印刷電路板110上的電源晶片 130改成利用導電膏進行電性連接。 請參考第4、5圖，其係依照本新型第4、5實施例的 一種封裝電源積體電路結構剖面圖。 修第4實施例與第5實施例之封裝電源積體電路中，與 第1實施例不同的是：多層電感晶片120與電源晶片130 以無重疊之方式直接設置於印刷電路板110之上。 而第4實施例之封裝電源積體電路中，多層電感晶片 120與印刷電路板110係藉由導電膏進行電性連接，又電 源晶片130與印刷電路板110係藉由焊線152進行電性連 接。 又第5實施例之封裝電源積體電路之多層電感晶片 120與電源晶片130都是利用焊線來與印刷電路板110進 7 行電t連接’以符合各種電路設計之需求。 知，若應財新型之^〜卿符合RGHS，且*上述可 需預留”㈣ΐ^ί電源積體1路，則印刷電路板毋 以大幅地減少製可以增進電感器之效益，又可 線與印刷電路板走空間使用，此外由於可減少金 本。即士&線金屬材料用量，因此可有效降低成 刷雷牧Γ 型之封裝電源積體電路消除傳統上利用印 上繞線以形成電感效應之製程，而空 間配置達到輕薄化、低成本的效果。 雖然本新盤已以實施方式揭露如上然其並非用以限 二新型，任何熟習此技藝者，在不脫離本新型之精神和 =圍内，當可作各種之更動與潤飾，因此本新型之保護範 當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】M416197 V. New description: [New technical field] The present invention relates to a package power integrated circuit, and more particularly to a package power integrated circuit including a multilayer inductor chip. [Prior Art] Existing power supply chips are often used in conjunction with various passive components on printed circuit boards due to circuit architecture requirements, such as inductors, capacitors, and resistors. Please refer to FIG. 6. FIG. 6 is a schematic diagram showing the structure of an integrated circuit in which the winding inductor and the power supply chip are co-packaged in the prior art. In order to achieve the inductance effect in the circuit design, the metal winding inductor 160 is used to generate the coil effect, and the wiring and the printed circuit board routing method are combined to assist in achieving the required inductance value, and then the bonding member 150 is used. It is electrically connected to the inductor chip 140 or electrically connected to the power source chip 130 or the like. It can be found that the wound inductors increase the overall use area of the printed circuit 110 and have very complicated layout lines and improper spatial configurations. [New Content] Therefore, an embodiment of the present invention provides a package power integrated circuit including a printed circuit board, a multilayer inductor chip, a power supply chip, and a plurality of bonding members. The printed circuit board contains a plurality of circuit connection points. The multilayer inductor chip is disposed above the printed circuit board and includes a build-up ceramic capacitor structure and internal windings, the internal winding configuration to form an inductive effect around the laminated ceramic capacitor structure. The power chip is disposed above the printed circuit board. A plurality of bonding members are used to electrically connect the multilayer inductor chip to the circuit 4 M416197 connection point of the printed circuit board and electrically connect the power chip to the circuit connection point of the printed circuit board. The bonding member may be a bonding wire or a conductive paste. According to an embodiment of the present invention, in the package power supply integrated circuit, the multi-layer inductor chip can be directly disposed on the power supply chip. The power supply chip is directly disposed on the printed circuit board. According to another embodiment of the present invention, in the package power supply integrated circuit, the power supply chip is directly disposed on the multilayer inductor wafer * the multilayer inductor wafer is directly disposed on the printed circuit board. According to still another embodiment of the present invention, in the package power supply integrated circuit, the multilayer inductor chip and the power supply chip are directly disposed on the printed circuit board without overlapping. Therefore, the packaged power supply integrated circuit proposed by the present invention can eliminate the conventional process of utilizing the winding on the printed circuit board to form an inductance effect, and greatly simplify the space configuration to achieve a slim, low-cost effect. [Embodiment] Please refer to FIG. 1 and FIG. 1B, which respectively show a schematic structural view and a structural cross-sectional view of a packaged power supply integrated circuit according to a first embodiment of the present invention. The package power supply integrated circuit of the first embodiment comprises a printed circuit board 110, a multilayer inductor wafer 120, a power supply chip 130, and a plurality of bonding members 150. The printed circuit board includes a plurality of circuit connection points 153. The multilayer inductor chip 120 is disposed above the printed circuit board 110 and includes a multilayer ceramic capacitor (MLCC) structure and internal windings, the internal winding configuration to form an inductive effect around the laminated ceramic capacitor structure. Multilayer inductor wafers using a multilayer ceramic capacitor structure and internal winding 5 1 high 2!j to relatively reduce the traditional two-end electrodes, can also easily achieve the inductance value 'also significantly reduces the overall volume. The tabs 130 are disposed above the printed circuit board 110. The complex Q is used to electrically connect the multilayer inductor chip 120 to the printed circuit board 11 电路 circuit connection point and to electrically connect the power Μ 13 () to the circuit connection point of the printed circuit board. The bonding member 150 may be a bonding wire 152 2 and is a conductive paste 154. The bonding wire 152 includes a metal wire such as a gold wire, an aluminum wire, or a copper wire, and the conductive paste 154 includes various conductive materials such as a solder paste and a conductive paste. In detail, in the package power supply integrated circuit of the first embodiment, the power supply chip 130 is directly disposed on the multilayer inductor wafer 12A, and the multilayer inductor wafer 12 is directly disposed on the printed circuit board 11A. The multilayer inductor chip 12A and the printed circuit board 110 are electrically connected by the conductive paste 154, and the power source chip 130 and the printed circuit board no are electrically connected to the respective circuit connection points 151, 153 by the bonding wires 152. Moreover, the multilayer inductor chip 120 and the power supply chip 130 are electrically connected by the bonding wires 152 in accordance with the circuit design. That is to say, the bonding member 150 can achieve the effect by the bonding wire 152, and the conductive paste 154 can also be used to achieve the effect. The package power supply circuit fabricated in accordance with the first embodiment has an overall size of about 5 ± 0.1 mm X 3 ± 0.1 mm X 1.85 + 0.05 mm, which is 70% smaller than the wafers available on the market (e.g., EN6337QI). Please refer to Fig. 2, which is a cross-sectional view showing the structure of a packaged power supply integrated circuit in accordance with the second embodiment of the new disk. In the package power supply integrated circuit of the second embodiment, unlike the first embodiment, the power supply chip 130 is directly disposed on the multilayer inductor wafer 120, and the M416197 multilayer inductor wafer 120 is directly disposed on the printed circuit board 110. The multi-layer inductor chip 120 and the power chip 130, and the multi-layer inductor chip 120 and the power chip 130 are electrically connected to the printed circuit board 110 by using bonding wires to meet various circuit design requirements. Please refer to Fig. 3, which is a cross-sectional view showing the structure of a package power supply integrated circuit in accordance with a third embodiment of the present invention. In the package power supply integrated circuit of the third embodiment, unlike the first embodiment, the multilayer inductor wafer 120 is directly disposed on the power source wafer 130, and the φ power source wafer 130 is directly disposed on the printed circuit board 110. The multilayer inductor chip 120 and the power chip 130 are electrically connected to the printed circuit board 110 by a bonding wire to meet the requirements of various circuit designs. Of course, another embodiment is conceivable for changing the power supply chip 130 disposed directly on the printed circuit board 110 to be electrically connected by using a conductive paste. Please refer to Figs. 4 and 5, which are cross-sectional views showing the structure of a package power supply integrated circuit in accordance with the fourth and fifth embodiments of the present invention. In the packaged power supply integrated circuit of the fourth embodiment and the fifth embodiment, unlike the first embodiment, the multilayer inductor wafer 120 and the power source wafer 130 are directly disposed on the printed circuit board 110 without overlapping. In the package power supply integrated circuit of the fourth embodiment, the multilayer inductor chip 120 and the printed circuit board 110 are electrically connected by a conductive paste, and the power source chip 130 and the printed circuit board 110 are electrically connected by the bonding wire 152. connection. Further, the multilayer inductor chip 120 and the power source chip 130 of the package power source integrated circuit of the fifth embodiment are electrically connected to the printed circuit board 110 by a bonding wire to meet various circuit design requirements. It is known that if the financial model is RGHS, and * can be reserved for the above, the printed circuit board can greatly improve the efficiency of the inductor, and the line can be improved. It can be used in conjunction with printed circuit boards, and because it can reduce the amount of gold used, it can effectively reduce the amount of metal materials used in the package, so it can effectively reduce the traditional use of printed windings to form a package. The process of the inductive effect, and the space configuration achieves the effect of being thin and light, and low cost. Although this new disk has been disclosed in the above manner, it is not limited to the new type, and anyone skilled in the art can not deviate from the spirit of the present invention. = Within the enclosure, when various changes and retouchings are available, the protection of this new model is subject to the definition of the patent application scope. [Simplified illustration]

At為讓本新型之上述和其他目的、特徵、優點與實施例 月匕更明顯易懂’所附圖式之說明如下： 第1A、1B圖分別繪示依照本新型第1實施例的一種 裝電源積體電路的結構示意圖與結構剖面圖。 第2圖係繪示依照本新型第2實施例的一種封裝電源 積體電路結構剖面圖。 第3圖係繪示依照本新型第3實施例的一種封裝電源 積體電路結構剖面圖。 第4圖係繪示依照本新型第4實施例的一種封裝電源 積體電路結構剖面圖 M416197 第5圖係繪示依照本新型第5實施例的一種封裝電源 積體電路結構剖面圖。 第6圖是先前技術中繞線電感與電源晶片共同封裝之 積體電路結構示意圖。 120 :多層電感晶片 151、153 :電路連接點 152 :焊線 154 :導電膏 【主要元件符號說明】 110 :印刷電路板 130 :電源晶片 φ H0 :電感晶片 150 :接合件 160 :繞線電感The above description of the above and other objects, features, advantages and embodiments of the present invention are made as follows. The description of the drawings is as follows: FIGS. 1A and 1B respectively illustrate a package according to the first embodiment of the present invention. A schematic structural view and a structural sectional view of a power integrated circuit. Fig. 2 is a cross-sectional view showing the structure of a package power supply integrated circuit in accordance with a second embodiment of the present invention. Figure 3 is a cross-sectional view showing the structure of a package power supply integrated circuit in accordance with a third embodiment of the present invention. 4 is a cross-sectional view showing a structure of a package power supply integrated circuit according to a fourth embodiment of the present invention. M416197 FIG. 5 is a cross-sectional view showing a structure of a package power supply integrated circuit according to a fifth embodiment of the present invention. Fig. 6 is a schematic view showing the structure of an integrated circuit in which the winding inductor and the power chip are co-packaged in the prior art. 120: Multi-layer inductor chip 151, 153: circuit connection point 152: bonding wire 154: conductive paste [Main component symbol description] 110: printed circuit board 130: power supply chip φ H0 : inductor wafer 150 : bonding member 160 : winding inductance

Claims (1)

M416197 六、申請專利範圍： 1. 一種封裝電源積體電路，包含： 一印刷電路板，包含複數個電路連接點； 一多層電感晶片，配置於該印刷電路板上方，且包含 一積層陶瓷電容器結構及一内部繞線，該内部繞線配置以 圍繞該積層陶瓷電容器結構； 一電源晶片，配置於該印刷電路板上方；以及 複數個接合件，用以將該多層電感晶片與該印刷電路 # 板之該電路連接點電性連接及將該電源晶片與該印刷電路 板之該電路連接點電性連接。 2. 如請求項1所述之封裝電源積體電路，其中該多 層電感晶片直接設置於該電源晶片之上’該電源晶片直接 設置於該印刷電路板之上。 3. 如請求項1所述之封裝電源積體電路，其中該電 源晶片直接設置於該多層電感晶片之上，該多層電感晶片 直接設置於該印刷電路板之上。 4. 如請求項1所述之封裝電源積體電路，其中該多 層電感晶片與該電源晶片以無重疊之方式直接設置於該印 刷電路板之上。 5. 如請求項1所述之封裝電源積體電路，其中該接 M416197 合件包含一焊線。 6. 如請求項1所述之封裝電源積體電路，其中該接 合件包含一導電貧。M416197 VI. Patent Application Range: 1. A package power integrated circuit comprising: a printed circuit board comprising a plurality of circuit connection points; a multilayer inductor chip disposed above the printed circuit board and comprising a multilayer ceramic capacitor a structure and an internal winding configured to surround the laminated ceramic capacitor structure; a power supply chip disposed over the printed circuit board; and a plurality of bonding members for the multilayered inductor wafer and the printed circuit The circuit connection point of the board is electrically connected and the power supply chip is electrically connected to the circuit connection point of the printed circuit board. 2. The package power integrated circuit of claim 1, wherein the multi-layer inductor chip is disposed directly on the power chip. The power chip is disposed directly on the printed circuit board. 3. The package power integrated circuit of claim 1, wherein the power supply chip is directly disposed on the multilayer inductor chip, and the multilayer inductor chip is directly disposed on the printed circuit board. 4. The package power integrated circuit of claim 1, wherein the multi-layer inductor chip and the power chip are disposed directly on the printed circuit board in a non-overlapping manner. 5. The package power integrated circuit of claim 1, wherein the connector M416197 includes a bonding wire. 6. The package power integrated circuit of claim 1, wherein the connector comprises a conductive poor.
TW100210836U 2011-06-15 2011-06-15 Packaged power integrated circuit TWM416197U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI578224B (en) * 2013-05-17 2017-04-11 緯創資通股份有限公司 File sharing circuit and computer using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI578224B (en) * 2013-05-17 2017-04-11 緯創資通股份有限公司 File sharing circuit and computer using the same
US9740273B2 (en) 2013-05-17 2017-08-22 Wistron Corporation File sharing circuit and computer using the same

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