M393041 五、新型說明： 【新型所屬之技術領域】 本創作是有關於一種主動元件陣列基板，且特別是有 關於一種具有窄邊框以及良好訊號傳輸品質的主動元件陣 列基板。 【先前技術】 圖1為習知一種主動元件陣列基板的上視示意圖。請 參照圖1，主動元件陣列基板100包括基板102以及設置 於基板102上的多條掃描線104以及與垂直於掃描線104 的多條資料線106。掃描線104與資料線1〇6交錯並定義 出主動區AA。每一條掃描線1〇6透過配線區WA中的一 條導線108與一驅動電路11〇相互連接，以接收來自驅動 電路110的掃描訊號。導線108的數目越多，則配線區 WA的寬度越大’意即主動元件陣列基板1〇〇的邊框越寬。 舉例來說’主動元件陣列基板1〇〇可採用寬視訊圖像 陣列（Wide Video Graphic Array，WVGA)標準的解析度 設計，亦即主動元件陣列基板100可達到的解析度為 480x800。一般來說，導線108會配置在主動元件陣二基 板100的兩側邊，亦即每一側邊會有400條的導線1〇8。 圖2A〜圖2C分別為一種圖1中配線區的局部剖面示 意圖。請參照圖2A，假設每一條導線108的線寬L為3 微米’兩相鄰導線108之間的間距d為3微米，則4〇〇條 導線108的總寬度約為2.4釐米。也就是說，主動元件$ M393041 列基板100的配線區WA寬度至少需要2.4釐米左右才足 夠。主動元件陣列基板100的主動區AA兩側的配線區 WA寬度合計至少需要預留4.8釐米的空間，以佈設導線 108與其他的線路。為了減少主動元件陣列基板1〇〇的邊 框免>度’圖2B所示的導線佈局方式係利用位於不同膜層 之導線108來進行訊號之傳遞。位於不同膜層中的導線 彼此交錯排列且分別受到保護層PI、P2之電性隔絕或保 護。圖2B.的導線佈局方式可使主動元件陣列基板1〇〇的 邊框寬度大約減少至1.2釐米。 然而’圖2B所示的導線佈局方式會使得主動元件陣 列基板100的配線區WA無法透光。由於目前的液晶顯示 面板大多是將液晶材料注入主動元件陣列基板與彩色漁光 基板之間’其後使用框膠貼合主動元件陣列基板與彩色減 光基板。特別是’一般會由主動元件陣列基板的背面照射 紫外光以使框膠硬化。因此，圖2B所示的導線佈局方式 勢必會受到目前的面板封裝製程所限制。 對此’在圖2C所示的導線佈局方式中，不同膜層的 導線108為彼此重疊，以使主動元件陣列基板10〇具有窄 邊框、且配線區WA仍具有適當的透光率。但是，在圖2c 所示的導線佈局方式中，彼此重疊的導線108容易發生輕 合效應(如圖2C中的區域C所示）而相互干擾，使得訊號的 傳輸品質不佳。 【新型内容】 5 及良元件陣列基板，可具有窄邊如 基板絲7敍，此杨树陣列 件陣列基板包括基板圍=線f，此主動元 動元件、多條第一走線IS線走多個主 _線以及多條資料線配= 遮蔽線。 ^中：多條掃描線與多條資料線交錯以定義出多 域。多個主動元件配置於基板上且位晝素區 主動7〇件電性連接於其中一條掃描以：二兰各 配置於基板上且位於主動區中：= 主魄木第二走線配置於基板上且由配線區延伸至 條遮蔽線配置重疊於第-走線。多 绦。式去3六 ，、他的輙捎線電性連接於第二走 #資料線電性連接於第—走線，且直他的 資料線電性連接於第—走線，且其他 3 =穴 料線電性連接於第二走線。 ，统、他的貧 本創作的主動元件陣列基板採用權疊式 方式’掃描線或資料線的訊號可經由的值 ==!、’因此本創作的主動元件陣列基板= 。尤^疋，不同獏層的走線之間還設置有遮蔽線作為 ㈣3041 =此以防止訊號之相互干擾’因此本創作的主動元件陣 列基板可具有良好的訊號傳輸品質。 為讓本鑛之上述特徵和優雜更明顯祕，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 第一實施例M393041 V. New description: [New technical field] This creation is related to an active device array substrate, and in particular to an active device array substrate having a narrow bezel and good signal transmission quality. [Prior Art] FIG. 1 is a schematic top view of a conventional active device array substrate. Referring to FIG. 1, the active device array substrate 100 includes a substrate 102 and a plurality of scan lines 104 disposed on the substrate 102 and a plurality of data lines 106 perpendicular to the scan lines 104. Scan line 104 is interleaved with data line 1 〇 6 and defines active area AA. Each of the scanning lines 1〇6 is connected to a driving circuit 11A through a wire 108 in the wiring area WA to receive a scanning signal from the driving circuit 110. The larger the number of the wires 108, the larger the width of the wiring area WA' means that the frame of the active device array substrate 1 is wider. For example, the active device array substrate 1 can adopt the resolution design of the Wide Video Graphic Array (WVGA) standard, that is, the resolution of the active device array substrate 100 can be 480×800. Generally, the wires 108 are disposed on both sides of the active matrix two substrate 100, that is, there are 400 wires 1〇8 on each side. 2A to 2C are respectively partial cross-sectional views of the wiring area of Fig. 1. Referring to Fig. 2A, assuming that the line width L of each of the wires 108 is 3 μm. The spacing d between two adjacent wires 108 is 3 μm, and the total width of the 4 wires 108 is about 2.4 cm. That is to say, the width of the wiring area WA of the active device $ M393041 column substrate 100 is at least about 2.4 cm. The wiring area WA width on both sides of the active area AA of the active device array substrate 100 needs to reserve at least 4.8 cm of space for routing the wires 108 and other lines. In order to reduce the edge of the active device array substrate 1 &> degree, the wire layout shown in Fig. 2B utilizes the wires 108 located at different film layers for signal transmission. The wires located in the different layers are staggered with each other and electrically isolated or protected by the protective layers PI, P2, respectively. The wire layout of Fig. 2B can reduce the frame width of the active device array substrate 1 to about 1.2 cm. However, the wire layout shown in Fig. 2B causes the wiring area WA of the active device array substrate 100 to be incapable of transmitting light. Since the current liquid crystal display panel mostly injects a liquid crystal material between an active device array substrate and a color fishing substrate, the active device array substrate and the color light-reducing substrate are bonded together using a sealant. In particular, ultraviolet light is generally irradiated from the back surface of the active device array substrate to harden the sealant. Therefore, the layout of the wires shown in Fig. 2B is bound to be limited by the current panel packaging process. In the wire layout shown in Fig. 2C, the wires 108 of the different film layers are overlapped with each other so that the active device array substrate 10 has a narrow bezel, and the wiring region WA still has an appropriate light transmittance. However, in the wire layout shown in Fig. 2c, the wires 108 which overlap each other are prone to the lightening effect (as shown by the area C in Fig. 2C) and interfere with each other, so that the transmission quality of the signal is not good. [New content] 5 and good component array substrate, can have a narrow side, such as the substrate wire 7, the poplar array device array substrate includes the substrate surrounding = line f, the active element moving component, a plurality of first routing IS line Multiple main _ lines and multiple data lines are equipped with = occlusion lines. ^ Medium: Multiple scan lines are interleaved with multiple data lines to define multiple domains. The plurality of active components are disposed on the substrate, and the active region of the pixel region is electrically connected to one of the scans: the two blues are disposed on the substrate and located in the active region: = the second trace of the main camphor is disposed on the substrate The upper and the wiring area extending to the strip shielding line are arranged to overlap the first-travel line. More 绦. Go to the 3-6, his squall line is electrically connected to the second walk # data line is electrically connected to the first line, and the data line straight to him is electrically connected to the first line, and the other 3 = points The material line is electrically connected to the second trace. The active component array substrate of the system is in a weighted manner. The value of the signal of the scan line or the data line can be passed through ==!, so the active device array substrate of the present invention =. In particular, shield lines are provided between the traces of different layers as (4) 3041 = This prevents signals from interfering with each other'. Therefore, the active array substrate of the present invention can have good signal transmission quality. In order to make the above features and advantages of the present mine more obvious, the following specific embodiments are described in detail below with reference to the accompanying drawings. Embodiments First Embodiment
、圖3為本創作第-實關之絲元件_基板的局部 上視不意圖。圖4為沿著圖3中A-A，、B-B，、C-C，線的剖 面示意圖。 3月參照圖3與圖4，主動元件陣列基板2〇〇具有主動 區AA以及位於主動區AA外圍的配線區WA。主動元件 陣列基板200包括基板202、多條掃描線21〇、多條資料線 220、多個主動元件230、多條第一走線240、多條第二走 線250以及多條遮蔽線260。多條掃描線21〇以及多條資 料線220配置於基板202上且位於主動區AA中，且多條 掃描線210與多條資料線220交錯以定義出多個晝素區域 PA。多個主動元件230配置於基板2Ό2上且位於多個晝素 區域PA中。在本實施例中，各主動元件23〇例如具有閘 極232、源極234與汲極236,其中閘極232電性連接於其 中一條掃描線210，且源極234電性連接於其中一條資料 線 220。Fig. 3 is a partial view of the substrate of the first real-acting wire element. Figure 4 is a cross-sectional view along line A-A, B-B, and C-C of Figure 3; Referring to Figures 3 and 4 in March, the active device array substrate 2 has an active area AA and a wiring area WA located at the periphery of the active area AA. The active device array substrate 200 includes a substrate 202, a plurality of scan lines 21A, a plurality of data lines 220, a plurality of active elements 230, a plurality of first traces 240, a plurality of second traces 250, and a plurality of mask lines 260. A plurality of scan lines 21A and a plurality of data lines 220 are disposed on the substrate 202 and located in the active area AA, and the plurality of scan lines 210 are interleaved with the plurality of data lines 220 to define a plurality of pixel regions PA. A plurality of active elements 230 are disposed on the substrate 2A and located in the plurality of halogen regions PA. In this embodiment, each active device 23 has, for example, a gate 232, a source 234, and a drain 236. The gate 232 is electrically connected to one of the scan lines 210, and the source 234 is electrically connected to one of the data. Line 220.
多條第一走線240以及多條第二走線250配置於基板 202上且由配線區WA延伸至主動區AA。位於配線區WA 令的夕條苐二走線250重疊於多條第— 所示。多條遮蔽線26〇 條 . 圖4 二走線弟—走線與多條第 第Ϊ 實施例中，遮蔽線26〇係用作第—、 Ϊ 250之間的屏蔽，使得不同膜層中的掃描訊 為了得到較佳的屏蔽效果，各遮蔽線2的 :以如可設計為大於或等於第一、第二走線24。、2:A plurality of first traces 240 and a plurality of second traces 250 are disposed on the substrate 202 and extend from the wiring area WA to the active area AA. The eve strips and two traces 250 located in the wiring area WA are superimposed on a plurality of sheets. A plurality of shielding lines 26 〇 .. Figure 4 走 弟 — 走 走 走 走 走 走 走 走 走 走 走 走 走 走 走 走 走 走 走 走 走 走 走 走 走 — — — — — — — — — — — — — Ϊ Ϊ In order to obtain a better shielding effect, the shielding lines 2 can be designed to be greater than or equal to the first and second routing lines 24. ,2:
掃線Μ""電性連接於第一走線⑽，且其他的 電性連接於第二走線25〇。在本實施例 =以奇數條(第i、3、5、7...2N+1條，N為 J ==性連接於對應的第—走線細，並以偶數= 於對岸的第U条’ N為正整數)的掃描、線210電性連接 於對應的弟—走線250。 f實施例的主動元件陣列基板2⑻更包括共用電極圖 jM，配置於基板2〇2上且位於主動區aa中，且 遮敝線260 t性連接於共用電極圖案⑽ 二第二走線勝250之間的遮蔽線260會具有：用兄電； 圖案CM之訊號，因此，即使第一走線240與第二走線25〇 重疊’第-走線24〇與第二走線MO所傳遞的掃描訊號也 ^彼此干擾。此外，本實施例的共用電極圖案CM例如 是環繞於每個晝素區域PA，以提高各晝素區域pA之開口 率。然而，本實施例的共用電極圖案CM僅為舉例說明， 本創作並不限制共用電極圖案CM的設置。 在主動元件陣列基板200中，第一走線240與共用電 M393041 極圖案CM為相同膜層，遮蔽線26〇與掃 膜層’且第二走線，與資料線，為相J層。 主動元件_基板更包括第—賴層m、閘絕緣層 GI、料體層S、第二保護層pv2以及多個晝素電極^ 第一保護層pvi覆蓋共用電極圖案CM以及多條第一 走線240，且掃描線210以及各主動元件23〇的閘極232 配置於第-保護層PV1上。_緣層GI覆蓋多條掃描線 210與各絲元件23G的閘極232。半導體層s設置於閘 極232上方的閘絕緣層GI上，且源極234與汲極2如設 置於半導體層S的兩側。 .第二保護層PV2覆蓋資料線220、各主動元件23〇的 源極234與汲極236，其中各汲極236上方的第二保護層 PV2中具有接觸窗開口 w。多個晝素電極四設置於多^ 晝素區域PA中，且各晝素電極把是藉由接觸窗開口 w 與對應的其中一個汲極236電性連接。 主動元件陣列基板200更包括多個第—開口 H1、多 個第二開口 H2、多個第三開口 H3、多個第一導電圖案cpi 以及多個第二導電圖案CP2。多個第一開口 H1配置於多 條知插線210上方的閘絕緣層GI與第二保護層pv2中， 以曝露掃描線210。多個第二開口 H2配置於多條第一走線 240上方的第一保護層PV卜閘絕緣層GI以及第二保護層 PV2中，以曝露第一走線240。多個第三開口 H3配置於多 條第二走線250上方的第二保護層pv2中，以曝露第二走 線 250 〇 ° 9 M393041 多個第一導電酸CP1以及多個第二導電圖案 配置於第一保護層PV2上。在本實施例中，第一導電 CP1、第二導電圖案CP2與晝素電極pE例如是相腹 層。詳言之，多個第一導電圖案cpi分別填入其中一、 二開口 H2以及對應的第一開口 H1(位於奇數條的= 21〇上方）’以電性連接第—走線施與奇數條的掃^ 211。一另一方面，多個第二導電圖案cp2分別填入其;1 個第三開口 H3以及對應的第一開口 m(位於偶數條 上方）’以電性連接第二走線250與偶數條的掃描 由上述可知，本實施例的主動元件陣列基板2㈧ 位於不同膜射的第一、第二走線24〇、25〇傳遞掃描訊 唬由^第一、第二走線240、250彼此重疊，使得配線區 =的寬度得以縮減，因此主動元件陣列基板2〇〇可達到 窄邊框的效果。再者，由於第一走線240或第二走線25〇 =間具有適當間隙d，意即配線區WA可維持適當的透光 率，因此主動元件陣列基板2〇〇不會有習知技術中無法使 框膠繪示)硬化的問題。此外，第一、第二走線240、250 之間還設置有遮蔽線26G以作為訊號屏蔽，因此主動元件 陣列基板200可具有良好的訊號傳輸品質。 第^實施例 、圖I為本創作第二實施例之主動元件陣列基板的局部 上視不意圖。圖6為沿著圖5中D-D，、e_E，線的剖面示意 M393041 圖。 凊參照圖5與圖6，主動元件陣列基板3〇〇與上述第 一實施例的主動元件陣列基板200類似，其中相同的構件 以相同的標號表示’以下不再贅述。主動元件陣列基板獅 與主動元件P㈣基板駐要差異在於，絲元件陣列 基板300是利用位於不同膜層的第一、第二走線24〇、 來進行資料線220的導線佈局。 在苐二實施例中，部份資料線22〇電性連接於第一走 線240 且其他的資料線220電性連接於第二走線250。更 確切而言，本實施例例如是以奇數條（第卜3、5、7 條’ N為正整數)的資料線22〇電性連接於 二 並以偶數條(第2、4、6、8.，條，二^^^^ 貝料線220電性連接於對應的第二走線250。 主動元件陣列基板300包括多個第一開口 η、多個 及多個導電圖㈣。多個第-開口 J1例如配 數條貝料線22〇上方的第二保護層ρν2中，以氓 i方料線跡多個第二開口 12配置於第一走線240 中2^護層PV1韻賴GI収第二保護層PV2 護層i42路}，走線240。多個導電圖案cp配置於第二保 口 U分㈣人射-個第二開 盘奇數對應的第—開口 ^電性連接第-走線240 敦條的貧料線220。 層中ΓΓ’ί述主動元件陣列基板3〇0 _立於不同膜 的弟一、弟二走線240、250進行資料線22〇之導線佈 M393041 】:第—、第二走線240、250之間設置有遮蔽線26〇做 屏蔽’使得資料線220所傳遞之訊號不會相互干擾，因此 =轉陣列基板30G可具有㈣框以騎好的訊號傳輸The wiper "" is electrically connected to the first trace (10), and the other is electrically connected to the second trace 25〇. In this embodiment = an odd number (i, 3, 5, 7...2N+1, N is J == sex is connected to the corresponding first - trace fine, and even number = the opposite U The scan of the strip 'N is a positive integer) and the line 210 are electrically connected to the corresponding brother-line 250. The active device array substrate 2 (8) of the f embodiment further includes a common electrode pattern jM disposed on the substrate 2〇2 and located in the active region aa, and the concealing line 260 is t-connected to the common electrode pattern (10). The shielding line 260 between the two has the signal of the pattern CM, so that even if the first line 240 overlaps with the second line 25, the first line 24 and the second line MO are transmitted. The scanning signals also interfere with each other. Further, the common electrode pattern CM of the present embodiment surrounds, for example, each of the halogen regions PA to increase the aperture ratio of each of the pixel regions pA. However, the common electrode pattern CM of the present embodiment is merely an example, and the present creation does not limit the arrangement of the common electrode pattern CM. In the active device array substrate 200, the first trace 240 and the common electrode M393041 polar pattern CM are the same film layer, and the shield line 26 and the scan layer 'and the second trace and the data line are the phase J layer. The active device_substrate further includes a first layer, a gate insulating layer GI, a material layer S, a second protective layer pv2, and a plurality of halogen electrodes. The first protective layer pvi covers the common electrode pattern CM and the plurality of first traces. 240, and the scan line 210 and the gate 232 of each active element 23A are disposed on the first protective layer PV1. The edge layer GI covers a plurality of scanning lines 210 and gates 232 of the respective wire elements 23G. The semiconductor layer s is disposed on the gate insulating layer GI over the gate 232, and the source 234 and the drain 2 are disposed on both sides of the semiconductor layer S. The second protective layer PV2 covers the data line 220, the source 234 of each active element 23A and the drain 236, wherein the second protective layer PV2 above each of the drains 236 has a contact opening w. A plurality of halogen electrodes are disposed in the plurality of halogen regions PA, and each of the pixel electrodes is electrically connected to the corresponding one of the drains 236 through the contact opening w. The active device array substrate 200 further includes a plurality of first openings H1, a plurality of second openings H2, a plurality of third openings H3, a plurality of first conductive patterns cpi, and a plurality of second conductive patterns CP2. The plurality of first openings H1 are disposed in the gate insulating layer GI and the second protective layer pv2 above the plurality of interposing lines 210 to expose the scanning lines 210. The plurality of second openings H2 are disposed in the first protective layer PV gate insulating layer GI and the second protective layer PV2 above the plurality of first traces 240 to expose the first trace 240. The plurality of third openings H3 are disposed in the second protective layer pv2 above the plurality of second traces 250 to expose the second traces 250 〇° 9 M393041, the plurality of first conductive acids CP1 and the plurality of second conductive pattern configurations On the first protective layer PV2. In the present embodiment, the first conductive CP1, the second conductive pattern CP2, and the halogen electrode pE are, for example, a belly layer. In detail, the plurality of first conductive patterns cpi are respectively filled in one of the two openings H2 and the corresponding first opening H1 (above the odd-numbered strips = 21〇)' to electrically connect the first-line to the odd-numbered strips Sweep ^ 211. On the other hand, a plurality of second conductive patterns cp2 are respectively filled in; a third opening H3 and a corresponding first opening m (above the even bars) are electrically connected to the second trace 250 and the even strips Scanning According to the above, the active device array substrate 2 of the present embodiment (8) is located at the first and second traces 24〇, 25〇 of the different film, and the scan signals are overlapped by the first and second traces 240 and 250. The width of the wiring area = is reduced, so that the active device array substrate 2 can achieve the effect of a narrow bezel. Moreover, since the first trace 240 or the second trace 25 〇= has an appropriate gap d, that is, the wiring area WA can maintain an appropriate light transmittance, the active device array substrate 2 does not have a conventional technique. The problem of hardening can not be made in the frame. In addition, a shielding line 26G is disposed between the first and second traces 240 and 250 as a signal shield, so that the active device array substrate 200 can have good signal transmission quality. The first embodiment and FIG. 1 are partial views of the active device array substrate of the second embodiment. Figure 6 is a cross-sectional view of the line D-D, e_E of Figure 5, M393041. Referring to Fig. 5 and Fig. 6, the active device array substrate 3 is similar to the active device array substrate 200 of the above-described first embodiment, wherein the same members are denoted by the same reference numerals and will not be described below. The difference between the active device array substrate lion and the active device P (four) substrate is that the wire element array substrate 300 uses the first and second traces 24〇 located on different film layers to perform the wire layout of the data line 220. In the second embodiment, a portion of the data line 22 is electrically connected to the first trace 240 and the other data lines 220 are electrically connected to the second trace 250. More specifically, in the present embodiment, for example, the data lines 22 of the odd-numbered strips (the third, fifth, and seventh 'N are positive integers) are electrically connected to the second and the even-numbered strips (the second, fourth, sixth, 8. The strip, the second ^^^^ the bead line 220 is electrically connected to the corresponding second trace 250. The active device array substrate 300 includes a plurality of first openings η, a plurality of and a plurality of conductive patterns (four). The first opening J1 is, for example, in the second protective layer ρν2 above the matching strip line 22〇, and the plurality of second openings 12 are arranged in the first trace 240 in the first trace 240. GI receives the second protective layer PV2 protective layer i42 way}, the trace 240. The plurality of conductive patterns cp are arranged in the second guarantee mouth U points (four) human shots - the second opening odd number corresponds to the first opening ^ electrical connection - Trace 240 to the poor material line 220 of the strip. Layer ΓΓ ' 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 主动 立 立 立 主动 立 立 立 立 立 立 立 立 立 立 立 立 立 立 立 主动 主动 主动 主动】: between the first and second traces 240, 250 are provided with shielding lines 26 to be shielded' so that the signals transmitted by the data lines 220 do not interfere with each other, so = the array substrate 30G can be (Iv) have good signal transmission blocks to ride
特f -提的是，軸第―實施例是彻第—走線⑽ 及弟—走線25G來進行掃描線210的導線佈局，以及第二 實^^用第-走線及第二走線25〇來進行資鄕 #的¥線料，然而，在其他實施射，也可以同時利 用弟-走線240及第二走線25〇來進行掃描線21〇及資 線220的導線佈力，也就是說，在其他實施例巾，部份 描線及部份·線祕連接於第―走線，且其他的掃描線 及其他的資料線電性連接於第二走線。 第三實施例Specifically, the first embodiment of the axis is the first-route (10) and the younger-line 25G for the wire layout of the scan line 210, and the second and the second and second traces. 25 〇 进行 鄕 鄕 的 的 的 的 的 的 的 ¥ , , , , , , , , 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 鄕 , , That is to say, in other embodiments, some of the lines and portions of the line are connected to the first line, and the other lines and other lines are electrically connected to the second line. Third embodiment
圖7為本創作第三實施例之主動元件陣列基板的局部 上視示意圖。圖8為沿著圖7中F_F，、G_G，、H_H,線的剖 面示意圖。 凊參照圖7與圖8，主動元件陣列基板4〇〇與上述實 施例的主動元件陣列基板2〇〇、3〇〇類似，其中相同的構件 以相同的標號表示，以下不再贅述。主動元件陣列基板4〇〇 與主動元件陣列基板2〇〇、3〇〇的主要差異在於，在主動元 件陣列基板400中，共用電極圖案CM與苐一保護層ρνι 例如疋依序设置於第二保護層pV2上。也就是說，本實施 例的共用電極圖案CM例如是位於掃描線21〇與資料線 12 M393041 220之上。此外’本實施例例如是在及極236上方的第二 保護層PV2與第一保護層pvi中形成接觸窗開口 w，以 曝露出汲極236。 要庄思的疋’在主動元件陣列基板400中，第一走線 240與掃描線21〇為相同膜層，遮蔽線26〇與資料線 為相同膜層，且第二走線250與共用電極圖案CM為相同 膜層。Fig. 7 is a partial top plan view showing the active device array substrate of the third embodiment of the present invention. Fig. 8 is a cross-sectional view showing the line along F_F, G_G, and H_H in Fig. 7. Referring to Fig. 7 and Fig. 8, the active device array substrate 4 is similar to the active device array substrate 2A, 3A of the above-described embodiment, wherein the same components are denoted by the same reference numerals and will not be described below. The main difference between the active device array substrate 4 and the active device array substrate 2〇〇, 3〇〇 is that in the active device array substrate 400, the common electrode pattern CM and the first protective layer ρνι are sequentially disposed in the second Protective layer pV2. That is, the common electrode pattern CM of the present embodiment is, for example, located above the scanning line 21A and the data line 12 M393041 220. Further, the present embodiment, for example, forms a contact opening w in the second protective layer PV2 over the gate 236 and the first protective layer pvi to expose the drain 236. In the active device array substrate 400, the first trace 240 and the scan line 21 are the same film layer, the shield line 26 is the same film layer as the data line, and the second trace 250 and the common electrode The pattern CM is the same film layer.
^主動元件陣列墓板400具有多個第一開口.K1、多個 第二開口 K2以及多個導電圖案CP。多個第一開口幻例 如配置於偶數條掃描線21〇上方的閘絕緣層GI、第二保護 層PV2以及第一保護層PV1中’以曝露偶數條的掃描線 21〇。多個第二開口 K2例如配置於第二走線250上方的第 —保護層PV1中’以曝露第二走線25〇。此外，多個 ，案CP配置於第一保護層PV1上，其中多個導電圖案邙 分，填入其中一個第二開口 K2以及對應的第一開口 κ卜 '黾〖生連接苐一走線250與偶數條的掃描線21〇。 雖然主動元件陣列基板400與上述第一、第二實1 =主動元件陣列基板200、3〇〇具有不同的膜層堆疊二你 =主動元件陣列基板4〇〇仍可透過類似的線路佈^ _ 線的訊號傳遞’進而得到窄邊框以及良； 第四實施例 圖9為本創作第二實施例之主動元件陣列基板的局部 13 M393041 上視示意圖。圖10為沿著圖9中H-H，、1-1，、J-J，線的剖 面示意圖。 凊參照圖9與圖10’主動元件陣列基板5〇〇與上述第 一 κ加例的主動元件陣列基板4〇〇類似，其中相同的構件 以相同的標號表示，以下不再贅述。主動元件陣列基板5〇〇 與主動元件陣列基板彻的主要差異在於，主動元件陣列 基板500是利用位於不同膜層的第—、第二走線24〇、25〇 來進行資料線220的導線佈局。 主動元件陣列基板包括多個第-開π L1、多個第 口 5、'多個第二開口 L3、多個第-導電圖案CP1以 圖案CP2。多個第—開口u配置於資料 線220上方的弟二保護層PV2與第一保護層州中，以 :^二。多個第二開°L2配置於第-走線上 Π;二第二保護層％以及第-保護層PV1 個第三開口L3配置於第二走 層PV1中，以曝露第二走線㈣。 此外，本貫施例的多個第—導電圖案c 二導電圖#CP2例如是配置於第鄉.及夕個弟 個第-導電_分別填4中==上Μ 對應的第-開π L1(位於奇數條的^ ^^2以^ 性連接第-走線240與奇數條的資料線22〇 ^古以电 多個第二導電圖案CP2分別填入发、， 方面’ (位於偶數條的資料線上方），以 電! 生連接第-走線25〇與偶數條的資料線22〇。上方）乂 14 M393041 特^提的是’雖'然第三實施例是利用第-走線240 及第二走線250來進行掃描線，的導線佈局，以及第四 2實 ==Γ走線240及第二走線250來進行資料線 然而’在其他實施例中，也可以同時利 線240及第二走線250來進行掃描線210及資料 線220的導線佈局，也就是說，在其他實施例中，部份掃 線電性連接於第一走線，且其他的掃描線 及其他的肓料線電性連接於第二走線。 综上所述，本創作的主動元件陣列基板透過不同膜層 中的走線進行掃插線或資料線的訊號傳輸，不同膜層中二 走線彼此重疊以減少配線區的寬度，因此本創作的主動元 1牛陣列基板可具有窄邊框。由於配線區可維持適當的透光 率丄因此本創作的主動元件陣列基板不會受到現有的框膠 貼合方式所限制。此外，由於不同膜層的走線之間還設置 有遮蔽線作為屏蔽，訊號不會相互干擾，因此本創作的主 動70件陣列基板可具有良好的訊號傳輸品質。 雖然本創作已以實施例揭露如上，然其並非用以限定 本創作’任何所屬技術領域中具有通常知識者，在不脫2 本創作之精神和範圍内’當可作些許之更動與潤飾，故本 創作之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為習知一種主動元件陣列基板的上視示意圖。 ^圖2Α〜圖2C分別為一種圖1中配線區的局部剖面示 思*圖。 15 M393041 圖3為本創作第一實施例之主動元件陣列基板的局部 上視示意圖。 圖4為沿著圖3中人-人’44’、(：-(：，線的剖面示意圖。 圖5為本創作第二實施例之主動元件陣列基板的局部 上視示意圖。 圖6為沿著圖5中D-D’、E-E’線的剖面示意圖。 圖7為本創作第三實施例之主動元件陣列基板的局部 上視示意圖。 圖8為沿著圖7中F-F’、G-G’線的剖面示意圖。 圖9為本創作第四實施例之主動元件陣列基板的局部 上視不意圖。 圖10為沿著圖9中H-H’、I-I’、J-J’線的剖面示意圖。 【主要元件符號說明】 100、200、300、400、500 :主動元件陣列基板 102 ' 202 :基板 104、210 :掃描線 106、220 :資料線 108 :導線 110 :驅動電路 230 :主動元件 232 :閘極 234 :源極 236 :汲極 240 :第一走線 16 M393041 250 :第二走線 260 :遮蔽線 A A .主動區 A-A，、B-B，、C-C，、D-D，、E-E，、F-F，、G-G，、H-H，、 Ι-Γ、J-Γ、K-K，：線 C :區域 CM :共用電極圖案 CP :導電圖案 CP1 :第一導電圖案 CP2 :第二導電圖案 d :間距 GI :閘絕緣層 HI、Jl、Kl、L1 :第一開口 H2、J2、K2、L2 :第二開口 H3、L3 :第三開口 L :線寬 PI、P2 :保護層 PA :晝素區域 PE :晝素電極 PV1 :第一保護層 PV2 :第二保護層 S:半導體層 W:接觸窗開口 WA :配線區 17The active element array tomb 400 has a plurality of first openings .K1, a plurality of second openings K2, and a plurality of conductive patterns CP. The plurality of first opening phantoms are disposed in the gate insulating layer GI, the second protective layer PV2, and the first protective layer PV1 above the even-numbered scanning lines 21A to expose the even-numbered scanning lines 21A. The plurality of second openings K2 are disposed, for example, in the first protective layer PV1 above the second traces 250 to expose the second traces 25A. In addition, a plurality of cases CP are disposed on the first protection layer PV1, wherein the plurality of conductive patterns are divided into two, and one of the second openings K2 and the corresponding first opening κ 黾 生 苐 苐 250 走 250 250 250 With an even number of scan lines 21〇. Although the active device array substrate 400 and the first and second real 1 = active device array substrates 200, 3 have different film layer stacks, you can use a similar circuit pattern. The signal transmission of the line is further obtained as a narrow frame and a good; Fourth Embodiment FIG. 9 is a top view of a portion 13 M393041 of the active device array substrate of the second embodiment of the present invention. Figure 10 is a cross-sectional view taken along line H-H, 1-1, and J-J of Figure 9; Referring to Fig. 9 and Fig. 10', the active device array substrate 5 is similar to the above-described first κ plus active device array substrate 4, wherein the same components are denoted by the same reference numerals and will not be described below. The main difference between the active device array substrate 5 and the active device array substrate is that the active device array substrate 500 uses the first and second traces 24〇, 25〇 located in different film layers to perform the wire layout of the data line 220. . The active device array substrate includes a plurality of first-open π L1, a plurality of first openings 5, 'a plurality of second openings L3, and a plurality of first conductive patterns CP1 in a pattern CP2. The plurality of first openings u are disposed in the second protective layer PV2 above the data line 220 and the first protective layer state, and are: The plurality of second openings L2 are disposed on the first-line Π; the second second protective layer % and the first protective layer PV1 third openings L3 are disposed in the second routing layer PV1 to expose the second trace (four). In addition, the plurality of first conductive patterns c of the present embodiment, the second conductive pattern #CP2, are, for example, disposed in the first town and the first one of the first conductive-conducting _ respectively filled with 4 == upper 对应 corresponding to the first open π L1 (^^^2 located in the odd-numbered strips connects the first-traffic line 240 with the odd-numbered data lines 22〇^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Above the data line, the electricity is connected to the second-line 25〇 and the even-numbered data line 22〇. Above) 乂14 M393041 Special mention is 'though' the third embodiment is to use the first-line 240 And the second trace 250 to perform the scan line, the wire layout, and the fourth 2 == Γ trace 240 and the second trace 250 to perform the data line. However, in other embodiments, the line 240 can also be used at the same time. And the second trace 250 is used to perform the wire layout of the scan line 210 and the data line 220. That is to say, in other embodiments, some of the scan lines are electrically connected to the first trace, and other scan lines and other The feed line is electrically connected to the second trace. In summary, the active device array substrate of the present invention transmits the signal of the sweeping line or the data line through the traces in different layers, and the two traces in different layers overlap each other to reduce the width of the wiring area, so the creation The active element 1 cow array substrate can have a narrow bezel. Since the wiring area can maintain an appropriate light transmittance, the active device array substrate of the present invention is not limited by the existing frame bonding method. In addition, since the shield lines are provided as shields between the traces of different layers, the signals do not interfere with each other. Therefore, the active 70-piece array substrate of the present invention can have good signal transmission quality. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention to anyone having ordinary knowledge in the technical field, and may make some changes and refinements within the spirit and scope of the present invention. Therefore, the scope of protection of this creation is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top plan view of a conventional active device array substrate. Figure 2A to Figure 2C are partial cross-sectional views of the wiring area of Figure 1, respectively. 15 M393041 FIG. 3 is a partial top plan view of the active device array substrate of the first embodiment of the present invention. 4 is a cross-sectional view of the human-human '44', (:-(:, line) of FIG. 3. FIG. 5 is a partial top view of the active device array substrate of the second embodiment of the present invention. FIG. Figure 7 is a schematic cross-sectional view of the active element array substrate of the third embodiment of the present invention. Figure 8 is a cross-sectional view along the line F-F' of Figure 7. FIG. 9 is a partial top view of the active device array substrate according to the fourth embodiment of the present invention. FIG. 10 is a cross-sectional view taken along line H-H', I-I', and J of FIG. Schematic diagram of the -J' line. [Main component symbol description] 100, 200, 300, 400, 500: Active device array substrate 102' 202: Substrate 104, 210: Scanning lines 106, 220: Data line 108: Conductor 110: Drive circuit 230: active element 232: gate 234: source 236: drain 240: first trace 16 M393041 250: second trace 260: shield line AA. active area AA, BB, CC, DD , EE, FF, GG, HH, Ι-Γ, J-Γ, KK, line C: region CM: common electrode pattern CP: conductive pattern CP1: first conductive Pattern CP2: second conductive pattern d: pitch GI: gate insulating layer HI, J1, K1, L1: first opening H2, J2, K2, L2: second opening H3, L3: third opening L: line width PI, P2: protective layer PA: halogen region PE: halogen electrode PV1: first protective layer PV2: second protective layer S: semiconductor layer W: contact window opening WA: wiring area 17