M379076 五、新型說明： , 【新型所屬之技術領域】 本創作是有關於一種電子元件陣列基板，且特別是有 關於一種能應用於顯示面板的主動元件陣列基板。 【先前技術】 ’ 目前常見的液晶顯示器大多為薄膜電晶體液晶顯示器 - (Thin Film Transistor Liquid Crystal Display, TFT-LCD ) > • 其主要元件包括薄膜電晶體陣列基板、彩色濾光基板（color filter substrate )、位在薄膜電晶體陣列基板與彩色濾光基板 之間的液晶層以及背光模組（backlight module )。 承上述’薄膜電晶體陣列基板是利用電場來改變液晶 層内的液晶分子排列，以控制背光模組所發出的光線對彩 色濾光基板的穿透，進而讓薄膜電晶體液晶顯示器顯示影 _ 像。因此’薄膜電晶體陣列基板乃是薄膜電晶體液晶顯示 器的重要元件。 圖1.是習知一種薄.膜電晶體陣列基板的俯視示意圖。 請參閱圖1 ’習知的薄膜電晶體陣列基板100包括一基板 110以及一晝素陣列120。基板110具有一顯示區112與一 位於顯示區112旁的非顯示區114,而晝素陣列120包括多 條掃描線122、多條資料線124以及一畫素群126。 詳細而言’掃描線122、資料線124與畫素群126皆 3 M379076 配置於顯示區112内，而這些掃描線122更從顯示區112 延伸至非顯示區114内。這些掃描線122都是由同一層膜 層所形成，因此這些掃描線122實質上是處於基板110的 同一平面上。 晝素群126包括多個晝素單元（pixel unit，圖1未續· . 示），而各個晝素單元包括一薄膜電晶體（圖1未繪示）與 一晝素電極（pixel electrode，圖1未緣示）。這些掃描線 φ 122與這些資料線124皆電性連接薄膜電晶體。控制晶片 (圖1未繪示）裝設於非顯示區114内，並透過位於這些 掃描線122，得以控制晝素群126的這些晝素單元，使得 薄膜電晶體液晶顯示器可以顯示影像。 【新型内容】 本創作提供一種主動元件陣列基板，其能應用於液晶顯 示技術。 # 本創作提出一種主動元件陣列基板，包括一基板、多 條第一配線、多條第二配線、多條第三配線、一晝素陣列、 一第一絕緣層以及一第二絕緣層。基板具有一顯示區與一 位於顯示區旁的非顯示區。這些第一配線、第二配線與第 三配線皆配置於非顯示區内。這些第二配線位於這些第一 配線的上方，而這些第三配線位於這些第二配線的上方。 晝素陣列配置於顯示區内，並電性連接這些第一配線、這 .些第二配線以及這些第三配線。第一絕緣層覆蓋這些第一 4 M379076 配線，並位於這些第一配線與這些第二配線之間。第二絕 緣層覆蓋這些第二配線與第一絕緣層，並位於這些第二配 線與這些第三配線之間。 在本創作一實施例中，這些第一配線與這些第三配線 部分重疊。 在本創作一實施例中，上述第一配線、第二配線以及 第三配線三者其中之一的形狀為折線形狀。 在本創作一實施例中，這些第一配線與這些第二配線 皆為金屬線。 在本創作一實施例中，這些第三配線皆為金屬線。 在本創作一實施例中，這些第三配線皆為透明導電線。 在本創作一實施例中，上述第一絕緣層為閘極絕緣層 (Gate Insulation layer，GI layer)。 在本創作一實施例中，上述第二絕緣層為平坦層 (passivation layer) ° 在本創作一實施例中，上述第二絕緣層的厚度可大於 第一絕緣層的厚度。 在本創作一實施例中，上述晝素陣列包括多條掃描 線、多條資料線以及多個晝素單元。這些掃描線.、這些資 料線與這些晝素單元皆配置於顯示區内，而這些畫素單元 配置於顯示區内，並電性連接這些掃描線與這些資料線。 在本創作一實施例中，這些掃描線電性連接這些第一 配線、這些第二配線以及這些第三配線。 5 M379076 在本創作一實施例中，上述主動元件陣列基板更包括 '多個第一導電柱以及多個第二導電柱。這些第一導電柱配 置於第一絕緣層中與第二絕緣層中，而各個第一導電柱連 接於其中一條第三配線與其中一條掃描線之間。這些第二 導電柱配置於第一絕緣層中，而各個第二導電柱連接於其 中一條第二配線與其中一條掃描線之間。 ' 在本創作一實施例中，這些資料線電性連接這些第一 • 配線、這些第二配線以及這些第三配線。 鲁 在本創作一實施例中，上述主動元件陣列基板，更包 括多個第一導電柱以及多個第二導電柱。這些第一導電柱 配置於第二絕緣層中，而各個第一導電柱連接於其中一條 第三配線與其中一條資料線之間。這些第二導電柱配置於 第一絕緣層中，而各個第二導電柱連接於其中一條第一配 線與其中一條資料線之間。 基於上述，因為第一配線、第二配線以及第三配線電 φ 性連接掃描線或資料線，所以裝設於非顯示區内的控制晶 - 片能透過第一配線、第二配線以及第三配線，來控制晝素 陣列的這些畫素單元，讓液晶顯示器得以顯示影像。如此， 本創作的主動元件陣列基板能應用於液晶顯示技術。 為讓本創作之上述特徵能更明顯易懂，下文特舉實施 例，並配合所附圖式，作詳細說明如下。 MJ/9076 【實施方式】 圖2A是本創作第一實施例之主動元件陣列基板的俯視 圖。請參閱圖2A，主動元件陣列基板200包括一基板210、 旦素陣列220、多條第一配線230a、多條第二配線230b 、及夕條第二配線23〇c，其中基板21〇具有一顯示區 與一非顯示區214，而非顯示區214位於顯示區212旁。 比這二第一配線23〇a、第二配線230b與第三配線230c 白配置於非顯示區214 A，而晝素陣列220配置於顯示區 =内’並電性連接這些第-配線2施、第二配線通以 一弟二配線23GC。第—配線23Ga、第二配線230b以及第 二：230:三者其中之一的形狀可以是折線形狀，例如圖 木的第二配線230c，其形狀為折線形狀。 狀或在其他未㈣的實施例中，第—配線2施的形 線形狀可=是折線形狀；或者，第一配 、, 一配線230b以及第二配線230c其中任二老的 形狀為折線形狀；或是，第一配線23Ga、第、一 〇 Vi u ^ 乐一配線 230b 三者的形狀皆為折線形狀。因此，圖 斤”的卓一配線230a、第二配線23%鱼 三者^形狀僅為舉例說明，並非限定本_。—配線織 至素陣列220包括多條掃描線222 以及多個書音罝 夕條貝枓線224 一 〜素早兀226,而迫些知描線222、 及廷些晝素單元220皆配置顯示區212内，甘、二 早το 226電性連接這些 這 些晝素 些貪料線224。 /yu/o 圖是圖2A中線M的剖面示意圖。請參閱圖2八與 θ ’各個晝素單元226包括一電晶體226a以及一電性 連接電晶體226a的晝素電極226b，而主動元件陣列基板 2〇〇更可以包括一第一絕緣層202以及一第二絕緣層2〇4。 承上述’各個電晶體226a可以是薄膜電晶體，並可包 括源極（source) S、一沒極（drain) D、一閘極（gate) G以及一通道層（ channel layer) C ’而晝素電極226b可為 透明導電層，其材料例如是銦錫氧化物（IndiumTin〇xide， ιτο)或銦鋅氧化物（IndiumZinc〇xide IZ〇)〇 閘極G配置於基板21〇上，並連接掃描線222，其中 這一閘極G與這些掃描線222可以是由同一層膜層所形 成而閘極G以及其所連接的掃描線222二者可以是一體 成型。第一絕緣層202覆蓋閘極G與基板210,並且可以 是由二氧切等絕緣材料所製成，而第-絕緣層2〇2可為 閘極絕緣層。 ' 通道層C配置於第一絕緣層2〇2上，並位於閘極g上 方，所以第一絕緣層202配置在閘極〇與通道層c之間， 讓閘極G不會直減通道層c電料通。源極s㈤及❹ 皆配置於通道層C與第—絕緣層2Q2 i，其中源極s連接 貢料線224,而汲極D則連接晝素電極226]^此外，這些 源極S與這些#料線224皆可以是由同—層膜層所形成了 而源極s以及與其連接的資料線224二者可以是一體成型。 第二絕緣層204覆蓋源極S、汲極D、通道層c以及 M379076 第一絕緣層202，並且可以是由氮化矽或高分子化合物等 :絕緣材料所製成。當第二絕緣層204是由高分子化合物所 ， 製成時，第二絕緣層204可為一種平坦層，且第二絕緣層 204的厚度T2可大於第一絕緣層202的厚度T1。第二絕 緣層204具有一開口（via) V，而晝素電極226b配置於第 二絕緣層204上，其中晝素電極226b透過開口 V而電性 * 連接汲極D。 ' 承上述，閘極G、源極S與汲極D皆可以是金屬層， • 而通道層C可以是半導體層，其材料例如是多晶矽（poly silicon)或非晶石夕（amorphous silicon)。此外，在本實施 例中，電晶體226a可以更包括一歐姆接觸層（Ohm contact layer) Ο，其配置於源極S與通道層C之間，以及汲極D 與通道層C之間。 由於電晶體226a的閘極G連接掃描線222,源極S連 接資料線224,而汲極D連接晝素電極226b，因此掃描線 • 222能開啟或關閉電晶體226a，以控制資料線224輸出電 ' 壓給晝素電極226b。如此，液晶層内的液晶分子能被這些 畫素電極226b所驅動，進而讓液晶顯示器得以顯示影像。 圖2C是圖2A中線II-II的剖面示意圖。請參閱圖2A 與圖2C，這些掃描線222電性連接這些第一配線230a、第 二配線230b與第三配線230c。這些第一配線230a直接連 接一些掃描線222,且這些第一配線230a與這些掃描線222 二者可以是由同一層膜層所形成，其中第一配線230a以及 M379076 其所連接的掃描線222二者可以是一體成型（如圖2A所 示），且第一配線23Oa可以是金屬線。 • 在本實施例中，主動元件陣列基板200更包括多個第 一導電柱240a以及多個第二導電柱240b，而透過這些第 一導電柱240a與這些第二導電柱240b，掃描線222得以 電性連接第二配線230b與第三配線230c。 ' 詳細而言，這些第一導電柱240a配置於第一絕緣層 202中與第二絕緣層204中，而各個第一導電柱240a連接 • 於其中一條第三配線230c與其中一條掃描線222之間。如 此，第三配線230c得以電性連接掃描線222。這些第二導 電柱240b配置於第一絕緣層202中，而各個第二導電柱 240b連接於其中一條第二配線230b以及其中一條掃描線 222之間。如此，第二配線230b得以電性連接掃描線222。 圖2D是圖2A中線III-III的剖面不意圖。請參閱圖 2D，這些第一配線230a配置於基板210上，這些第二配線 φ 230b位於這些第一配線230a的上方，而這些第三配線230c • 位於這些第二配線230b的上方。也就是說，這些第二配線 230b位於這些第一配線230a與這些第三配線230c之間。 請參閱圖2B與圖2D，第一絕緣層202位於這些第一 配線230a與這些第二配線230b之間，且第一絕緣層202 .不僅覆蓋電晶體226a的閘極G與基板210，同時更覆蓋這 些第一配線230a。第二絕緣層204位於這些第二配線230b 與這些第三配線230c之間，而且第二絕緣層204不僅覆蓋 M379076M379076 V. New description: , [New technical field] This creation relates to an electronic component array substrate, and in particular to an active device array substrate which can be applied to a display panel. [Prior Art] 'The current common liquid crystal display is mostly Thin Film Transistor Liquid Crystal Display (TFT-LCD) > • Its main components include thin film transistor array substrate, color filter substrate (color filter) a substrate, a liquid crystal layer between the thin film transistor array substrate and the color filter substrate, and a backlight module. The above-mentioned thin film transistor array substrate uses an electric field to change the arrangement of liquid crystal molecules in the liquid crystal layer to control the penetration of the light emitted by the backlight module to the color filter substrate, thereby allowing the thin film transistor liquid crystal display to display an image. . Therefore, a thin film transistor array substrate is an important component of a thin film transistor liquid crystal display. Figure 1. is a top plan view of a conventional thin film transistor array substrate. Referring to FIG. 1 'the conventional thin film transistor array substrate 100 includes a substrate 110 and a halogen array 120. The substrate 110 has a display area 112 and a non-display area 114 located beside the display area 112, and the pixel array 120 includes a plurality of scan lines 122, a plurality of data lines 124, and a pixel group 126. In detail, the scan line 122, the data line 124, and the pixel group 126 are all disposed in the display area 112, and the scan lines 122 extend from the display area 112 to the non-display area 114. These scan lines 122 are all formed by the same film layer, and thus these scan lines 122 are substantially on the same plane of the substrate 110. The pixel group 126 includes a plurality of pixel units (not shown in FIG. 1), and each of the pixel units includes a thin film transistor (not shown in FIG. 1) and a pixel electrode (pixel electrode). 1 did not show). The scan lines φ 122 and the data lines 124 are electrically connected to the thin film transistors. Control wafers (not shown in FIG. 1) are disposed in the non-display area 114, and through these scan lines 122, the pixel units of the pixel group 126 are controlled so that the thin film transistor liquid crystal display can display images. [New Content] This creation provides an active device array substrate that can be applied to liquid crystal display technology. The present invention proposes an active device array substrate comprising a substrate, a plurality of first wires, a plurality of second wires, a plurality of third wires, a cell array, a first insulating layer and a second insulating layer. The substrate has a display area and a non-display area located adjacent to the display area. The first wiring, the second wiring, and the third wiring are disposed in the non-display area. These second wirings are located above these first wirings, and these third wirings are located above these second wirings. The halogen array is disposed in the display area, and electrically connects the first wirings, the second wirings, and the third wirings. A first insulating layer covers the first 4 M379076 wirings and is located between the first wirings and the second wirings. The second insulating layer covers the second wiring and the first insulating layer and is located between the second wiring and the third wiring. In an embodiment of the present creation, the first wirings overlap with the third wiring portions. In an embodiment of the present invention, one of the first wiring, the second wiring, and the third wiring has a shape of a broken line. In an embodiment of the present invention, the first wiring and the second wiring are both metal wires. In an embodiment of the present creation, the third wires are all metal wires. In an embodiment of the present invention, the third wires are all transparent conductive wires. In an embodiment of the present invention, the first insulating layer is a Gate Insulation Layer (GI layer). In an embodiment of the present invention, the second insulating layer is a passivation layer. In an embodiment of the present invention, the thickness of the second insulating layer may be greater than the thickness of the first insulating layer. In an embodiment of the present invention, the pixel array includes a plurality of scan lines, a plurality of data lines, and a plurality of pixel units. The scan lines, the data lines and the pixel units are disposed in the display area, and the pixel units are disposed in the display area and electrically connected to the scan lines and the data lines. In an embodiment of the present invention, the scan lines are electrically connected to the first wirings, the second wirings, and the third wirings. 5 M379076 In an embodiment of the present invention, the active device array substrate further includes 'a plurality of first conductive pillars and a plurality of second conductive pillars. The first conductive pillars are disposed in the first insulating layer and the second insulating layer, and each of the first conductive pillars is connected between one of the third wires and one of the scan lines. The second conductive pillars are disposed in the first insulating layer, and each of the second conductive pillars is connected between one of the second wires and one of the scan lines. In an embodiment of the present invention, the data lines are electrically connected to the first wiring, the second wiring, and the third wiring. In an embodiment of the present invention, the active device array substrate further includes a plurality of first conductive pillars and a plurality of second conductive pillars. The first conductive pillars are disposed in the second insulating layer, and each of the first conductive pillars is connected between one of the third wires and one of the data lines. The second conductive pillars are disposed in the first insulating layer, and each of the second conductive pillars is connected between one of the first wiring lines and one of the data lines. Based on the above, since the first wiring, the second wiring, and the third wiring are electrically connected to the scanning line or the data line, the control crystal chip mounted in the non-display area can pass through the first wiring, the second wiring, and the third. Wiring to control these pixel units of the pixel array, allowing the LCD display to display images. Thus, the active device array substrate of the present invention can be applied to liquid crystal display technology. In order to make the above-mentioned features of the present invention more comprehensible, the following specific embodiments are described below in conjunction with the accompanying drawings. MJ/9076 [Embodiment] Fig. 2A is a plan view of an active device array substrate of a first embodiment of the present invention. Referring to FIG. 2A, the active device array substrate 200 includes a substrate 210, a denier array 220, a plurality of first wirings 230a, a plurality of second wirings 230b, and a second wiring 23〇c, wherein the substrate 21 has a The display area is adjacent to a non-display area 214, and the non-display area 214 is located adjacent to the display area 212. The first wiring 23A, the second wiring 230b, and the third wiring 230c are disposed in the non-display area 214A, and the pixel array 220 is disposed in the display area=inside and electrically connected to the first wiring 2 The second wiring is connected to a second wiring 23GC. The first wiring 23Ga, the second wiring 230b, and the second: 230: one of the three shapes may be a polygonal line shape, for example, the second wiring 230c of the figure, and its shape is a polygonal line shape. Or in other embodiments, the shape line shape of the first wiring 2 may be a polygonal line shape; or, the first matching, the wiring 230b and the second wiring 230c are in the shape of a broken line; Alternatively, the shapes of the first wiring 23Ga, the first one, and the first Viu ^ wiring 230b are all in a polygonal line shape. Therefore, the shape of the wire 230a and the second wire 23% of the fish are only for illustrative purposes, and are not limited to the present invention. The wire-wound array 220 includes a plurality of scanning lines 222 and a plurality of book sounds.夕条贝枓线224 〜一素早兀226, and some of the known line 222, and some of the elements 220 are arranged in the display area 212, Gan, two early το 226 electrically connected these these greedy lines 224. /yu/o The figure is a schematic cross-sectional view of line M in Fig. 2A. Referring to Fig. 2 and θ', each pixel unit 226 includes a transistor 226a and a halogen electrode 226b electrically connected to the transistor 226a. The active device array substrate 2 may further include a first insulating layer 202 and a second insulating layer 2〇4. The above-mentioned respective transistors 226a may be thin film transistors, and may include a source S, a Drain D, a gate G and a channel layer C ' and the halogen electrode 226b may be a transparent conductive layer, such as indium tin oxide (IndiumTin〇xide, ιτο) Or indium zinc oxide (IndiumZinc〇xide IZ〇) 〇 gate G is configured in The board 21 is connected to the scan line 222, wherein the gate G and the scan lines 222 may be formed by the same film layer and the gate G and the scan line 222 to which they are connected may be integrally formed. The first insulating layer 202 covers the gate G and the substrate 210, and may be made of an insulating material such as dioxotomy, and the first insulating layer 2〇2 may be a gate insulating layer. 'The channel layer C is disposed at the first The insulating layer 2〇2 is located above the gate g, so the first insulating layer 202 is disposed between the gate electrode and the channel layer c, so that the gate G does not directly reduce the channel material c. The source s (five) And ❹ are disposed in the channel layer C and the first insulating layer 2Q2 i, wherein the source s is connected to the tributary wire 224, and the drain D is connected to the halogen electrode 226] ^ In addition, these source S and these #feed 224 Both of the source s and the data line 224 connected thereto may be integrally formed. The second insulating layer 204 covers the source S, the drain D, the channel layer c, and the M379076. An insulating layer 202, and may be made of tantalum nitride or a polymer compound or the like: an insulating material. When the second insulating layer 20 4 is made of a polymer compound, the second insulating layer 204 may be a flat layer, and the thickness T2 of the second insulating layer 204 may be greater than the thickness T1 of the first insulating layer 202. The second insulating layer 204 has a The via V is disposed on the second insulating layer 204, wherein the halogen electrode 226b is electrically connected to the drain D through the opening V. 'According to the above, the gate G, the source S and the gate The pole D may be a metal layer, and the channel layer C may be a semiconductor layer, the material of which is, for example, poly silicon or amorphous silicon. In addition, in this embodiment, the transistor 226a may further include an Ohm contact layer, which is disposed between the source S and the channel layer C, and between the drain D and the channel layer C. Since the gate G of the transistor 226a is connected to the scan line 222, the source S is connected to the data line 224, and the drain D is connected to the pixel electrode 226b, the scan line 222 can turn on or off the transistor 226a to control the output of the data line 224. The electric pressure is applied to the halogen electrode 226b. Thus, liquid crystal molecules in the liquid crystal layer can be driven by the pixel electrodes 226b, thereby allowing the liquid crystal display to display an image. 2C is a schematic cross-sectional view taken along line II-II of FIG. 2A. Referring to FIG. 2A and FIG. 2C, the scan lines 222 are electrically connected to the first wiring 230a, the second wiring 230b, and the third wiring 230c. The first wires 230a are directly connected to the scan lines 222, and the first wires 230a and the scan lines 222 may be formed by the same film layer, wherein the first wires 230a and M379076 are connected to the scan lines 222. The one may be integrally formed (as shown in FIG. 2A), and the first wiring 23Oa may be a metal wire. In this embodiment, the active device array substrate 200 further includes a plurality of first conductive pillars 240a and a plurality of second conductive pillars 240b. Through the first conductive pillars 240a and the second conductive pillars 240b, the scan lines 222 are The second wiring 230b and the third wiring 230c are electrically connected. In detail, the first conductive pillars 240a are disposed in the first insulating layer 202 and the second insulating layer 204, and each of the first conductive pillars 240a is connected to one of the third wirings 230c and one of the scanning lines 222. between. Thus, the third wiring 230c is electrically connected to the scanning line 222. The second conductive pillars 240b are disposed in the first insulating layer 202, and each of the second conductive pillars 240b is connected between one of the second wirings 230b and one of the scanning lines 222. As such, the second wiring 230b is electrically connected to the scan line 222. Fig. 2D is a cross-sectional view of line III-III in Fig. 2A. Referring to FIG. 2D, the first wirings 230a are disposed on the substrate 210, and the second wirings φ 230b are located above the first wirings 230a, and the third wirings 230c are located above the second wirings 230b. That is, these second wirings 230b are located between the first wirings 230a and the third wirings 230c. Referring to FIG. 2B and FIG. 2D, the first insulating layer 202 is located between the first wiring 230a and the second wiring 230b, and the first insulating layer 202 not only covers the gate G of the transistor 226a and the substrate 210, but also These first wirings 230a are covered. The second insulating layer 204 is located between the second wirings 230b and the third wirings 230c, and the second insulating layer 204 covers not only the M379076
第一絕緣層202與電晶體226a的源極s、沒極D C (如圖915 π-、 一通道層 1 _ 2Β所不），同時更覆蓋這些第二配線230b。 另外，第一配線230a與第二配線230b可以皆為 線而這些第二配線23〇b與資料、線224可以是由同^屬 層所形成，因此第二配線230b、汲極D與源極8三者二膜 以疋由同一層膜層所形成。 可The first insulating layer 202 and the source s of the transistor 226a, the pole D C (as shown in FIG. 915 π-, one channel layer 1 _ 2 )), cover the second wiring 230b at the same time. In addition, the first wiring 230a and the second wiring 230b may both be lines, and the second wiring 23〇b and the data and the line 224 may be formed by the same layer, and thus the second wiring 230b, the drain D and the source 8 three of the two films are formed by the same film layer. can
此第三配線挪皆配置於第二絕緣層204上，而這 一—己線230c與這些晝素電極226b可以是由同— 層:::成’其中晝素電極可以是由銦錫氧化物或銦: 私物所形成的透明導電層，因此這些第三配線23〇c可以 皆為透明導電線。 不過’在其他實施例中’這些第三配線23〇c也可以是 金屬線。也就是說，在本創作的所有實施例中，這些第三 、’Ί 3 〇c與這些晝素電極226b不一定是由同一層膜層所 形成’所以在此不限定第三配線23〇c為透明導電線。 睛參閱圖2A與圖2D，由於這些第三配線230c的形狀 白為折線形狀’因此這些第三配線23〇c可以被彎曲而分別 與這些第一配線230a部分重疊，如圖2A與圖2D所示。 這樣可以減少這些第一配線230a、第二配^線230b以及第 二配線230c三者在基板210上所佔據的面積，讓更多的線 路可以配置在基板210上。 圖3A是本創作第二實施例之主動元件陣列基板的俯 視圖’而圖3B是圖3A中線IV-IV的剖面示意圖。請參閱 11 M379076 圖3A與圖3B，本實施例的主動元件陣列基板300包括基 板210、畫素陣列220、多條第一配線330a、第二配線330b 以及第三配線330c ’其中主動元件陣列基板300與第一實 施例的主動元件陣列基板200二者結構相似，因此二者相 同的特徵不再重複贅述，以下僅介紹二者的差異。 主動元件陣列基板300與主動元件陣列基板2〇〇二者 的主要差異在於：晝素陣列220的這些資料線224電性連 接這些第一配線330a、第二配線330b以及第三配線330c， 其中這些第二配線330b直接連接一些資料線224，且這些 第二配線330b與這些資料線224二者可以是由同一層膜層 所形成，因此第二配線330b與其所連接的資料線224二者 可以是一體成型。 在本實施例中，主動元件陣列基板300更包括多個第 —導電柱340a、多個第二導電柱340b、第一絕緣層202以 及第二絕緣層204，而透過這些第一導電柱34〇a與第二導 電柱340b，資料線224得以電性連接第一配線33〇a與第 二配線330c。 具體而言’這些第一導電柱340a配置於第二絕緣層 204中，而各個第一導電柱340a連接於其中一條第三配線 330c與其中—條㈣線224之間。如此，第三配線遍 2以電性連接資料線224。這些第二導電柱34%配置於第 、、、巴緣層202中，而各個弟一導電柱340b連接於其中一條 第—配線330a與其中一條資料線224之間。如此，第一配 12 M379076 線330a亦能電性連接資料線224。 :綜上所述，由於第一配線、第二配線以及第三配線電 1 性連接掃描線或資料線，因此裝設於非顯示區内的控制晶 片能透過第一配線、第二配線以及第三配線，來控制晝素 陣列的這些晝素單元，讓液晶顯示器得以顯示影像。 其次，第一配線、第二配線以及第三配線其中至少一 ' 者的形狀可以是折線形狀，且這些第二配線位於這些第一 ' 配線與這些第三配線之間，因此第三配線能與第一配線部 _ 分重疊，進而減少這些第一配線、第二配線以及第三配線 三者在基板上所佔據的面積，讓更多的線路配置在基板 上，以提高主動元件陣列基板的線路密度。 值得一提的是，這些第三配線與這些第一配線之間配 置二層絕緣層（即第一絕緣層與第二絕緣層）而彼此分開， 加上第二絕緣層的厚度可大於第一絕緣層的厚度，因此本 創作能大幅拉開這些第三配線與這些第一配線之間的距 • 離，以降低因第三配線與第一配線部分重疊所產生的寄生 ' 電容對晝素陣列的影響，讓此寄生電容不會破壞液晶顯示 器的整體晝面品質。 雖然本創作以前述實施例揭露如上，然其並非用以限 定本創作，任何熟習相像技藝者，在不脫離本創作之精神 和範圍内，所作更動與潤飾之等效替換，仍為本創作之專 利保護範圍内。 13 M379076 【圖式簡單說明】 圖1 是習知一種薄膜電晶體陣列基板的俯視示意圖。 圖2A是本創作第一實施例之主動元件陣列基板的俯視圖。 圖2B是圖2A中線I-Ι的剖面示意圖。 圖2C是圖2A中線II-II的剖面示意圖。 圖2D是圖2A中線III-III的剖面示意圖。 圖3A是本創作第二實施例之主動元件陣列基板的俯視圖。 圖3B是圖3A中線IV-IV的剖面示意圖。 【主要元件符號說明】 100 薄膜電晶體陣列基板 110、210 基板 112 ' 212 转頁不區 114 、 214 非顯不區 120 ' 220 畫素陣列 122 ' 222 掃描線 124 、 224 資料線 126 晝素群 200 > 300 主動元件陣列基板 202 第一絕緣層 204 第二絕緣層 226 晝素單元 226a 電晶體 14 M379076The third wiring is disposed on the second insulating layer 204, and the line 230c and the halogen electrode 226b may be formed by the same layer:::', wherein the halogen electrode may be made of indium tin oxide Or indium: a transparent conductive layer formed by a private object, and therefore these third wires 23〇c may be transparent conductive wires. However, in other embodiments, these third wires 23〇c may also be metal wires. That is to say, in all embodiments of the present creation, these third, 'Ί 3 〇c and these halogen electrodes 226b are not necessarily formed by the same film layer', so the third wiring 23〇c is not limited herein. It is a transparent conductive wire. 2A and 2D, since the shape of the third wires 230c is white in a zigzag shape', these third wires 23〇c can be bent to partially overlap the first wires 230a, respectively, as shown in FIGS. 2A and 2D. Show. This can reduce the area occupied by the first wiring 230a, the second wiring 230b, and the second wiring 230c on the substrate 210, so that more wiring can be disposed on the substrate 210. Fig. 3A is a plan view of the active device array substrate of the second embodiment of the present invention, and Fig. 3B is a cross-sectional view taken along line IV-IV of Fig. 3A. Referring to FIG. 3A and FIG. 3B, the active device array substrate 300 of the present embodiment includes a substrate 210, a pixel array 220, a plurality of first wirings 330a, a second wiring 330b, and a third wiring 330c', wherein the active device array substrate The structure of the active device array substrate 200 of the first embodiment is similar to that of the active device array substrate 200 of the first embodiment, and therefore the same features will not be described again. Only the differences between the two will be described below. The main difference between the active device array substrate 300 and the active device array substrate 2 is that the data lines 224 of the pixel array 220 are electrically connected to the first wiring 330a, the second wiring 330b, and the third wiring 330c. The second wiring 330b is directly connected to some of the data lines 224, and the second wirings 330b and the data lines 224 may be formed by the same film layer. Therefore, the second wiring 330b and the data line 224 connected thereto may be One piece. In this embodiment, the active device array substrate 300 further includes a plurality of first conductive pillars 340a, a plurality of second conductive pillars 340b, a first insulating layer 202, and a second insulating layer 204, and through the first conductive pillars 34〇 a and the second conductive pillar 340b, the data line 224 is electrically connected to the first wiring 33a and the second wiring 330c. Specifically, these first conductive pillars 340a are disposed in the second insulating layer 204, and each of the first conductive pillars 340a is connected between one of the third wirings 330c and the middle (four) line 224 thereof. Thus, the third wiring is electrically connected to the data line 224. The second conductive pillars 34% are disposed in the first, and the margin layer 202, and each of the first conductive pillars 340b is connected between one of the first wirings 330a and one of the data lines 224. Thus, the first 12 M379076 line 330a can also be electrically connected to the data line 224. In summary, since the first wiring, the second wiring, and the third wiring are electrically connected to the scanning line or the data line, the control chip mounted in the non-display area can pass through the first wiring, the second wiring, and the first Three wires are used to control the pixel units of the pixel array to allow the liquid crystal display to display images. Secondly, at least one of the first wiring, the second wiring, and the third wiring may have a shape of a broken line, and the second wirings are located between the first 'wirings and the third wirings, so the third wiring can be The first wiring portion _ overlaps, thereby reducing the area occupied by the first wiring, the second wiring, and the third wiring on the substrate, and allowing more lines to be disposed on the substrate to improve the line of the active device array substrate. density. It is worth mentioning that the third wiring and the first wiring are disposed with two insulating layers (ie, the first insulating layer and the second insulating layer) and are separated from each other, and the thickness of the second insulating layer may be greater than the first The thickness of the insulating layer, so this creation can greatly open the distance between these third wirings and these first wirings to reduce the parasitic 'capacitance pair of halogen arrays caused by the overlap of the third wiring and the first wiring portion. The effect of this parasitic capacitance does not damage the overall quality of the LCD display. Although the present invention is disclosed above in the foregoing embodiments, it is not intended to limit the present invention. Any skilled person skilled in the art, without departing from the spirit and scope of the present invention, is equivalent to the replacement of the modifiers and retouchings. Within the scope of patent protection. 13 M379076 [Simplified Schematic] FIG. 1 is a schematic top view of a conventional thin film transistor array substrate. 2A is a plan view of the active device array substrate of the first embodiment of the present invention. Fig. 2B is a schematic cross-sectional view taken along line I-Ι of Fig. 2A. 2C is a schematic cross-sectional view taken along line II-II of FIG. 2A. Figure 2D is a schematic cross-sectional view taken along line III-III of Figure 2A. 3A is a top plan view of an active device array substrate of a second embodiment of the present invention. Figure 3B is a schematic cross-sectional view taken along line IV-IV of Figure 3A. [Major component symbol description] 100 Thin film transistor array substrate 110, 210 Substrate 112 '212 Rotation no area 114, 214 Non-display area 120 '220 pixel array 122 ' 222 Scan line 124, 224 Data line 126 Alizarin group 200 > 300 active device array substrate 202 first insulating layer 204 second insulating layer 226 halogen unit 226a transistor 14 M379076
226b226b
230a 、 330a 230b 、 330b 230c 、 330c 240a、340a 240b > 340b C D G O S230a, 330a 230b, 330b 230c, 330c 240a, 340a 240b > 340b C D G O S
ΤΙ、T2 V 晝素電極 第一配線 第二配線 第三配線 第一導電柱 第二導電柱 通道層 没極 閘極 歐姆接觸層 源極 厚度 開口 15ΤΙ, T2 V 昼 electrode First wiring Second wiring Third wiring First conductive column Second conductive column Channel layer No pole Gate ohmic contact layer Source Thickness Opening 15