M366088 四、指定代表圖： (一) 本案指定代表圖為：第三^ (二) 本代表圖之元件符號簡單說明： 30 畫素結構 3 2 掃描線 34 資料線 36 薄膜電晶體 361 閘極 3 6 2 源極 363 汲極 364穿孔 38畫素電極 五、新型說明： 【新型所屬之技術領域】 [0001] [0002] 本創作係有關於一種液晶顯示器，特別是指一種畫素 結構。 【先前技術] 由於畫素結構（Liquid Crystal Panel)與背光模 組（Back Light Module)之製作技術越來越成熟，因 此當液晶顯示器（Liquid Crystal Display，LCD) 不論在解析度、重量、厚度、反應速度以及耗電量等特 性上皆優於傳統之陰極射線管（Cathode Ray Tube， CRT)顯示器的時候，液晶顯示器已漸漸取代傳統之陰極 射線管顯示器，所以液晶顯示器是現今最為普遍的顯示 器之—。液晶顯示器之畫面包含有複數晝素（pixel)， 098208393 表單編號A0101 第2頁/共π頁 0982027206-0 M366088 每一畫素包含-定面積之液晶而用於顯示影像，以及利 用至少一薄膜電晶體（Thin-Film TransistQr，TFT) =以控制。由於液晶受到電場作用會偏轉而改變光線的 穿透率，所以液晶顯示器顯示影像時，會經由薄膜電晶 體之控制而施加電壓至畫素喊生電場於畫素區域内之 液晶’而控制晝素區域内之液晶的傾角，如此即可控制 光線對液晶的穿透率，亦即可控制畫素之亮度。 请參閱第一圖，其為習知畫素結構之示意圖。如圖所 不’習知晝素結構10包含一掃描線12、一資料線14、一M366088 IV. Designated representative diagram: (1) The representative representative figure of this case is: third ^ (2) The symbol of the representative figure is simple: 30 pixel structure 3 2 scan line 34 data line 36 thin film transistor 361 gate 3 6 2 Source 363 Bungee 364 perforation 38 pixel electrode 5. New description: [New technical field] [0001] [0002] This creation relates to a liquid crystal display, especially a pixel structure. [Prior Art] Since the production technology of the Liquid Crystal Panel and the Back Light Module is becoming more and more mature, when a liquid crystal display (LCD) is used in resolution, weight, thickness, When the reaction speed and power consumption are superior to those of conventional cathode ray tube (CRT) displays, liquid crystal displays have gradually replaced traditional cathode ray tube displays, so liquid crystal displays are the most common displays today. —. The screen of the liquid crystal display contains a plurality of pixels, 098208393 Form No. A0101 Page 2 / Total π page 0982027206-0 M366088 Each pixel contains a fixed area of liquid crystal for displaying images and using at least one thin film Crystal (Thin-Film Transist Qr, TFT) = controlled. Since the liquid crystal is deflected by the electric field to change the transmittance of the light, when the liquid crystal display displays an image, a voltage is applied to the liquid crystal in the pixel region by the control of the thin film transistor, and the pixel is controlled. The tilt angle of the liquid crystal in the area, so that the transmittance of light to the liquid crystal can be controlled, and the brightness of the pixel can be controlled. Please refer to the first figure, which is a schematic diagram of a conventional pixel structure. As shown in the figure, the conventional structure 10 includes a scan line 12, a data line 14, and a
薄膜電晶體16與-畫素電極18，其中薄膜電晶體16包含 一閘極161、一源極162與一汲極ι63，閘極161耦接掃描 線12，源極16 2耗接資料線14 ,閘極161上設置一半導體 層164，源極162與汲極163設置於半導體層164上，汲極 164經由一穿孔165耦接畫素電極18，一般而言，閘極 161與源極162會衍生寄生電容Cgs，閘極161與汲極163 會衍生寄生電容Cgd。然而，如第一A圖所示，畫素結構 10為未發生製程偏移的情況，所以寄生電容Cgs與寄生電 容Cgd未發生變化，若製程發生偏移而導致寄生電容Cgd 大幅增加，則輸入電壓會嚴重受到寄生電容Cgd影響，也 就是寄生電容Cgd所導致之電壓準位（Δν)導致輸入電 壓的變化量大。然而，寄生電容於半導體製程上是不可 避免，一般寄生電容會衍生在薄膜電晶體之周邊，例如： 薄膜電晶體之閘極（gate)與汲極（drain)之間的電 容Cgd，所以液晶顯示器於輸入電壓的運算上會考慮寄生 電容的影響，影響輸入電壓的電容耦合參數為（（Vgh- 098208393The thin film transistor 16 and the pixel electrode 18, wherein the thin film transistor 16 includes a gate 161, a source 162 and a drain ι 63, the gate 161 is coupled to the scan line 12, and the source 16 2 is connected to the data line 14. A semiconductor layer 164 is disposed on the gate 161. The source 162 and the drain 163 are disposed on the semiconductor layer 164. The drain 164 is coupled to the pixel electrode 18 via a via 165. Generally, the gate 161 and the source 162 are connected. The parasitic capacitance Cgs will be derived, and the gate 161 and the drain 163 will generate a parasitic capacitance Cgd. However, as shown in FIG. A, the pixel structure 10 is in a case where no process offset occurs, so the parasitic capacitance Cgs and the parasitic capacitance Cgd are not changed, and if the process is shifted and the parasitic capacitance Cgd is greatly increased, the input is performed. The voltage is heavily affected by the parasitic capacitance Cgd, which is the voltage level (Δν) caused by the parasitic capacitance Cgd, which causes a large amount of change in the input voltage. However, the parasitic capacitance is unavoidable in the semiconductor process. Generally, the parasitic capacitance is derived around the thin film transistor, for example: the capacitance Cgd between the gate and the drain of the thin film transistor, so the liquid crystal display The influence of parasitic capacitance is considered in the calculation of the input voltage, and the capacitive coupling parameter affecting the input voltage is ((Vgh- 098208393)
Vgl) xCgd) / (Cgd+Clc+Cst) 表單編號A0101 第3頁/共17頁 ，其中Vgh與Vgl為掃 0982027206-0 M366088 描線之最高輸入電壓與最低輸入電壓，Cgd為寄生電容，Vgl) xCgd) / (Cgd+Clc+Cst) Form No. A0101 Page 3 of 17 where Vgh and Vgl are the highest input voltage and minimum input voltage of the trace 0982027206-0 M366088, and Cgd is the parasitic capacitance.
Clc為晝素電容’ Cst為儲存電容，由於晝素結構偏移導 致寄生電谷Cgd大幅增加而減低畫素電容與儲存電容之影 所乂電谷耗5值大幅增加。如此造成經由薄膜電晶 體控制而施加於畫素結構之輸人電壓即受到寄生電容Cgd 所對應之電絲合值的影響，亦即寄生電容所影響之電 谷耗合值所對應之—電壓準位（Δν)導㈣加於晝素上 的輸入電壓產生準位偏移，進而降低液晶顯示器之顯示 品質。 為了補償寄生電容在製程偏移時的影響，發展出一種 電容補償方式，如第二圖所示。請參閱第二圖，其為習 知晝素結構具有補償電容的示意圖。其中第一圖之畫素 結構10與第二圖之畫素結構20的差異在於第二圖之掃描 線22所延伸之閘極261再延伸一延伸部266至汲極263， 由於延伸部266係沿著晝素電極28設置，而延伸至汲極 263 ’所以畫素電極28透過走線方式而經由穿孔265耗接 至薄膜電晶體26之汲極263。習知晝素結構20係在製程上 發生了偏移，其中薄膜電晶體26因偏移導致寄生電容ca 產生偏移電容變化量ΔΠ，延伸部266於汲極263補償了 一補償電容CC，其中補償電容CC包含偏移電容變化量△ C2，且AC1 + AC2會趨近於0，因而補償製程偏移所產生 之電容變化量。但第二圖所示之延伸部266卻導致晝素電 極28需繞過延伸部266之走線’以電性連接汲極263，因 而衍生了晝素結構20之開口率下降，且經由補償電容cc 補償後仍會導致寄生電容Cgd的電容值增加，進而降低晝 素電容與儲存電容對電容耦合參數之影響。 098208393 表單編號A0101 第4頁/共17頁 0982027206-0 M366088 口匕本發明針對上述問題而提出一種畫1 僅可改善傳統補償電容導致開口率降低的問題 低電容耦合之相對變化量，可解決上述之問題 不 又可降 【新型内容】 [0003] 少 本創作之-目的，在於提供一種晝素結構 補乜電容，以補償偏移所衍、’用至 寄生電容的影響。 而降低 本創作之另-㈣，在於提供—種畫素 2膜電晶體之難所形成之補償電容降低寄生電容之 1 用 本創作之另一目的，在於提供一種晝素 =體之汲極形成補償電容，以降低補償電： 素，，、°構之開口率的影響。 于畫 *本創作之畫素結構，其包含一掃描線、 薄膜電晶體’其中掃描線與資料線相互交錯，薄腹’、 體叹置於掃描線上，薄膜電晶體包含-間極、、日日 原極相極位於該掃财，該祕相對位於該= 線上方並辑接該資料線，該沒極相對位於該延伸區上方 :該攻極與該延伸區之間具有—第—補償電容。此外， ，:之畫素結構更包含一晝素電極與一健存電容電極 ~晝素電極叙接該汲極’儲存電容電極設置於 ί容2極之_，贿極經該畫素電極延伸至該儲存 電容電，，該沒極與該儲存電容電極之間具一第二補償 補償電容極自身及其延伸部份所形成之 —素叩構因偏移所衍生之電容變化，以降 098208393 表單編號AOloi 0982027206-0 第5頁/共17頁 M366088 低寄生電容之變化量對輪入電壓的影響，並降低補償電 容對開口率之影響。 兹為使責審查委員對本創作之結構特徵及所達成之 功效更有進一步之瞭解與認識，謹佐以較佳之實施例圖 及配合詳細之說明，說明如後： 【實施方式】 [0004] 晴參閱第三圖’其為本創作之一較佳實施例之畫素結 構之結構不意圖。如圖所示，本創作之畫素結構3〇包含 —掃描線32、一資料線34與一薄膜電晶體36，其中薄膜 電晶體36包含一閘極361、一源極362與一汲極363。掃 描線32於薄膜電晶體36之相對位置上具有一延伸區322， 閘極361位於掃描線32，源極362耦接資料線34，源極 3 6 2相對位於掃描線3 2上，沒極3 6 3相對位於延伸區3 2 2 上，由於没極3 6 3相對位於延伸區3 2 2上.，所以汲極3 6 3 與延伸區322之間具有一第一補償電容CC1。此外，相對 應於第一補償電容CC1之延伸區322的寬度係大於相對應 於第一補償電谷CC1之没極363的寬度。一般掃描線32.與 資料線3 4係選自於導電材料，例如：鉻、金、銀、銘、鎖 、猛等等，且薄膜電晶體36之源極362與汲極363亦選自 於導電材料。 此外，本創作之畫素結構30更包含一畫素電極38與一 儲存電容電極40 ;其中晝素電極38係相鄰掃描線32與資 料線34，且薄膜電晶體36係經由汲極363耦接至晝素電極 38，汲極363與畫素電極38之間具有一穿孔364，供汲極 363與畫素電極38電性相接，畫素電極38係選自於透明導 098208393 表單編號A0101 第6頁/共17頁 0982027206-0 M366088 電材料，y, , . 例如：氧化銦錫（Indium-Tin Oxide，ITO) 2存電容電極40係設置於晝素電極38之周圍，且薄膜 電=體36之汲極363係延伸至晝素電極38，再延伸至儲存 電極40，如此汲極363與儲存電容電極4〇之間形成— 第二補償電容CC2，以進一步補償寄生電容。 在本創作中，第一補償電容CC1為對應寄生電eCgd， 第二補償電容CC2為對應寄生電容Cst，所以，基於影響 輸入電壓的電容耦合函數為（（Vgh_Vgl) xCgs) / (Clc is a halogen capacitor ’Cst is a storage capacitor. Since the parasitic structure shift causes the parasitic electric valley Cgd to increase greatly, the pixel capacitance and the storage capacitance are reduced. Thus, the input voltage applied to the pixel structure via the thin film transistor control is affected by the wire value corresponding to the parasitic capacitance Cgd, that is, the voltage valley corresponding to the parasitic capacitance. The bit (Δν) conducts (4) the input voltage applied to the pixel produces a level shift, which in turn reduces the display quality of the liquid crystal display. In order to compensate for the influence of parasitic capacitance during process offset, a capacitor compensation method has been developed, as shown in the second figure. Please refer to the second figure, which is a schematic diagram of a conventional halogen structure with a compensation capacitor. The difference between the pixel structure 10 of the first figure and the pixel structure 20 of the second figure is that the gate 261 extending from the scan line 22 of the second figure extends an extension 266 to the drain 263, since the extension 266 is It is disposed along the halogen electrode 28 and extends to the drain 263' so that the pixel electrode 28 is drained to the drain 263 of the thin film transistor 26 via the via 265 by way of a trace. The conventional structure 20 is offset in the process, wherein the thin film transistor 26 causes the parasitic capacitance ca to generate a shift capacitance change amount ΔΠ due to the offset, and the extension portion 266 compensates the compensation capacitor CC at the drain 263, wherein The compensation capacitor CC includes the offset capacitance change amount Δ C2, and AC1 + AC2 will approach 0, thus compensating for the amount of capacitance change caused by the process offset. However, the extension portion 266 shown in the second figure causes the halogen electrode 28 to bypass the trace 266 of the extension portion 266 to electrically connect the drain 263, so that the aperture ratio of the halogen-derived structure 20 is decreased, and the compensation capacitor is passed through the compensation capacitor. After cc compensation, the capacitance value of the parasitic capacitance Cgd will increase, which will reduce the influence of the halogen capacitor and the storage capacitor on the capacitive coupling parameters. 098208393 Form No. A0101 Page 4 of 17 0982027206-0 M366088 The present invention proposes a drawing 1 which can improve the relative variation of the low capacitance coupling, which can improve the aperture ratio of the conventional compensation capacitor, and can solve the above problem. The problem can not be reduced again [new content] [0003] The purpose of this book is to provide a halogen structure complementary capacitor to compensate for the effect of offset and 'parasitic capacitance. The other thing to reduce the creation of this creation is to provide a compensation capacitor that reduces the parasitic capacitance formed by the difficulty of a type of pixel crystal. Another purpose of the present invention is to provide a compensation for the formation of a halogen element. Capacitance to reduce the compensation of the electricity: the effect of the aperture ratio of the prime, °, °. The picture structure of the picture is composed of a scanning line, a thin film transistor, in which the scanning line and the data line are interlaced, the thin abdomen, the body sigh is placed on the scanning line, and the thin film transistor contains - the interpole, the day The Japanese original pole is located in the sweeping, and the secret is located above the line and is connected to the data line. The pole is relatively located above the extension: the first and the compensation capacitor are between the attack pole and the extension . In addition, the: pixel structure further comprises a halogen electrode and a storage capacitor electrode ~ the halogen electrode is connected to the drain electrode. The storage capacitor electrode is set at the thickness of the 2 pole, and the brittle electrode extends through the pixel electrode. To the storage capacitor, a second compensation compensation capacitor between the pole and the storage capacitor electrode and the extension of the capacitor body and the extension thereof form a change in capacitance caused by the offset of the element to reduce the 098208393 form No. Aloi 0982027206-0 Page 5 of 17 M366088 The effect of the amount of change in low parasitic capacitance on the wheel-in voltage and the effect of the compensation capacitor on the aperture ratio. In order to make the Responsible Review Committee better understand and understand the structural features and the efficacies of the creation, please refer to the preferred embodiment diagram and the detailed description to explain the following: [Embodiment] [0004] Clear Referring to the third figure, it is not intended to be a structure of a pixel structure of a preferred embodiment of the present invention. As shown, the pixel structure of the present invention includes a scan line 32, a data line 34 and a thin film transistor 36. The thin film transistor 36 includes a gate 361, a source 362 and a drain 363. . The scan line 32 has an extension 322 at a relative position of the thin film transistor 36. The gate 361 is located on the scan line 32, the source 362 is coupled to the data line 34, and the source 362 is oppositely located on the scan line 32. 3 6 3 is located on the extension 3 2 2 , and since the pole 3 36 is relatively located on the extension 3 2 2 , there is a first compensation capacitor CC1 between the drain 3 6 3 and the extension 322. Further, the width of the extension region 322 corresponding to the first compensation capacitor CC1 is greater than the width of the gate 363 corresponding to the first compensation valley CC1. The general scan line 32. and the data line 34 are selected from conductive materials such as chrome, gold, silver, imprint, lock, smash, etc., and the source 362 and the drain 363 of the thin film transistor 36 are also selected from Conductive material. In addition, the pixel structure 30 of the present invention further includes a pixel electrode 38 and a storage capacitor electrode 40; wherein the pixel electrode 38 is adjacent to the scan line 32 and the data line 34, and the thin film transistor 36 is coupled via the drain 363. Connected to the halogen electrode 38, the drain 363 and the pixel electrode 38 have a through hole 364, the drain 363 is electrically connected to the pixel electrode 38, and the pixel electrode 38 is selected from the transparent guide 098208393. Form No. A0101 Page 6 of 17 page 0982027206-0 M366088 Electrical material, y, , . For example: Indium-Tin Oxide (ITO) 2 storage capacitor electrode 40 is placed around the halogen electrode 38, and the film electricity = The drain 363 of the body 36 extends to the halogen electrode 38 and then extends to the storage electrode 40. Thus, a second compensation capacitor CC2 is formed between the drain 363 and the storage capacitor electrode 4 to further compensate for the parasitic capacitance. In the present creation, the first compensation capacitor CC1 is the corresponding parasitic electric energy eCgd, and the second compensation capacitance CC2 is the corresponding parasitic capacitance Cst, so the capacitive coupling function based on the influence of the input voltage is ((Vgh_Vgl) xCgs) / (
Cgd+Clc + Cst)，當畫素結構30發生製程偏移時，畫素 結構30可經第一補償電容(^丨與第二補償電容CC2補償， 使電谷麵合函數中代表分子之Cgd與分母之可同時增 加，以降低輸入電壓受寄生電容Cgd的影響，且本創作之 第一補償電容CC2為薄膜電息體36之汲極363延伸至儲存 電容電極40所形成，因此第二補償電容CC2並不會影響畫 素電極38之設置位置，且畫素電極38耦接汲極363不需另 外設置走線。 由上述可知，本創作係利用第償電容CC1及/或第 ...〇 .：!- 二補償電容CC2補償畫素結構纟0因製程發生偏移時所衍生 之寄生電容，藉此降低寄生電容針對對應於輸入電壓之 電容耦合值的影響，且可避免另外設置走線，以供汲極 363耦接畫素電極38。 請參閱第四圖，其為第三圖之一實施例之斷面圖。第 —圖之斷面方向為第二圖之AB方向。如圖所示，本創 作之薄膜電晶體36更包含閘極361、源極362、汲極363 以及一絕緣層365與一半導體層366，其中絕緣層365設 置於閘極361上，半導體層366設置於絕緣層365上，薄 098208393 表單編號A0101 第7頁/共17頁 0982027206-0 M366088 膜電晶體36之源極362與ί及極363分別設置於半導體層 366上方兩側，源極362耦接資料線34，汲極363經由穿 孔364耦接畫素電極38 ’由於薄膜電晶體36之源極362與 汲極363選自於導電材料’但半導體層366為半導體材料 ，所以本實施例為了使源極362與半導體層366之間以及 汲極363與半導體層之間達到歐姆接觸，源極362與半導 體層366之間更設置有一第一歐姆接觸層367，且沒接 363與半導體層366之間更設置有一第二歐姆接觸層368 ’ 一般第一歐姆接觸層367與第二歐姆接觸層368為捧雜 半導體層’例如：Ν型掺雜之非晶梦氧化合金（ν+ )。此外，本實施例之薄膜電晶體36更包含一保護層36g ’其設置於源極362與汲極363之上。 復參閱第三圖，本創作之掃描線32係耦接至—掃插驅 動電路42，資料線34係耦接至一資料驅動電路44，掃妆 驅動電路42係產生至少一掃描訊號並傳送至掃插線32， 資料驅動電路44產生至少，資料訊號並傳送至資料線34 ’當薄膜電晶體36經由閛極361接收掃描訊號，而驅使半 導體層366形成暫時性通道時’若薄膜電晶體36於同—時 間經源極362接收資料訊號，則資料訊號可經半導體層 366傳輸至汲極363，以傳送至晝素電極38，因而產生驅 動電壓，用於驅動相對位於晝素結構30之液晶，而晝素 電極38之有效使用面積即相當於畫素結構3〇之開口率， 本創作之第一補償電容CC1及/或第二補償電容cC2並不會 導致畫素電極38與薄膜電晶體36之間的電性連接方式， 所以可降低補償電容對於畫素電極38之設置方式的影響 ，如此本創作之第一補償電容cci及/或第二補償電容CC2 098208393 表單編號A0101 第8頁/共17頁 0982027206-0 M366088 可避免晝素結構30之開口率嚴重下降。 綜上所述，本創作為一種晝素結構，其利用薄膜電晶 體之汲極所衍生之補償電容降低寄生電容之變化，且因 補償電容之設置不會導致晝素電極之走線改變，所以本 創作可降低補償電容對畫素結構之開口率的影響。 故本創作實為一具有新穎性、進步性及可供產業上利 用者，應符合我國專利法專利申請要件無疑，爰依法提 出新型專利申請，祈鈞局早曰賜准專利，至感為禱。 惟以上所述者，僅為本創作一較佳實施例而已，並非 I 用來限定本創作實施之範圍，故舉凡依本創作申請專利 範圍所述之形狀、構造、特徵及精神所為之均等變化與 修飾，均應包括於本創作之申請專利範圍内。 【圖式簡單說明】 [0005] 第一圖為習知畫素結構的示意圖； 第二圖為習知畫素結構具補償電容之示意圖； 第三圖為本創作之一較佳實施例之畫素結構的示意圖； » 以及 第四圖為第三圖之畫素結構的斷面圖。 【主要元件符號說明】 [0006] 10 晝素結構 ' 12 掃描線 . 14 資料線 16 薄膜電晶體 161 閘極 162 源極 098208393 表單編號A0101 第9頁/共17頁 0982027206-0 M366088 163 波極 164 半導體層 165 穿孔 18 晝素電極 20 晝素結構 22 掃描線 24 資料線 26 薄膜電晶體 261 閘極 262 源極 263 汲極 264 半導體層 265 穿孔 266 延伸部 28 晝素電極 30 畫素結構 32 掃描線 34 資料線 36 薄膜電晶體 361 閘極 362 源極 363 汲極 364 穿孔 365 絕緣層 366 半導體層 367 第一歐姆接觸層 表單編號A0101 098208393 第10頁/共17頁 0982027206-0 M366088 368 第二歐姆接觸層 369 保護層 38 畫素電極 40 儲存電容電極 42 掃描驅動電路 44 資料驅動電路 CA 補償電容 CC 補償電容 CC1 第一補償電容 CC2 第二補償電容 0982027206-0 098208393 表單編號A0101 第11頁/共17頁Cgd+Clc + Cst), when the pixel structure 30 is offset, the pixel structure 30 can be compensated by the first compensation capacitor (^丨 and the second compensation capacitor CC2, so that the Cgd of the representative molecule in the electric valley junction function The denominator can be simultaneously increased to reduce the input voltage from being affected by the parasitic capacitance Cgd, and the first compensation capacitor CC2 of the present invention is formed by the drain 363 of the thin film electrical body 36 extending to the storage capacitor electrode 40, so the second compensation Capacitor CC2 does not affect the position of the pixel electrode 38, and the pixel electrode 38 is coupled to the drain 363 without additional routing. As can be seen from the above, the author uses the compensation capacitor CC1 and/or ... 〇.:!- The second compensation capacitor CC2 compensates for the pixel structure 纟0 parasitic capacitance due to the offset of the process, thereby reducing the influence of the parasitic capacitance on the capacitive coupling value corresponding to the input voltage, and avoiding the additional setting The line is provided for the drain electrode 363 to be coupled to the pixel electrode 38. Please refer to the fourth figure, which is a cross-sectional view of an embodiment of the third figure. The cross-sectional direction of the first figure is the AB direction of the second figure. As shown in the figure, the thin film transistor 36 of this creation is further included. a gate 361, a source 362, a drain 363, and an insulating layer 365 and a semiconductor layer 366, wherein the insulating layer 365 is disposed on the gate 361, and the semiconductor layer 366 is disposed on the insulating layer 365, thin 098208393 Form No. A0101 No. 7 Pages / Total 17 pages 0982027206-0 M366088 The source 362 and the 355 of the film transistor 36 are respectively disposed on both sides of the semiconductor layer 366, the source 362 is coupled to the data line 34, and the drain 363 is coupled via the through hole 364. Since the source electrode 362 and the drain 363 of the thin film transistor 36 are selected from the conductive material 'but the semiconductor layer 366 is a semiconductor material, the present embodiment is for the source 362 and the semiconductor layer 366 and the drain 363. An ohmic contact is formed between the source layer 362 and the semiconductor layer 366, and a second ohmic contact layer 368 is disposed between the 365 and the semiconductor layer 366. The one-ohmic contact layer 367 and the second ohmic contact layer 368 are a semiconductor layer of a semiconductor layer, for example, a germanium-doped amorphous dream oxide alloy (ν+). In addition, the thin film transistor 36 of the present embodiment further includes a protective layer. 36g 'its design Above the source 362 and the drain 363. Referring to the third figure, the scan line 32 of the present invention is coupled to the sweeping driver circuit 42, the data line 34 is coupled to a data driving circuit 44, and the makeup driver is driven. The circuit 42 generates at least one scan signal and transmits it to the sweep line 32. The data drive circuit 44 generates at least the data signal and transmits it to the data line 34'. When the thin film transistor 36 receives the scan signal via the drain 361, the semiconductor layer 366 is driven. When the temporary channel is formed, if the thin film transistor 36 receives the data signal through the source 362 at the same time, the data signal can be transmitted to the drain 363 via the semiconductor layer 366 for transmission to the halogen electrode 38, thereby generating a driving voltage. For driving the liquid crystal relative to the pixel structure 30, and the effective use area of the halogen electrode 38 is equivalent to the aperture ratio of the pixel structure 3, the first compensation capacitor CC1 and/or the second compensation capacitor cC2 of the present invention The electrical connection between the pixel electrode 38 and the thin film transistor 36 is not caused, so that the influence of the compensation capacitance on the arrangement of the pixel electrode 38 can be reduced, so that the first compensation capacitor cci of the present creation And/or the second compensation capacitor CC2 098208393 Form No. A0101 Page 8 of 17 0982027206-0 M366088 The aperture ratio of the halogen structure 30 can be prevented from being seriously degraded. In summary, the creation is a halogen structure, which uses the compensation capacitor derived from the drain of the thin film transistor to reduce the variation of the parasitic capacitance, and the setting of the compensation capacitor does not cause the change of the trace of the halogen electrode, so This creation reduces the effect of the compensation capacitance on the aperture ratio of the pixel structure. Therefore, this creation is a novelty, progressive and available for industrial use. It should be consistent with the patent application requirements of China's patent law. It is undoubtedly a new type of patent application, and the Prayer Council will grant patents as soon as possible. . However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so the shape, structure, characteristics and spirit described in the scope of the patent application are equally changed. And modifications should be included in the scope of the patent application of this creation. BRIEF DESCRIPTION OF THE DRAWINGS [0005] The first figure is a schematic diagram of a conventional pixel structure; the second figure is a schematic diagram of a conventional pixel structure with a compensation capacitor; Schematic diagram of the prime structure; » and the fourth figure is a sectional view of the pixel structure of the third figure. [Main component symbol description] [0006] 10 昼 structure 12 12 scan line. 14 data line 16 thin film transistor 161 gate 162 source 098208393 Form No. A0101 Page 9 of 17 0982027206-0 M366088 163 Wave 164 Semiconductor layer 165 perforation 18 halogen electrode 20 halogen structure 22 scanning line 24 data line 26 thin film transistor 261 gate 262 source 263 drain 264 semiconductor layer 265 perforation 266 extension 28 germanium electrode 30 pixel structure 32 scan line 34 data line 36 thin film transistor 361 gate 362 source 363 drain 364 via 365 insulating layer 366 semiconductor layer 367 first ohmic contact layer form number A0101 098208393 page 10 of 17 page 0982027206-0 M366088 368 second ohmic contact Layer 369 Protective layer 38 Pixel electrode 40 Storage capacitor electrode 42 Scan drive circuit 44 Data drive circuit CA Compensation capacitor CC Compensation capacitor CC1 First compensation capacitor CC2 Second compensation capacitor 0992027206-0 098208393 Form number A0101 Page 11 of 17