M362447 五、新型說明： 【新型所屬之技術領域】 本新型係關於一種重置 訊號產生·。 ，域涉及—觀置倾ϋ之重置 【先前技術】 隨著電子科技的進步，各 型的電子裝置具有-處_ 、衣置已愈趨於小型化，此種小 子裝置常常因為硬體運作行運算處理。而這種小型化電 電源不穩定献_趟_^==^如開機時 令而2=動作的現象。此時，需要重置二來重置處 = 壬何指 當刖’處理n的重置電魅 ^處理為 =-個計時電路及相對應的計時暫存器丄器内 :·’Γ=Γ的值在間隔的時間内沒有被重寫乞 减，另-種讀用相的重置频電路 結髓雜、縣較高。 W鮮稍重置電路 【新型内容】 有鑒於此，需提供一種曹罟余 置’具有較低的成本，且Γ構可實_的重 一種重置訊號產生電路驗重置處理器，包括 電路及觸發電路。其中，該充電電路用於當 2、放電 處理器之定時脈衝訊號，並根據該定時脈衝訊號提供充 2當该處理㈣現故_不提供充物4。放魏路連接於咳 電路’用於當該處理器正常時根據該充電電流進行充電，狀當該 M362447 處理器出現輯時進行放電讀出-低電壓訊號。觸發電路與該處 理器及該放電電路树，驗_該低訊號，並根據該低電壓 訊號輸出觸發訊號至該處理器以重置該處理器。 藉由以下對具體實施方式詳細的描述結合附圖，將可輕易的瞭 解上述内容及此項新型之諸多優點。 【實施方式】 圖1所不係本新型一實施方式之重置訊號產生電路之電路圖。 鲁在本實施方式中，該重置訊號產生電路用於在處理器4〇出現故障時 生成重置減以重置鱗理II 4〇，其包括充電電路、放電電路如 以及觸發電路30。處理器4〇包括一通用输々输出(Generai pu_eM362447 V. New description: [New technical field] This new type is about a reset signal generation. , domain involves - resetting of the dumping [previous technology] With the advancement of electronic technology, various types of electronic devices have - the _, the clothing has become more and more miniaturized, such small devices often operate because of hardware Row arithmetic processing. And this miniaturized power supply is unstable. _趟_^==^ If the power is turned on and the 2= action phenomenon. At this point, you need to reset the second to reset the location = 壬 指 刖 处理 'Processing n reset electric charm ^ processed as = - a timing circuit and the corresponding timer register: · 'Γ = Γ The value of the read-frequency phase is not rewritten and reduced in the interval time. W fresh reset circuit [new content] In view of this, it is necessary to provide a kind of reset signal generation circuit resetting processor, including circuit, which has a lower cost and has a lower cost. And the trigger circuit. Wherein, the charging circuit is used for the timing pulse signal of the discharge processor, and the charging signal is provided according to the timing pulse signal. When the processing (4) occurs, the filling 4 is not provided. The Wei road is connected to the cough circuit 'for charging according to the charging current when the processor is normal, and the discharge reading-low voltage signal is generated when the M362447 processor appears. The trigger circuit and the processor and the discharge circuit tree check the low signal and output a trigger signal to the processor according to the low voltage signal to reset the processor. The above and many of the novel advantages are readily apparent from the following detailed description of the embodiments of the invention. [Embodiment] FIG. 1 is a circuit diagram of a reset signal generating circuit according to an embodiment of the present invention. In the present embodiment, the reset signal generating circuit is configured to generate a reset minus a reset scale II 4 when the processor 4 fails, and includes a charging circuit, a discharging circuit, and a trigger circuit 30. The processor 4〇 includes a general-purpose output (Generai pu_e)
Input Output，GPIO)接腳以及—重置接腳，其可為_央處理哭 (C_r〇—Unit ’ CPU)或者微處理器(臟· MCU)等。 充電電路10用於當處理器4〇正常工作時從處理器之側〇 接腳接蚊雜衝峨，細蚊雜衝峨提縣钱流，以及 當處理器4〇出現故障時不提供充電電流。在本實施例中，當處理器 4〇正常時’處理ϋ 4G纽過其_接嘴蚊時脈衝訊號至充電 =路1〇 °充電電路10包括運算放大器，’運算放大器饥之同相 輸入端連接於處财射及其輸出端，其反向輸人端接地，以形成 緩触’用於提供充電電流至放電電路2〇以使該放電電路2〇快速 充電。 放電電路20連接於充電電路1〇，用於當處理器初正常工作時 艮虞充電電流進行充電，以及當處理器4〇出現故障時進行放電以輸 低電壓訊號。在本實施例中，放電電路2〇包括第一電阻以與充 M362447 電電容C2。其中，該第—電阻Ri連接於運算放大器 ，間’ _紅2連接於運算放大器饥之輸_地:第 %阻111用於為充電電玄兩 _ 弟 電時間。 祕放祕徑並確做tf路20的放 觸發電路30與處理4n R & ^ , - ,ρ,# 電電路20相連’用於偵測低電壓 ^在本中Γ號輪出觸發訊號至處理器4〇以重置處理器 在中’觸發電路3〇包括n通道金屬氧 阻^=容=金屬氧化物電咖之桃極連接於第一電 金屬_ 、雜接地。第二電阻R2連接於該Ν通道 ^屬軋化物電晶細之漏極，Ν通道金屬 電阻2之公共節點連接於處理器40之重置訊號輪入端體M11 括搞入雷ί發明一實施方式之進一步中，該重置訊號產生電路還包 =電谷α與二極體D1，合電容C1連接於處理 ，咖嶋。二極㈣ 流逆流。 G，其陰極連接於放電電路3G，用於防電 始=本發明一實施方式中，當該處理器4〇正常工作時，其GPI0 號腳二號:轉_ C1隔絕該定時脈衝訊號之直流訊 人電六γΓΓ氣以及快速變動之訊號通過。定時脈衝訊號經由輕 :二電容==大器U1’運算放大器U1之同相輸入端連接 /、輪出端’其反向輸入端接地，以形成緩衝器， 猎由外接33V電壓而輸出高電壓訊號。該高電壓訊號經由 極W1傳輸至充電電容C2與N通道金屬氧化物電晶體M1之柵 電電容C2儲存電荷，此時，該N通道金屬氧化物電晶體 M362447Input Output, GPIO) pins and reset pins, which can be used to process crying (C_r〇-Unit' CPU) or microprocessor (dirty MCU). The charging circuit 10 is used to pick up the mosquitoes from the side of the processor when the processor 4 is working normally, the fine mosquitoes and the money flow, and the charging current is not provided when the processor 4 fails. . In the present embodiment, when the processor 4 is normal, the processing signal is transmitted to the charging circuit. The charging circuit 10 includes an operational amplifier, and the operational amplifier is connected to the non-inverting input terminal. At the end of the fuse and its output, the reverse input terminal is grounded to form a slow contact 'for supplying a charging current to the discharge circuit 2 〇 to enable the discharge circuit 2 to be quickly charged. The discharge circuit 20 is connected to the charging circuit 1 for charging the charging current when the processor is initially operating normally, and discharging to output a low voltage signal when the processor 4 fails. In this embodiment, the discharge circuit 2A includes a first resistor to charge the M362447 capacitor C2. Wherein, the first resistor Ri is connected to the operational amplifier, and the _ red 2 is connected to the operational amplifier hunger _ ground: the first resistor 111 is used for charging the electric power. The secret path and the trigger circuit 30 of the tf circuit 20 are connected to the processing 4n R & ^ , - , ρ, # electrical circuit 20 'for detecting low voltage ^ in the middle of the ring to trigger the signal to The processor 4 is configured to reset the processor in the 'trigger circuit 3', including the n-channel metal oxide resistor, and the metal oxide is connected to the first metal, and the ground is connected. The second resistor R2 is connected to the drain of the germanium channel, and the common node of the germanium channel metal resistor 2 is connected to the reset signal of the processor 40. The terminal body M11 includes the implementation of the invention. In a further aspect, the reset signal generating circuit further includes a voltage valley α and a diode D1, and the combined capacitor C1 is connected to the processing, the curry. Two poles (four) flow countercurrent. G, the cathode is connected to the discharge circuit 3G, and is used for preventing the electric start. In an embodiment of the present invention, when the processor 4 is in normal operation, the GPI0 pin 2: _ C1 isolates the DC of the timing pulse signal. The signal of the six gamma helium and the rapid change of the signal passed. The timing pulse signal is connected via the light: two capacitor == large U1' op amp U1 non-inverting input terminal, the round terminal 'the reverse input terminal is grounded to form a buffer, and the hunting is outputted by an external 33V voltage to output a high voltage signal. . The high voltage signal is transferred to the charging capacitor C2 via the pole W1 and the gate capacitor C2 of the N-channel metal oxide transistor M1 to store the charge. At this time, the N-channel metal oxide transistor M362447
Ml之輸入電壓大於其臨界電壓，N通道金屬氧化物電晶體奶 並將該輸人頓雜至地。在本實财射，該N财销氧^ 電晶體Ml外接3.3V電堡，確保了處理器4〇開始工作的瞬間 的電壓導通該N通道金屬氧化物電晶體M1。 當該處理器4〇發生故障時，其GPI〇接腳停止輸出定時脈料 號’運异放大器U1停止輸出高電屡訊號。此時，充電電容c 放電以輸出低紐緘’第—觀R1域電絲口提供了放 徑’並確保了足夠的放電時間。二極體m之陽極與算放大器U 輸出端連接，其陰極與第-電阻R1與充電電容C2連接，防 此，謝_訊號輸人至_____二 通道金屬氧化物電晶體組由於輸入之低電壓訊號小於其臨界電壓 而截止’該财壓訊號成為觸發訊號被輪出至處理器40之重 輸入端。在本實施方式中’第二電⑽連接於該N通道金屬氧化： 電晶體Mi之漏極，限置該觸發訊號之電流。 觀化物 =2所=本新型—實施方式之重置訊號產生電路之訊號波形 丄⑷所不之曲線為充電電容C2之訊號波形圖，處理器4〇 ^工作時輸蚊時脈衝峨嘱電容c2約鳥告 障時停止輸出定時叫 ΪΪ電==麵正常工作時，輸出定時脈衝訊號，並藉由 充冤電路10對充電電容C2繼續充電。 _圖卢之曲_ N通道金屬氧化物電晶體Ml之訊號波 電:體Ϊΐ :正^工作時輸出定時脈衝訊號，N通道金屬氧化物 體L正壓大於其臨界電壓，該ν通道金屬氧化物電晶 ㈣。物躺峡轉時，Ν通細氧化物電晶 M362447 體M1之輸入麵小於其臨界龍，該 停止工作。直到處理器4〇重新正常工ζ乳化物電晶體Ml 晶體Ml繼續正常工作。 〇x通道金屬氧化物電 圖2 (c)所示之曲線為觸發 工作時，N通道今屬翁儿仏 之訊唬波形圖，處理器4〇正常 地，此時沒有觸發麵。將其以M傳輸至 ^體則h= 到處理器40重新正常工作眸，兮Μ、3 β U ^ —• 通道金屬氧化物電晶體Ml重新 導通並將其輸入電壓傳輸至地。 姑雷3_対峨供之麵繼生電路_充電電路10、 ί= 7發電路3G來產生_壓’再將觸發電壓輸入 .,,°之重置而虎輪入端，實現處理器40的重置，具有較低 的成本，且結構簡單。 ,，綜上所述’搞藉合_專利要件，纽法提出專利申請。 准以辆述者僅為本新型之較佳實施例，舉凡熟悉本案技藝之人 士，在爰依本案新型精神所作之等效修飾或變化，皆應包含於以下 之申睛專利範圍内。 【圖式簡單說明】 圖1為本新型一實施方式重置訊號產生電路之電路圖。 圖2為本新型一實施方式重置訊號產生電路之訊號波形圖。 【主要元件符號說明】 充電電路 10 放電電路 7 20 M362447 觸發電路 30 處理器 40 耦合電容 C1 充電電容 C2 運算放大器 U1 二極體 D1 第一電阻 R1 φ 第二電阻 R2 N通道金屬氧化物電晶體 Ml 8The input voltage of Ml is greater than its threshold voltage, N-channel metal oxide transistor milk and the input is mixed to ground. In this real financial, the N-selling oxygen ^ transistor Ml externally connected to the 3.3V electric castle, ensuring that the voltage at the instant of the start of operation of the processor 4〇 turns on the N-channel metal oxide transistor M1. When the processor 4 fails, its GPI pin stops outputting the timing pulse number. The transmission amplifier U1 stops outputting the high power relay signal. At this time, the charging capacitor c is discharged to output a low-turn 'first-view R1 domain wire port to provide a diameter' and to ensure sufficient discharge time. The anode of the diode m is connected to the output terminal of the amplifier U, and the cathode is connected to the first resistor R1 and the charging capacitor C2. In view of this, the signal is input to the _____ two-channel metal oxide transistor group due to the input. The low voltage signal is less than its threshold voltage and the cutoff 'the financial pressure signal becomes the trigger signal is turned out to the heavy input end of the processor 40. In the present embodiment, the second electric (10) is connected to the N-channel metal oxide: the drain of the transistor Mi, which limits the current of the trigger signal. Observation = 2 = The new type - the signal waveform of the reset signal generation circuit of the embodiment 丄 (4) The curve of the signal is the signal waveform of the charging capacitor C2, and the pulse 峨嘱 capacitance c2 when the processor is operated When the bird stops shooting, the output timing is called ΪΪ = == When the surface is working normally, the timing pulse signal is output, and the charging capacitor C2 is continuously charged by the charging circuit 10. _Tulu's Song _ N-channel metal oxide transistor Ml signal wave: body Ϊΐ: positive ^ output timing pulse signal, N channel metal oxide body L positive pressure greater than its threshold voltage, the ν channel metal oxide Electro-crystal (4). When the object is lying in the gorge, the input surface of the fine oxide oxide crystal M362447 body M1 is smaller than its critical dragon, which stops working. Until the processor 4 restarts the normal operation, the emulsion transistor M1 crystal M1 continues to operate normally. 〇x channel metal oxide electricity Figure 2 (c) shows the signal of the triggering operation, the N channel is now the signal waveform of Weng Er, the processor 4 〇 normal, there is no trigger surface. Transfer it to M and then h= until processor 40 is working again. 兮Μ, 3 β U ^ —• Channel metal oxide transistor M1 is turned back on and its input voltage is transferred to ground. Gulei 3_ 対峨 之 继 继 继 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The reset has a lower cost and a simple structure. In summary, the above-mentioned "involvement of patents", New Zealand filed a patent application. The subject matter of the vehicle is only the preferred embodiment of the present invention. Any equivalent modifications or changes made by those who are familiar with the skill of the present invention in the novel spirit of the present invention shall be included in the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a reset signal generating circuit according to an embodiment of the present invention. 2 is a waveform diagram of a signal of a reset signal generating circuit according to an embodiment of the present invention. [Main component symbol description] Charging circuit 10 Discharging circuit 7 20 M362447 Trigger circuit 30 Processor 40 Coupling capacitor C1 Charging capacitor C2 Operational amplifier U1 Diode D1 First resistor R1 φ Second resistor R2 N-channel metal oxide transistor Ml 8