M338506 八、新型說明： [新型所屬之技術領域] 本創作涉及-種時序控制電路，特別是指一種用於控 制主機板上電時序的電路。 [先前技術】 晶片組是主機板的重要組成部分，幾乎決定著主機板 T全部功能。主機板的晶片組通常包括南橋晶片和北橋晶 其中’南橋晶片主要負責週邊設備的資料處理與傳 一旦南橋晶片出現問題’則會導致週邊設備無法使 用。北橋晶片負責與C PU聯繫並控制記憶體，提供對㈣ _型和主頻、系統的前端匯流排頻率、記憶體的類型和 最大容量等的支援。 、 使用不同的電源為主機板上的南橋和北橋晶片上電 時，由於不同的電源在開啟之後會在不同的時間内攸升至 其峰值，從而從南橋和北橋晶片輸出的信號時序會有不 :。如圖ί及2所示’為不同電源在特定時間I内爬 升至其峰值的二維圖。由圖i可知，+33v電源較早爬升 ^值’ +5V電源最輪升至其峰值。由圖2可知，+5V 電源較早爬升至峰值，+12V電源最晚爬升至峰值。 這樣，當使用不同的電源控制主機板上的南橋和北橋 =^電時，有可能沒有按照預期上電時序控制主機板上 电致主機板上電時序錯亂。如圖3所示，使用圖工中 的+5V電源控制北橋晶片上電，+3·3ν 上電’從北橋晶片輸出的A信號要晚于從南橋晶= 二 6 M338506 B信號，然而，若期望得到從北橋晶片輸出的A信號早于 從南橋晶片輸出的B信號，則必須要更換電源，否則不能 實現。這樣對不同的電源的相容性不好。 【新型内容】 鑒於以上内容，有必要提供一種能夠控制主機板正常 . 上電時序的電路。 _ 一種時序控制電路，用於控制主機板的上電時序，該 時序控制電路包括一控制主機板上電的晶片，主機板的各 * 種輸入電壓共同連接於該晶片的輸入端，該晶片設有一臨 界電壓，當該晶片的輸入端的電壓達到該臨界電壓時，該 晶片的輸出端輸出一信號控制該主機板上電。 相對于習知技術，本創作時序控制電路中，只有在各 種輸入電壓均達到峰值後，該時序控制電路產生一高電平 信號控制主機板上電。保證了不同電源控制主機板上電的 上電時序。 • 【實施方式】 ~ 請參閱圖4，圖4為本創作時序控制電路較佳實施方 . 式的一電路圖。該時序控制電路的較佳實施方式包括一第 一分壓電路10、一第二分壓電路20、一第三分壓電路30、 一分壓電阻R1及一晶片（型號U527) 50。 該第一分壓電路10包括一電阻R11及與其相連接的 兩並聯電阻R12、R13，該第二分壓電路20包括一電阻 R21及與其相連接的兩並聯電阻R22、R23，該第三分壓 電路30包括一電阻R31及與其相連接的兩並聯電阻 7 M338506 R32、R33。該晶片50設有一輸入電壓針腳VIN，一與+3·3ν 備用電源相連為該晶片50供電的針腳vCC及一輸出電壓 針腳ENOUT。 該第一分壓電路10的電阻R11的一端連接一第一電 源+3.3V，另一端連接該第一分壓電路1〇的兩並聯電阻 -R12、R13並聯後的共同端，該兩並聯電阻R12、R13的另 _ 一端連接分壓電阻R1，R1的另一端接地。該第二分壓電 I 路20的電阻R21的一端連接一第二電源+5V，另一端連接 該第二分壓電路20的兩並聯電阻R22、R23並聯後的共同 端’該兩並聯電阻R22、R23的另一端連接分壓電阻R1， 且與第一分壓電路10相交於共同點C。第三分壓電路30 的電阻R31的一端連接一第三電源+ 12V，另一端連接該第 三分壓電路30的兩並聯電阻R32、R33並聯後的共同端， 該兩並聯電阻R32、R33的另一端連接分壓電阻R1，即連 接於共同點C。該共同點C與該晶片50的輸入電壓針腳 _ VIN連接。 * 下面詳細介紹本創作時序控制電路的工作過程。 在本創作時序控制電路中，R1為20K歐姆，R11為 240K歐姆，R12、R13為12K歐姆，R21為402K歐姆， R22、R23 為 10K 歐姆，R31 為 1.21M 歐姆，R32、R33 為 160K歐姆，第一電源+3.3V、第二電源+5V、第三電源+ 12V 分別藉由該第一分壓電路10、第二分壓電路20、第三分 壓電路30分壓後，在C點產生的電壓為+0.6V。從而，該 +0.6V電壓輸入到該晶片50的針腳VIN。該晶片50設有 M338506 一臨界電壓值為+0.6V，當輸入的電壓大於等於+〇 6v時， 產生一同電平#號S從針腳ENOUT輸出，如圖5所示。 遠尨號呂輸入至主機板上的南橋或北橋晶片。當輸入的電 壓小於+0.6V時，該晶片50則產生一低電平信號。 這樣，假設第二電源+5V、第三電源+ 12V已到達，但 第-電源+3.3V還未到達，在共同點c產生的電壓未達到 * +〇.6V，則晶片50的針腳ENOUT不輸出高電平信號s， 鲁攸而導致南橋或北橋晶片沒有上電，確保主機板時序正 ::請-併參閱圖5，當第一電源+33V，第二電源+5v， 第三電源+ 12V都達到峰值後，在共同點c才會產生後^ 電壓，並同時會產生一個高電平輸出信號S，為主機板上 電。若期望從北橋輸出的信號早于從南橋輸出的信號，口 需在輸出信號S後連接一邏輯電路，延遲該信號s輸入; $橋晶片，從而保證從北橋輸出的信號早于從南橋輸出的 本創作時序控制電路中，可使用不同晶片替換晶片 5〇,即㈣換後的晶片的臨界電壓值也發生了改變 樣，只需相應更換該第—分壓電路、第二分壓電路二 分壓電路及分壓電㈣卩可滿足要求。料，當使用的^ 中壓值不^特定電壓時’例如+2〇.3ν，此時^控 制电路中亚不需要分壓電路，因為此時只有在+33V’M338506 VIII. New Description: [New Technology Field] This creation involves a kind of timing control circuit, especially a circuit for controlling the power timing of the main board. [Prior Art] The chipset is an important part of the motherboard, and it almost determines the overall function of the motherboard. The chipset of the motherboard usually includes the south bridge wafer and the north bridge crystal. The 'Southbridge wafer is mainly responsible for the data processing and transmission of the peripheral equipment. Once the south bridge wafer has problems', the peripheral equipment cannot be used. The Northbridge chip is responsible for contacting the CPU and controlling the memory, providing support for (4) _ type and frequency, system front-end bus frequency, memory type and maximum capacity. When using different power supplies to power up the south bridge and north bridge chips on the motherboard, since the different power supplies will rise to their peaks in different time after being turned on, the signal timing output from the south bridge and the north bridge chip will not be :. As shown in Figures ί and 2, a two-dimensional map of different power sources climbing to their peaks at a specific time I. As can be seen from Figure i, the +33v power supply climbs earlier. The value '+5V power supply rises to its peak value. As can be seen from Figure 2, the +5V power supply climbed to the peak earlier, and the +12V power supply climbed to the peak at the latest. In this way, when different power supplies are used to control the south bridge and the north bridge of the main board, it may not be possible to control the on-board power timing disorder on the main board according to the expected power-on sequence. As shown in Figure 3, using the +5V power supply in the drawing to control the powering of the Northbridge chip, +3·3ν power-on's the A signal output from the Northbridge chip is later than the signal from the South Bridge = 2 M M M M M M M M. It is expected that the A signal output from the north bridge chip is earlier than the B signal output from the south bridge chip, and the power supply must be replaced, otherwise it cannot be realized. This is not compatible with different power supplies. [New content] In view of the above, it is necessary to provide a circuit capable of controlling the normal timing of the motherboard. _ a timing control circuit for controlling the power-on sequence of the motherboard, the timing control circuit includes a chip for controlling the power on the motherboard, and each of the input voltages of the motherboard is commonly connected to the input end of the chip, and the chip is set There is a threshold voltage. When the voltage at the input of the chip reaches the threshold voltage, the output of the chip outputs a signal to control the power on the motherboard. Compared with the prior art, in the authoring timing control circuit, the timing control circuit generates a high level signal to control the power on the main board only after various input voltages reach a peak value. The power-on timing of the power supply of different power control mainframes is guaranteed. • [Embodiment] ~ Please refer to FIG. 4, which is a circuit diagram of a preferred embodiment of the creation timing control circuit. A preferred embodiment of the timing control circuit includes a first voltage dividing circuit 10, a second voltage dividing circuit 20, a third voltage dividing circuit 30, a voltage dividing resistor R1, and a chip (Model U527). . The first voltage dividing circuit 10 includes a resistor R11 and two parallel resistors R12 and R13 connected thereto. The second voltage dividing circuit 20 includes a resistor R21 and two parallel resistors R22 and R23 connected thereto. The three-divided circuit 30 includes a resistor R31 and two parallel resistors 7 M338506 R32, R33 connected thereto. The chip 50 is provided with an input voltage pin VIN, a pin vCC for supplying power to the chip 50 and an output voltage pin ENOUT connected to the +3·3ν standby power source. One end of the resistor R11 of the first voltage dividing circuit 10 is connected to a first power source +3.3V, and the other end is connected to the common end of the parallel resistors R12 and R13 of the first voltage dividing circuit 1〇, the two ends. The other end of the parallel resistors R12 and R13 is connected to the voltage dividing resistor R1, and the other end of the R1 is grounded. One end of the resistor R21 of the second partial piezoelectric I path 20 is connected to a second power source +5V, and the other end is connected to the common terminal of the two parallel resistors R22 and R23 of the second voltage dividing circuit 20 in parallel. The other end of R22 and R23 is connected to the voltage dividing resistor R1 and intersects the first voltage dividing circuit 10 at a common point C. One end of the resistor R31 of the third voltage dividing circuit 30 is connected to a third power source + 12V, and the other end is connected to the common terminal of the parallel resistors R32 and R33 of the third voltage dividing circuit 30, and the two parallel resistors R32, The other end of R33 is connected to the voltage dividing resistor R1, that is, connected to the common point C. This common point C is connected to the input voltage pin _VIN of the wafer 50. * The working process of the timing control circuit of this creation is described in detail below. In this authoring timing control circuit, R1 is 20K ohms, R11 is 240K ohms, R12 and R13 are 12K ohms, R21 is 402K ohms, R22 and R23 are 10K ohms, R31 is 1.21M ohms, and R32 and R33 are 160K ohms. The first power supply +3.3V, the second power supply +5V, and the third power supply +12V are respectively divided by the first voltage dividing circuit 10, the second voltage dividing circuit 20, and the third voltage dividing circuit 30, The voltage generated at point C is +0.6V. Thus, the +0.6 V voltage is input to the pin VIN of the wafer 50. The wafer 50 is provided with a threshold voltage value of +0.6V of M338506. When the input voltage is greater than or equal to +〇 6v, the same level ## is generated from the pin ENOUT, as shown in FIG. The remote sign is input to the south bridge or north bridge chip on the motherboard. When the input voltage is less than +0.6V, the wafer 50 produces a low level signal. Thus, assuming that the second power supply +5V, the third power supply +12V has arrived, but the first power supply +3.3V has not arrived, and the voltage generated at the common point c does not reach * +〇.6V, the pin ENOUT of the wafer 50 is not Output high level signal s, reckless and cause the South Bridge or North Bridge chip to not power on, to ensure that the motherboard timing is positive:: Please - and refer to Figure 5, when the first power +33V, the second power +5v, the third power + After 12V reaches the peak value, the post-voltage will be generated at the common point c, and a high-level output signal S will be generated at the same time to power the main board. If it is desired that the signal output from the north bridge is earlier than the signal output from the south bridge, the port needs to be connected to a logic circuit after the output signal S to delay the input of the signal s; the bridge chip ensures that the signal output from the north bridge is earlier than the output from the south bridge. In the creation timing control circuit, different wafers can be used to replace the wafer 5〇, that is, (4) the threshold voltage value of the replaced wafer is also changed, and the first voltage dividing circuit and the second voltage dividing circuit need to be replaced accordingly. The two-divider circuit and the divided piezoelectric (four) 卩 can meet the requirements. It is expected that when the voltage used is not a specific voltage, for example, +2〇.3ν, at this time, the voltage control circuit is not required in the control circuit because it is only at +33V'
11 ' " B^，J ^ ^ ^ ^-20.3V U才會輸出-高電平信號為主機板上電。 知上所达，本創作符合新型專利之要件，爰依法提出 9 M338506 J申二惟，以上僅為本創作之較佳實施例，舉凡熟悉 本案技藝之人士，於爰依本創作精神所作之等效修飾或； 匕，皆應涵蓋於以下之申請專利範圍内。11 ' " B^,J ^ ^ ^ ^-20.3V U will output - the high level signal is the board power. Knowing the above, this creation meets the requirements of the new patent, and is proposed according to law. 9 M338506 J Shen Erwei, the above is only the preferred embodiment of this creation. For those who are familiar with the skill of this case, Yu Yiyi’s spirit of creation Modifications; or 匕, should be covered by the following patents.
【圖式簡單說明】 圖1係習知技術中 圖2係習知技術中 圖3係習知技術中 片上電的不意圖。 不同電源隨時間爬升的座標圖。 不同電源隨時間爬升的座標圖。 不同電源為主機板上的南橋與北橋 曰a 圖4係本創作時序控制 圖5係本創作時序控制電：::：知方式的電路圖 制兒路較佳實施方式的時序圖 【主要元件符號說明】 第一分壓電路10 第BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a prior art in FIG. 2 and FIG. 3 is a schematic view of a conventional technique in which a chip is powered on. A coordinate map of different power supplies climbing over time. A coordinate map of different power supplies climbing over time. The different power supplies are the south bridge and the north bridge on the motherboard. Figure 4 is the timing control of the creation. Figure 5 is the timing diagram of the preferred timing of the circuit::::the circuit diagram of the known method. 】 First voltage divider circuit 10