M302830 八、新型說明： 【新型所屬之技術領域】 本創作係有關於一種功率轉換器，特別是關於一種功率轉換器之控制電路。 【先前技術】 按，現今功率轉換器已廣泛運用於提供調整之輸出電源。基於安全性之考 量，功率轉換器之一次側與二次側必須隔離，所以功率轉換器通常設置有一變 壓器用於提供隔離以及轉移能量。請參閱第一圖，係為習用之功率轉換器的電 路圖。如圖所示，習用之功率轉換器設置有一變壓器10，其包含有一一次側繞 •組NP、一一次側繞組Ns與一辅助繞組naux，一次側繞組np分別耦接一輸入電 壓Vin與一開關20。開關20導通期間，變壓器1〇之一次側將儲存能量，一旦 開關20截止時，變壓器10將釋放一次側之能量至變壓器1〇之二次側並進而轉 •移能量至功率轉換器之輸出端。其中，_ 2〇為—功率電晶體或—功率金屬氧 ，化半 V體場效電晶體（Metal Oxide Semiconductor Field Effect Tramistoi·， MOSFET)。 -電流感啦阻2卜其串聯於開關2〇與接地端，用於_變壓器1〇之切 換電流而產生-電流訊號Vs，以提供—控制器25進行切換控制。控制器25， _其具有-電壓侧端DET、-電流制端vs與—輸出端〇υτ，電壓偵測端 與電流感咖vs分顺接Mi| 1G和電流制電阻2卜祕在輸出端⑽ 產生一控制訊號Vg，以控制開關2〇導通與截止並且調整功率轉換器之輸出。 控，器25更包含有一補償端c〇M與一接地端圓，補償端㈣耦接^償 電今24。接地端GND轉接至接地端。變壓器1〇之二次側繞組&之一端係輕接 的端’整流器15之另一端與二次側繞組乂之另一端之間祕有 、'谓截止日守，輔助繞組Naux即會產生-返馳電壓(flyback voltage ) F，其與功率轉換器之輪出電壓v〇相對應，因此，返驰電壓％可被運用於回 又功率轉換$之輸出電壓％。恤场h dw·处吻所提出之美國專利第 6 M302830M302830 VIII. New Description: [New Technology Field] This creation is about a power converter, especially a control circuit for a power converter. [Prior Art] Press, today's power converters have been widely used to provide regulated output power. For safety reasons, the primary and secondary sides of the power converter must be isolated, so the power converter is typically equipped with a transformer to provide isolation and transfer energy. Please refer to the first figure for a circuit diagram of a conventional power converter. As shown in the figure, a conventional power converter is provided with a transformer 10 including a primary side winding group NP, a primary side winding Ns and an auxiliary winding naux, and the primary side winding np is coupled to an input voltage Vin and a respectively. Switch 20. During the conduction of the switch 20, the primary side of the transformer 1 will store energy. Once the switch 20 is turned off, the transformer 10 will release the energy of the primary side to the secondary side of the transformer 1 and further transfer the energy to the output of the power converter. . Among them, _ 2〇 is a power transistor or a power metal oxide, and a metal Oxide Semiconductor Field Effect Tramistoi (MOSFET). - The current sense resistor 2 is connected in series to the switch 2 〇 and the ground terminal for the switching current of the _ transformer 1 产生 to generate a current signal Vs to provide - the controller 25 performs switching control. The controller 25, _ has a voltage side terminal DET, a current system terminal vs. an output terminal 〇υτ, a voltage detecting terminal and a current sensing coffee vs. a subsequent Mi| 1G and a current resistor 2 at the output end (10) A control signal Vg is generated to control the switch 2 〇 on and off and adjust the output of the power converter. The controller 25 further includes a compensation terminal c〇M and a ground terminal circle, and the compensation terminal (4) is coupled to the power supply 24 . Ground GND is transferred to ground. The secondary winding of the transformer 1〇& one end of the lightly connected end is connected to the other end of the rectifier 15 and the other end of the secondary winding 秘, and the auxiliary winding Naux is generated. The flyback voltage F, which corresponds to the turn-off voltage v〇 of the power converter, therefore, the flyback voltage % can be applied to the output voltage % of the power conversion. U.S. Patent No. 6 M302830
I5 rt ：^eCtlf1^^ P〇Wer Supply with Multi-Channel Flyback==° ^，反·嶋_編法精準量測 返驰紐Vk缺點，_是在神魏胁輕貞餘態下。 功率轉換器之變壓器1G的放電時間&可表示為如下： VlN 、 WNS TDS =(I5 rt :^eCtlf1^^ P〇Wer Supply with Multi-Channel Flyback==° ^,Reverse·嶋_Compiled Accurate Measurements The disadvantages of returning to New Zealand Vk are _ in the state of Shen Wei. The discharge time & of the transformer 1G of the power converter can be expressed as follows: VlN, WNS TDS = (
Vo + Vd WnpVo + Vd Wnp
:T〇N (1) 其中，VlN為功率轉換器之輸入電壓；Wnp與Wns分別為變壓器i〇之一次側繞 組叫與二次側繞組叫的繞組隨；％為整流器ls之順向偏壓的壓降；TOR為 控制訊號V〇之一導通時間。 上述之返桃電壓VF，其透過-電阻22傳送至控制器25之電壓偵測端娜 所以控 25會產生，懸Vdet，制賭㈣Μ之糖_卿侧 返驰電壓VF，但是因為-寄生電容23_於電阻22，而會引起—低通遽波特 性，導致返驰電壓VF會被過渡。此外，功率轉換器於輕負載狀態 訊號VG之導通時間T0N，依據方程式⑴得知亦會縮短返驰電壓％之放= 間TDS，如此會造成侧電壓vDET如第二圖所示發生波形失真之情形 制器25會偵測到低電壓之返馳電壓vF。 1 ^ 因此，本創作基於前述問題提出一種功率轉換器之控制電路，以可提高偵測 返馳電壓之精確度以可確實調整功率轉換器之輸出。 、 【新型内容】 本創作之主要目的，在於提供—種功率轉換器之控制電路，其藉由偵測電路 產生偏壓訊號，用以提尚偵測返馳電壓之精確度與防止波形失真，以達到 電路可在功率讎ϋ於輕貞餘態下精確制魏H之觀之目的。 本創作之另-目的，麵提供—獅样絲之控觀路，其藉由切換電路 依據控制訊號而產生消隱訊號，以確保控制訊號被導通時之最低導通時門如 此可確保返驰電壓之最小脈波寬度，以達容易偵測返馳電壓之目的。 7 M302830 - 賴作力率轉換D°之控制電路’其用於彳貞測功率轉換器之-變壓器之返驰 電壓’以及調整功率轉換器之輸出。控制電路包含有—開關與—控彻，開關 雛變壓《歸切換懸器，以從變壓器之—次側轉移能量至變壓器之二次 側。控制器包含有-偵測電路、一切換電路與一調整電路，侧電路雛變壓 益，用於偵;則變壓器之返驰電壓，以依據返驰電壓產生一第一訊號與一第二訊 说’第-减與功率轉換器之輸出有關，第二訊號係表示變壓器之放電時間。 切換電路用於依據第-訊號產生一控制訊號，以控制開關之切換並且調整功率 鲁轉換器之輸出。 猶電路，其依據第二訊號之脈波寬度，產生一調整訊號，债測電路依據 ，凋整减產生-偏壓訊號’並傳送至_電路之一電壓偏測端，以助於偵測 “返馳賴並戦波形失真。此外，切換電路依據控制纖產生—消隱訊號，一 旦控制訊麵導贿，舰訊號可確健伽叙最小導猶間，此最小導通 日守間可確保返馳電壓之最小脈波寬度，如此即可便於偵測返馳電壓。 φ 茲為使貴審查委員對本創作之結構特徵及所達成之功效更有進一步之瞭 解與㊂忍識’謹佐以較佳之實施例圖及配合詳細之說明，說明如後·· 【實施方式】 本創作之功率轉換器的控制電路包含有開關與控制器，控制器產生一控制 訊遽’以控制所耦接之開關進而切換功率轉換器之變壓器。請參閱第三圖，係 為本創作之一較佳實施例之控制器的方塊圖。如圖所示，本創作之控制器包含 有一切換電路30、一偵測電路50與一調整電路55。偵測電路50，其經由電壤 偵側端DET耦接變壓器1〇而偵側變壓器1〇之返馳電壓Vf，以依據返馳電髮 Vf產生一第一訊號VFB與一第二訊號SDS並分別傳送至控制器之補償端COM與 調整電路55。由於返驰電壓VF與功率轉換器之輸出電壓V〇相對應，所以第〜 8 M302830 -訊號Vfb亦與功率轉換器之輸出電壓v〇相對應，而第二訊號Sds則表示變壓器 10之放電時間TDS。切換電路3〇，其係依據第一訊號Vfb而產生控制訊號Vg， 並傳达至輸出端OUT，以用於控制開關20與調整功率轉換器之輸出，另外，切 換電路30更輕接電_測端vs，以接收電流訊號％而產生控制訊號。調 正電路55其祕债測電路5〇而依據第二訊號&產生一調整訊號匕並傳送至 偵測電路50。 月多閱第四圖’係為本創作之一較佳實施例之切換電路的電路圖。如圖所 不’本創狀切換電路3G包含_振轉路3卜㈣產生職性之_脈波訊號 PLS ’其經由-反相器33傳送至一第一正反器％，以導通控制訊號％。反相器 33之一輸入端與一輸出端分別連接振盤電路31之一輸出端和第一正反器％之 一時脈輸入端’第一正反器32之一輸出端連接一及閘34之一輸入端，及閘34 之另-輸入端連接反相器33之輸出端，及閘34之一輸出端產生控制訊號％並 ’傳輸至輸出端OUT。及閘34透過反相器33依據振盪電路31之脈波訊號pLS， • 讓控制訊號VG具有最大導通時間。 -第-比較ϋ 36 ’ 運用於_旦電流訊號％高於第_訊號I時，透過一 反及閘35 t置第-正反器32。第-比較器36之一正輸入端與一負輸入端分別 接收電流訊號Vs與第-訊號vFB，第一比較器36之一輸出端則搞接反及閘％ 之一輸入端，反及閘35之另一輸入端耦接一消隱電路（blan]dng circuit) 4〇之 -輸出端out，用以接收-消隱訊號Vblk，反及閘35之一輸出端織第一正 反态32之一重置輸入：^，用以重置第一正反器％，消隱電路4〇之一輸入端取 轉接及閘34之輸出端，用以接收控制訊號Vg。 請參閱第五圖，係為本創作之一較佳實施例之消隱電路的電路圖。本創作 之消隱電路40為一脈波產生電路，其包含有一反相器42，反相器42之一輸入 端為脈波產生電路之輸入端IN，用以接收一輸入訊號，其為控制訊號VG，反相 器42之一輸出端麵接一電晶體46之閘極，如此脈波產生電路之輸入端取則經 由反相器42耦接至電晶體46之閘極，當脈波產生電路所接收之輸入訊號導通 時，將驅使電晶體46關閉，此外電晶體46之源極耦接至接地端。一電流源41， 其耗接於電晶體46之;及極與一供應電壓vcc之間。一電容47，其搞接於電流源 9 M302830 -41和接地端之間。一旦電晶體46關閉時，電流源41即對電容47充電。 另外，電容47更透過一反相器43連接一反及閘45，反相器43之一輸入端 耦接電容47，反相器43之一輸出端則耦接反及閘45之一輸入端，反及閘45之 另一輸入端耦接脈波產生電路之輸入端IN，用以接收輸入訊號，反及閘45之一 輸出端為脈波產生電路之輸出端ουτ，用以輸出一脈波訊號，其為該消隱訊號:T〇N (1) where VlN is the input voltage of the power converter; Wnp and Wns are respectively the primary winding of the transformer i〇 and the winding called the secondary winding; % is the forward bias of the rectifier ls The voltage drop; TOR is the conduction time of one of the control signals V〇. The above-mentioned returning voltage VF is transmitted to the voltage detecting end of the controller 25 through the resistor 22, so that the control 25 will generate, suspend Vdet, and gambling (four) Μ sugar _ qing side return voltage VF, but because of - parasitic capacitance 23_ is in the resistor 22, which causes a low-pass chopping characteristic, which causes the flyback voltage VF to be transitioned. In addition, the power converter is in the light-on state signal VG on-time T0N, according to equation (1), it is also known that the flyback voltage % is reduced by the interval TDS, which causes the side voltage vDET to be waveform distortion as shown in the second figure. The situation controller 25 detects the low voltage flyback voltage vF. 1 ^ Therefore, this creation proposes a control circuit for the power converter based on the aforementioned problem, so as to improve the accuracy of detecting the flyback voltage to adjust the output of the power converter. [New content] The main purpose of this creation is to provide a control circuit for the power converter, which generates a bias signal by the detection circuit to improve the accuracy of detecting the flyback voltage and prevent waveform distortion. In order to achieve the purpose of the circuit, the power can be accurately determined in the light state. The other purpose of this creation is to provide a controlled view of the lion-like wire, which generates a blanking signal by switching the circuit according to the control signal to ensure that the minimum conduction time when the control signal is turned on ensures the flyback voltage. The minimum pulse width is for the purpose of easily detecting the flyback voltage. 7 M302830 - The control circuit for the D rate conversion D° is used to measure the flyback voltage of the power converter - and to adjust the output of the power converter. The control circuit includes - switch and - control, and the switch is switched to "switch the suspension to transfer energy from the secondary side of the transformer to the secondary side of the transformer. The controller includes a detection circuit, a switching circuit and an adjustment circuit, and the side circuit is used to detect the voltage; the return voltage of the transformer is used to generate a first signal and a second signal according to the flyback voltage. It is said that the 'first-subtraction is related to the output of the power converter, and the second signal is the discharge time of the transformer. The switching circuit is configured to generate a control signal according to the first signal to control the switching of the switch and adjust the output of the power converter. The circuit of jujube generates an adjustment signal according to the pulse width of the second signal, and the debt measurement circuit is based on the subtraction of the -bias signal and transmitted to one of the voltage bias terminals of the circuit to help detect In addition, the switching circuit generates a blanking signal according to the control fiber. Once the control plane is bribed, the ship signal can be surely symmetrical. The minimum conduction day can ensure the return. The minimum pulse width of the voltage, so that it is easy to detect the flyback voltage. φ In order to enable the review board to have a better understanding of the structural characteristics and the achieved effects of the creation and the three tolerances, The example diagram and the detailed description are as follows. [Embodiment] The control circuit of the power converter of the present invention includes a switch and a controller, and the controller generates a control signal to control the coupled switch and switch. A transformer of a power converter. Please refer to the third figure, which is a block diagram of a controller of a preferred embodiment of the present invention. As shown in the figure, the controller of the present invention includes a switching circuit 30, a detective The detecting circuit 50 and the adjusting circuit 55. The detecting circuit 50 is coupled to the transformer 1 via the electromagnetic detecting side end DET and detects the flyback voltage Vf of the transformer 1 to generate a first signal according to the flyback Vf. VFB and a second signal SDS are respectively transmitted to the compensation terminal COM of the controller and the adjustment circuit 55. Since the flyback voltage VF corresponds to the output voltage V〇 of the power converter, the ～8 M302830 - the signal Vfb is also the power The output voltage v 转换器 of the converter corresponds to the second signal Sds, which represents the discharge time TDS of the transformer 10. The switching circuit 3 产生 generates a control signal Vg according to the first signal Vfb and transmits it to the output terminal OUT. For controlling the switch 20 and adjusting the output of the power converter, in addition, the switching circuit 30 is lightly connected to the measuring terminal vs. to receive the current signal % to generate the control signal. The correcting circuit 55 has its secret measuring circuit 5 An adjustment signal is generated according to the second signal & and transmitted to the detection circuit 50. The fourth picture of the month is a circuit diagram of the switching circuit of a preferred embodiment of the present invention. Switching circuit 3G includes _ vibration 3 (4) generating the job _ pulse signal PLS 'transmitted to a first flip-flop % via the inverter 33 to turn on the control signal %. One of the input terminals of the inverter 33 is connected to an output terminal One output of the vibrating plate circuit 31 and one of the first flip-flops % of the clock input terminal 'one of the first flip-flops 32 are connected to one of the input terminals of the gate 34, and the other input terminal of the gate 34 is connected. The output of the inverter 33 and the output of one of the gates 34 generate a control signal % and 'transmitted to the output terminal OUT. And the gate 34 passes through the inverter 33 according to the pulse signal pLS of the oscillation circuit 31, • the control signal VG It has the maximum on-time. - The first-comparison ϋ 36 ' is used when the current signal % is higher than the first signal I, and the first-reverse device 32 is placed through a reverse gate 35 t. The positive input terminal and the negative input terminal respectively receive the current signal Vs and the first signal vFB, and one output of the first comparator 36 is connected to one of the input terminals of the gate and the gate. The other input end of the 35 is coupled to a blanking circuit (blan]dng circuit). The output terminal out is used to receive the blanking signal Vblk, and the output of one of the gates 35 is woven into the first positive and negative state 32. One of the reset inputs: ^ is used to reset the first flip-flop %, and one of the input terminals of the blanking circuit 4 is taken as an output of the switch and the gate 34 for receiving the control signal Vg. Please refer to the fifth figure, which is a circuit diagram of a blanking circuit according to a preferred embodiment of the present invention. The blanking circuit 40 of the present invention is a pulse wave generating circuit, which comprises an inverter 42. One input end of the inverter 42 is an input terminal IN of the pulse wave generating circuit for receiving an input signal, which is a control. The output end of one of the inverters 42 is connected to the gate of a transistor 46. The input end of the pulse wave generating circuit is coupled to the gate of the transistor 46 via the inverter 42 when the pulse wave is generated. When the input signal received by the circuit is turned on, the transistor 46 is driven to be turned off, and the source of the transistor 46 is coupled to the ground. A current source 41 is consumed between the transistor 46 and a supply voltage vcc. A capacitor 47 is coupled between the current source 9 M302830-41 and the ground. Once the transistor 46 is turned off, the current source 41 charges the capacitor 47. In addition, the capacitor 47 is further connected to a reverse gate 45 through an inverter 43. One input end of the inverter 43 is coupled to the capacitor 47, and one output of the inverter 43 is coupled to one input terminal of the opposite gate 45. The other input end of the anti-gate 45 is coupled to the input terminal IN of the pulse wave generating circuit for receiving the input signal, and the output end of the gate 45 is the output end of the pulse wave generating circuit ουτ for outputting a pulse Wave signal, which is the blank signal
VblK°電流源41之電流與電容47之電容值係決定脈波訊號之脈波寬度。由上 述說明可知，消隱電路40在控制訊號Vg導通時，進而產生消隱訊號Vblk。一 旦控制訊號VG被導通時，消隱訊號vBLK便可確保控制訊號Vg具有一最小導通 時間’控制訊號VG之最小導通時間可確保返驰電壓％之最小脈波寬度，以可 矚容易偵測返馳電壓vF。 4參閱第六圖，係為本創作之一較佳實施例之偵測電路的電路圖。如圖所 不^本創作之偵測電路50包含有一誤差放大器67、一波形偵測電路1〇〇以及一 偏壓電路60。偏壓電路60 i生-偏壓訊號Vb並傳輸至债側電路5〇之電壓摘測 .端DET，用以偵測返驰電壓Vf以及避免偵測電壓Vdet之波形失真。其中，偏 壓汛號VB與調整訊號IB成比例。偏壓電路6〇包含一第一電晶體65、一第二電 曰曰體=1、一電流源62與一第一電阻63。第一電晶體65之源極耦接偵測電路50 =壓制端DET，用以產生偏壓概Vb，電晶體65之錄餘接供應 _包壓Vcc ’第一電晶體65之閘極則麵接第一電阻63。第一電阻63接收調整訊 號^用於產生-偏壓電壓於第一電晶體65之閘極，所以偏壓訊號％與偏壓 電[成比例’亦即與調整訊號Ιβ成比例。為了補償第一電晶體65之閘極至源極 ^間的，壓，第二電晶體61與第一電阻63串聯。第二電晶體61之間極與沒極 白輕接第-電阻63，第二電晶體61之源極則雛至接地端。電流源62，其連 接供應電壓Vcc、第二電晶體61之閘極與汲極，以供給偏壓予第二電晶體6卜 為了偵測返驰電壓vF，波形_電路100輕接電壓_端DET，以感測返 馳電壓vF並依據返馳電壓Vf產生一取樣訊號Va與第二訊號&。誤差放大器 67其-正輸入端接收-參考電壓V·，誤差放大器π之一負輸入端則柄接波 :偵測電路腦而接收取樣訊號Va，誤差放大器67依據取樣訊號I而在一輸 出端輸出第-訊號vFB。誤差放大器67為_轉導放A|| (加_相祕 M302830 山P )其中誤差放大器67之輸出端更耦接至控制器之補償端COM，補償 端COM如第一圖所示，係輕接有補償電容％以透過補償端⑺μ提供頻率補 償至誤差放大器67。 、 ❼閱第七圖’係為本創作之—較佳實施例之波形伽彳電賴電路圖。如 圖所示，本創作之波形偵測電路⑽包含有一第一取樣開關151，其一端織偵 測包路=0之電壓偵測端DET，用以取樣返馳電壓％。一第一取樣電容⑹，其 據在第-取樣開關⑸之另一端與接地端之間，以箝住第一取樣開關151 ς 取樣之訊號。-第二取樣關15G，其_於第—取樣電容161與—第二取樣電 容160之間二以週期性的取樣第一取樣電容161所箝住之訊號至第二取樣電容 I湖。其中’第二取樣開關150受控於振盛電路31之週雛的脈波訊號pLs， 而第一取樣開關151則受控於控制訊號vG。 控制减vG係經-反相器1G2哺送至—脈波產生電路⑽。反相器1〇2 之-輸入端接收控制訊號Vg，反相器脱之—輸出端職接脈波產生電路14〇 之-，入端IN，脈波產生電路14G之—輸出端⑽係產生—脈波訊號以經由一 反相為105控制第-取樣開關1M，亦即第一取樣開g 151在控制訊號％截止 時取樣返驰電壓VF至第-取樣電容16卜如此即可依據返馳電壓Vp在第二取 樣電容160產生取樣訊號γΑ。 -第二正反器159’其-時脈輸人端_反相旨1〇2之輸出端，用於經由反 相器102依據控制訊號Vg，以在一輸出端產生第二訊號&，控制訊號％用於 在截止時，導通第二訊號SDS…第二比較器155，其—正輸人端耦接侧電路 50之電壓偵測端DET，第二比較器155之—負輸人端則接收—臨界電壓Vth， 第二比較器155用於依據臨界電壓Vth比較返馳電壓％而產生一重置訊號，重 置訊號用於經由-或閘i56與-及閘158重置第二正反器159，所以一旦返驰電 壓VF低於臨界電壓v™日夺，第二正反器159輸出之第二峨&將被截止。上 述之第二比較器155之-輸出端係輕接至或閘156之—輸人端，或閘156之另 -輸入端則接收控制訊號VG，或閘156之-輸出端係減及閘158之一輸入端， 及間⑸之另一輸入端減一反相器157之—輸出端，反相_ π之一輸入端 接收脈波峨PLS，如此即可傳輸脈波峨PLS至及閘158，及閘158之一輸 11 M302830 出端f妾第^L反器159之-重置輸人端，用以重置第二正反器159。 -，二二，V圖’係為本創作之—較佳實施例之調整電路的電路圖。如圖所 不第一取^周整電路55包含有一充電開關81，其一第一端細共應電壓Vcc。 =其耦接在充電開關81之一第二端與接地端之間，用以對第 ㈣v电所电達到一設定值，例如供應電壓Vcc。充電開關81受控於控制 Γ 轉電容84在蝴喊％導通__先奴。一放電開 Γ端，第三取樣電容84，放電_82受控制於第二訊號、， :取樣電谷84在第二訊號Sds導通時放電。因為放制關82之一第 疒係广放電驗源83串接’所以第三取樣電容84係藉由放電電流源83放 =’ 一第二取樣關87，其_在第三取樣電容84和_第四取樣電容89之間， 四:===8。7鱗脈波喊PLS觀㈣鄉三轉餘84取觀號至第 電壓對喊電路8〇，其包含有一放大器86、 曰 =與::電流鏡日’ _據第四取樣電容89之訊號產生調整訊號iB。 四&样·^電阳體91與—第五電晶體92。放大器86 ’其—正輸人端雛第 山取樣=89。第二雜85，其兩端分職概大器％之-負輸人端與接地 放大H 86之-輸出端係输第三電晶體9()之閘極，用以依據第四取樣電 ς89之訊號與第二電阻85之電阻值，產生―第―電流^第—電流^產生於 弟二電晶體90之汲極，第三電晶體9〇之源極耦接於放大器％之一負輸入端。 電流鏡’其㈣依魏—電流l9。產生調整訊私，所關整城ΐβ可說是 ^據控制訊號VG之脈波寬度所產生。此外，為了節省電源，一第六電晶體奶 妾電概鏡以在控制賴^ vG導通時截止調整訊號L。電晶體9丨、 f源極皆祕供應電壓^，電晶體.92之閘極與電晶體9G、9卜93之汲極 馬接在-起，第五電晶體92之汲極係產生健碱。第六電晶體％之閘極 接▲或閘95之輸出端，或閘95之一第一輸入端與一第二輸入端分別接收 二制吼號vG#第三域Sds。如此可知，調整喊Ιβ亦與第二訊號&相關， 即第二=號sDS所表示之變壓器1G之放電時間齡_整訊號Ib則增加，此 由上述第六圖之制可知，偏壓訊號％倾調整峨IB成正比例，而調整訊 12 M302830 "B/、第汛號8呢呈反比例，所以偏壓訊號vB亦與變壓器l〇之放電時間成 反比=也就心兄當變壓器10之放電時間減少時偏壓訊號Vb則增加。 曰口月參閱第九圖，係為本創作之功率轉換器於輕負載狀態下所產生之翻電 堅DET的波开少圖。如圖所示，偏壓訊號Vb係加於電壓偵測端，偵測電壓 Vdet可表示為如下： (2) (3)The current value of the VblK° current source 41 and the capacitance of the capacitor 47 determine the pulse width of the pulse signal. As can be seen from the above description, the blanking circuit 40 generates the blanking signal Vblk when the control signal Vg is turned on. Once the control signal VG is turned on, the blanking signal vBLK ensures that the control signal Vg has a minimum on-time. The minimum on-time of the control signal VG ensures the minimum pulse width of the flyback voltage %, so that it can be easily detected. The voltage is vF. 4 is a circuit diagram of a detection circuit of a preferred embodiment of the present invention. The detection circuit 50 of the present invention includes an error amplifier 67, a waveform detecting circuit 1A, and a bias circuit 60. The bias circuit 60i generates a voltage-bias signal Vb and transmits it to the voltage side of the debt side circuit 5〇. The terminal DET detects the flyback voltage Vf and avoids waveform distortion of the detection voltage Vdet. Among them, the bias voltage VB is proportional to the adjustment signal IB. The bias circuit 6A includes a first transistor 65, a second transistor=1, a current source 62 and a first resistor 63. The source of the first transistor 65 is coupled to the detecting circuit 50 = the pressing end DET for generating the bias voltage Vb, and the recording of the transistor 65 is supplied to the package Vcc 'the gate of the first transistor 65 The first resistor 63 is connected. The first resistor 63 receives the adjustment signal for generating a bias voltage to the gate of the first transistor 65, so the bias signal % is proportional to the bias voltage, i.e., proportional to the adjustment signal Ιβ. In order to compensate for the voltage between the gate and the source of the first transistor 65, the second transistor 61 is connected in series with the first resistor 63. The second transistor 61 is lightly connected to the first-resistor 63, and the source of the second transistor 61 is grounded to the ground. The current source 62 is connected to the supply voltage Vcc, the gate and the drain of the second transistor 61 to supply a bias voltage to the second transistor 6 for detecting the flyback voltage vF, and the waveform_circuit 100 is connected to the voltage _ terminal The DET senses the flyback voltage vF and generates a sample signal Va and a second signal & according to the flyback voltage Vf. The error amplifier 67 has a positive input terminal receiving a reference voltage V·, and a negative input terminal of the error amplifier π is connected to the wave: the detection circuit brain receives the sampling signal Va, and the error amplifier 67 is based on the sampling signal I at an output end. The first signal vFB is output. The error amplifier 67 is _transfer A|| (plus _ phase secret M302830 mountain P), wherein the output of the error amplifier 67 is more coupled to the compensating end COM of the controller, and the compensating end COM is as shown in the first figure. A compensation capacitor % is connected to provide frequency compensation to the error amplifier 67 through the compensation terminal (7) μ. The seventh figure is a schematic diagram of a waveform gamma electric circuit of the preferred embodiment. As shown in the figure, the waveform detecting circuit (10) of the present invention comprises a first sampling switch 151, and one end of the voltage detecting end DET of the detection packet = 0 for sampling the flyback voltage %. A first sampling capacitor (6) is provided between the other end of the first sampling switch (5) and the ground to clamp the signal sampled by the first sampling switch 151. - a second sampling off 15G, between the first sampling capacitor 161 and the second sampling capacitor 160, to periodically sample the signal clamped by the first sampling capacitor 161 to the second sampling capacitor I lake. Wherein the second sampling switch 150 is controlled by the pulse signal pLs of the periphery of the oscillation circuit 31, and the first sampling switch 151 is controlled by the control signal vG. The control minus vG is supplied to the pulse wave generating circuit (10) via the inverter 1G2. The input terminal of the inverter 1〇2 receives the control signal Vg, and the inverter is disconnected—the output terminal is connected to the pulse wave generating circuit 14〇, the input terminal IN, and the output terminal (10) of the pulse wave generating circuit 14G is generated. - the pulse signal is controlled by the first sampling switch 1M via an inversion 105, that is, the first sampling opening g 151 samples the flyback voltage VF to the first sampling capacitor 16 when the control signal % is cut off. The voltage Vp produces a sampled signal γΑ at the second sampling capacitor 160. - the output of the second flip-flop 159', the clock-input terminal _-inverted, is used to generate a second signal & at an output via the inverter 102 according to the control signal Vg, The control signal % is used to turn on the second signal SDS...the second comparator 155, which is connected to the voltage detecting terminal DET of the side circuit 50 and the negative input terminal of the second comparator 155. Then, the threshold voltage Vth is received, and the second comparator 155 is configured to generate a reset signal according to the threshold voltage Vth to compare the flyback voltage %, and the reset signal is used to reset the second positive via the - or gate i56 and - and gate 158. The inverter 159, so that once the flyback voltage VF is lower than the threshold voltage vTM, the second 峨& output of the second flip-flop 159 will be cut off. The output of the second comparator 155 is lightly connected to the input terminal of the OR gate 156, or the other input terminal of the gate 156 receives the control signal VG, or the output of the gate 156 is reduced by the gate 158. One input terminal, and the other input terminal of (5) are subtracted from the output terminal of the inverter 157, and one of the inverting_π input terminals receives the pulse wave 峨PLS, so that the pulse wave 峨PLS to the gate 158 can be transmitted. And one of the gates 158 loses 11 M302830, the end of the 妾 L 反 反 - - - 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置 重置-, 22, V diagram is a circuit diagram of the adjustment circuit of the preferred embodiment. As shown in the figure, the first complete circuit 55 includes a charging switch 81, and a first end thereof has a common voltage Vcc. = It is coupled between the second end of one of the charging switches 81 and the ground to supply a set value, for example, a supply voltage Vcc, to the fourth (fourth). The charge switch 81 is controlled by the control Γ turn capacitor 84 in the squeak % conduction __ sin slave. A discharge opening terminal, a third sampling capacitor 84, and a discharge signal 82 are controlled by the second signal, and the sampling power valley 84 is discharged when the second signal Sds is turned on. Since one of the discharges 82 is connected to the wide discharge source 83 in series, the third sampling capacitor 84 is discharged by the discharge current source 83 = 'a second sampling off 87, _ at the third sampling capacitor 84 and _ between the fourth sampling capacitor 89, four: ===8. 7 scale pulse called PLS view (four) township three turn 84 take the view to the voltage on the shout circuit 8〇, which contains an amplifier 86, 曰 = and :: Current Mirror Day' _ The adjustment signal iB is generated based on the signal of the fourth sampling capacitor 89. Four & electro-opposite body 91 and - fifth transistor 92. The amplifier 86's - is being input to the human side and sampling = 89. The second miscellaneous 85, the two ends of which are divided into large and large devices - the negative input terminal and the grounding amplification H 86 - the output terminal is connected to the third transistor 9 () gate, according to the fourth sampling electrode 89 The signal and the resistance value of the second resistor 85 generate a "first current" - the current is generated in the drain of the second transistor 90, and the source of the third transistor 9 is coupled to one of the negative inputs of the amplifier end. The current mirror '(4) is Wei-current l9. The adjustment of the private property is generated, and the whole city ΐβ can be said to be generated according to the pulse width of the control signal VG. In addition, in order to save power, a sixth transistor milk pan mirror is used to turn off the adjustment signal L when the control is turned on. The transistor 9 丨, f source is the secret supply voltage ^, the gate of the transistor .92 is connected with the transistor 9G, 9 卜 93, and the fifth transistor 92 is the base. . The gate of the sixth transistor is connected to the output of the ▲ or gate 95, or the first input terminal and the second input terminal of the gate 95 respectively receive the second nickname vG# third domain Sds. As can be seen, the adjustment of the Ιβ is also related to the second signal & the second generation sDS represents the discharge time of the transformer 1G _ the whole signal Ib is increased, which is known from the system of the sixth figure, the bias signal % tilt adjustment 峨 IB is proportional, and adjustment signal 12 M302830 " B /, 汛 8 8 is inversely proportional, so the bias signal vB is also inversely proportional to the discharge time of the transformer l 也就 = is the heart of the transformer 10 The bias signal Vb increases as the discharge time decreases. See the ninth picture of the mouth of the mouth, which is the wave-breaking diagram of the power-on DET generated by the power converter of the present invention under light load conditions. As shown in the figure, the bias signal Vb is applied to the voltage detection terminal, and the detection voltage Vdet can be expressed as follows: (2) (3)
Vdet = VFx(i.eRxC)H_VB 依據方程式（2)，t可表示為如下 t = RxCx|n(--VF__ VF. VDET +VB； 其中，^為電阻22之電阻值；C為寄生電容23之電容值；t為偵測電壓％ 充，至等於返馳電壓VF之週期時間。本創作藉由增加偏壓訊號％，而減少偵測 電壓:而之上升時間，所以控制器可容易侧到返驰電壓％。 抑了丁、上所述’本創作功率轉換ϋ之控制電路，其用於_功率轉換器之變壓 Γ 電壓卩及调整功率轉換器之輸出。本創作之控制電路包含有開關與 控，Γ :控制11包括有切換電路與侧電路，關餘接於變壓11而用於切換 顏二制電路係祕髓11，以侧顏11之现雜而絲返驰電壓產 生第-訊號；場電路則__電路，以依據第—訊號產生控制訊號，控制 訊號用於控制開關而切換變壓器，以調整功率轉換器之輸出。此外，彳貞測;路 更產生偏壓4號’以助則貞測返馳電壓，如此可提高伽彳返馳電壓之準確性且 可確實調整功率轉換器之輸出。 、故本創作貫為-具有新穎性、進步性及可供產業上利用者，應符合我國專 利法專利申請要件無疑，爰依法提出創作專利申請，祈釣局早曰賜 至感為禱。 准以上所述者’僅為本創作—較佳實施例而已，並制來限定本創作實施 之範圍故舉凡依本創作申請專利範圍所述之形狀、構造、特徵及精神所為之 均等變化與修飾，應包括於本_之帽範圍内。 13Vdet = VFx(i.eRxC)H_VB According to equation (2), t can be expressed as follows: t = RxCx|n(--VF__ VF. VDET +VB; where ^ is the resistance value of the resistor 22; C is the parasitic capacitance 23 The capacitance value; t is the detection voltage % charge to the cycle time equal to the flyback voltage VF. This creation reduces the detection voltage by increasing the bias signal %: and the rise time, so the controller can easily The flyback voltage is %. Suppressing the control circuit of the above-mentioned 'power conversion switch', which is used for the voltage transformer _ voltage converter and the output of the power converter. The control circuit of the present invention includes Switch and control, Γ: Control 11 includes a switching circuit and a side circuit, and the switch is connected to the transformer 11 for switching the secret system of the second system, and the voltage is generated by the side - signal; the field circuit is __ circuit, according to the first signal to generate the control signal, the control signal is used to control the switch and switch the transformer to adjust the output of the power converter. In addition, the test; the road is more biased 4 'Help to measure the flyback voltage, which can increase the gamma flyback voltage Accuracy and can indeed adjust the output of the power converter. Therefore, this creation is a novelty, progressive and available for industrial use. It should be in accordance with the patent application requirements of China's patent law. The Prayer and Fishing Bureau has given the feelings of prayer as early as possible. The above-mentioned persons are only for the purpose of this creation, the preferred embodiment, and the scope of the implementation of the creation is limited, so that the shape described in the patent application scope of the creation, Equivalent changes and modifications in structure, character and spirit should be included in the scope of this cap.