M3 02194 八、新型說明： 【新型所屬之技術領域】 本創作關於一種電源轉換器，且更具體地說，本創作關於一種切換式電源轉換器。 【先前技術】 電源轉換器廣泛用於提供穩定的輸出調節。為了安全起見，電源轉換器必須在其初級 侧與次級侧之間提供電氣隔離（galvanicisolation)。通常，變壓器可用來提供隔離和能量 轉移。第1圖繪示具有一變壓器10的一傳統電源轉換器。當一開關2〇導通時，能量儲 存在變壓器10中。當開關20截止時，能量將被釋放到電源轉換器的輪出端。一電阻器 • 21與開關20串聯連接，以感測變壓器1〇的切換電流，並產生用於切換控制的一電流信 號Vs。一控制器25耦接到變壓器10和電阻器21，以產生一控制信號Vg，以便控制開 關20的導通/截止，並調節電源轉換器的輸出。變壓器1〇包括一初級繞組^、一次級繞 組Ns和一輔助繞組Na。當開關20截止時，輔助繞組Na就會產生一反射電壓Vf，所述 ^ 反射電壓Vf與輸出電壓v〇相關。因此，反射電壓VF可用來反饋輪出電壓v〇。在美國 -專利第 4,302,803 號“Rectifier-Conve_ Power Supply with Multi-Channel Flyback Inverter” 中已揭示反射電壓控制技術。然而，此參照案的缺點是不能精確地測量反射電壓，尤其 是在輕載條件下。 第2圖繪示電源轉換器在輕載狀態下多個信號的電壓波形。變壓器的放電時間Tds可由 下式表示： 鲁 -/ Vin x Wns -M3 02194 VIII. New Description: [New Technical Field] This creation relates to a power converter, and more specifically, to a switched power converter. [Prior Art] Power converters are widely used to provide stable output regulation. For safety reasons, the power converter must provide electrical isolation between its primary and secondary sides. Typically, transformers can be used to provide isolation and energy transfer. FIG. 1 illustrates a conventional power converter having a transformer 10. When a switch 2 turns on, energy is stored in the transformer 10. When the switch 20 is turned off, energy is released to the wheel-out of the power converter. A resistor • 21 is connected in series with the switch 20 to sense the switching current of the transformer 1 , and generate a current signal Vs for switching control. A controller 25 is coupled to the transformer 10 and the resistor 21 to generate a control signal Vg for controlling the on/off of the switch 20 and regulating the output of the power converter. The transformer 1A includes a primary winding ^, a primary winding Ns and an auxiliary winding Na. When the switch 20 is turned off, the auxiliary winding Na generates a reflected voltage Vf which is related to the output voltage v〇. Therefore, the reflected voltage VF can be used to feedback the turn-off voltage v〇. Reflected voltage control techniques have been disclosed in U.S. Patent No. 4,302,803, "Rectifier-Conve_ Power Supply with Multi-Channel Flyback Inverter." However, the disadvantage of this reference is that the reflected voltage cannot be accurately measured, especially under light load conditions. Figure 2 shows the voltage waveform of multiple signals of the power converter under light load conditions. The discharge time Tds of the transformer can be expressed by the following formula: Lu - / Vin x Wns -
Tds=(v^)xw^xTon ................................... 其中，VIN是電源轉換器的輸入電壓，WNP和Wns分別是變壓器1〇的初級繞組 和次級繞組NS的匝數，VDS整流器15的順向電壓降，且T〇N是控制信號¥〇的導通時 間。在第1圖中，反射電壓VF透過一電阻器22耦接到一控制器2S，而在控制器中 產生用於檢測反射電壓的一電壓vDET。然而，一寄生電容器23和電阻器22會對於反射 電壓Vf產生低通濾波的效果。除了控制信號VG的導通時間t〇n和反射電壓Vf的放電 時間TDS在輕載狀態下會變得很短之外’第2圖中繪示了電壓乂班^的波形失真。因此， 將會檢測到較低的反射電壓。故本創作的主要目的乃是克服上述缺點。 M3 02194 【新型内容】 ，齡提供-種控制電路來檢測_變壓器的_反射電壓以調節電源轉換器。控制電 路=括-關和-控彻，其中„絲切換變㈣，並錢餘麵 =次級側蔽控制器包括-檢測電路、—切換電路和—調整電路。檢測電路_到變㈣ 來檢測變壓㈣反射電壓，並依據反射電壓而產生—反饋信號。切換電路用於產生一控 2號，並依據反饋信號而控制開關，並調節電源轉換器的輸出。調整電路更利用反饋 信號來產生調整信號。檢職路包括—偏壓電路，以產生输到檢測電路的輸入端的一 偏壓信號，胁幫助侧反射頓並社波敎真。生的偏壓錢與讎信號成比 例。除了切換電路外’遮沒電路依據控制信號而產生一遮沒信號。當控制信號啟用時， 遮沒信號確保控制錢的-最小導通時間。鋪信號的最小導通時間麵反射電壓的最 小脈衝寬度，其更有助於檢測反射電壓。 上述說明僅是本創作技術方案的減，為了能夠更清楚瞭解本創作的技術手段，並 可依照說明書的内容予以實施，町財創作的較佳實施舰配合關詳細說明如後。 【實施方式】 - 以下結合附圖及較佳實施例，對依據本創作提出的電源轉換器的控制電路之特徵及其功 效’詳細說明如後。 請參照第1圖，一電源轉換器的一控制電路包括一開關2❶和一控制器25。控制器 25產生一控制信號\^來控制用於切換變壓器1〇的切換。第3圖繪示本創作一實施例的 φ 控制器25的方塊圖。控制器25包括一切換電路30、一檢測電路50,和一調整電路55。 參照第1圖，將檢測電路50耦接到變壓器10,以檢測變壓器1〇的一反射電壓Vf，並根 據反射電壓¥!^產生一反饋信號VFB。切換電路30在控制器25的輪出端處產生控制信號 Vg ’並根據反饋信號Vfb而控制開關2〇並調節電源轉換器的輸出。調整電路55更因應 反饋信號VFB來產生一調整信號1B。 第4圖中繪示切換電路30，其利用振盪電路31來產生週期性的一脈衝信號PLS。 脈衝信號PLS耦接到正反器32，以啟用控制信號VG。正反器32的一輸出端連接到及閘 34的一輸入端。及閘34的另一輸入端經由反相器33耦接到脈衝信號PLS，以提供控制 信號Vg的最大導通時間。及閘34的輸出端於控制器25的輸出端out產生控制信號 VG。在一電流信號vs高於反饋信號Vfb時，利用一比較器36來禁用正反器32。比較器 36的一輸出端連接到及閘35的一輸入端。及閘35的另一輸入端連接到遮沒電路40的 M3 02194 -輸出端。控制信號％供應至遮沒電路4()的一輸入端。此外，及閘3s的—輸出端可用 來重置正反器32。 在第5圖中繪示本創作一實施例的遮沒電路4〇。當控制信號％啟用時，控制信號 VG可經由反相器42ffl以截止電晶體46。在電晶體46截止時，一電流源41就會開始對 一電谷器47充電。電容器47更經由一反相|| 43連接到一反及間45的一輸入端，而反 及閘45的另-輸入端輕接到控制信號％。因此，反及閘45的輸出端根據控制信號w 的啟用而產生-遮沒信號Vblk。電流源41的電流值和電容器47的電容值可決定遮沒信 號vBLK的脈衝寬度。當控制㈣Vg導通時，遮沒信號Vblk確保控制信號Vg的一最^ 導通時間。參照第1圖和第2目，控制信號vG的最小導通時間更確保反射電壓％的一 最小脈衝寬度，其有助於檢測反射電壓。 • 第6圖顯示根據本創作的一實施例的檢測電路5〇。檢測電路5〇包括一誤差放大器 67、-波形檢廳1GG和-偏壓電路。參照第3圖，偏壓電路於檢測電路50的輸入端 DET處產生_職錢％，其驗幫助侧反射錢，细贿止糕的波形失 真。所產生的偏壓信號VB與調整信號iB成比例。偏壓電路包括一電晶體6S，其一源極 ，端耦接到檢測電路so的輸入端DET，以產生偏壓信號VB。電阻器60用來接收調整信號 Ib，其用於在電晶體65的一閘極端處產生一偏壓電壓。因此，所產生的偏壓信號乂^與 偏壓電壓成比例。為了補償電晶體65閘極至源極的電壓，電晶體61與電阻器6〇串聯連 接。電晶體61的一閘極端和一汲極端連接到電阻器6〇。電晶體61的一源極端接地。此 外，電流源62係用來偏壓電晶體61。 為了檢測反射電壓VF，波形檢測器1〇〇耦接到輸入端DET來感測反射電壓\^，並 •根據反射電壓VF產生一取樣信號vA。具有參考信號VREF的誤差放大器67根據取樣信 號VA而產生反饋信號VFB。誤差放大器67係為一轉導(trail-conductance)放大器◊誤差放 大器67的一輸出端耦接到控制器25的COM端。參照第1圖，電容器24連接到COM 端，來為誤差放大器67提供頻率補償。 第7圖顯示本創作一實施例的波形檢測器1〇〇的電路示意圖。一電晶體14〇具有一 連接到一電流源105的一沒極端。一放大器102具有一正輸入端，其連接到檢測電路5〇 的輸入端DET，用於檢測反射電壓vF。放大器102的一輸出端耦接到電晶體140的一閘 極端。放大器102的一負輸入端連接到電晶體140的一源極端。電容器161連接到電晶 體140的一源極端。一開關151與電容器161並聯連接，用以週期性地將電容器161放 電。電容器160根據反射電壓VF而產生取樣信號VA。一開關150由脈衝信號PLS控制， 將電容器161上的電壓週期地取樣到電容器160上，以便將取樣信號vA保存在電容器 6 M302194 160 上。 第8圖顯示調整電路55的電路示意圖。一放大器8〇具有由一門檻電壓Vth供應的 正輸入端。一放大器81具有一耦接到反饋信號Vfb的正輸入端。放大器81的一負輸入 端連接到放大H 81的-輸出端，以形成_緩衝器…電晶體⑽祕到放大器⑽的一輸 出端，以便根據門檻電Μ vTH和反饋信號Vfb而產生一電流l9〇。一電阻器85從電晶體 90的-源極連接到放大器81的―輸出端。—電晶體91和一電晶體似形成一電流鏡， 以便根據電流！9〇產生調整信號lB。因此，可根據反饋信號％而產生調整健&，其中 可並根據反射電壓vF而產生反饋信號Vfb ◊ 第9隨示根據本辦_實施_電轉㈣在輕載下❹健魏舰形，其中 偏壓信號VB添加到輸入端DET。電壓vDET如下式表示·Tds=(v^)xw^xTon ....................................... Where VIN is power conversion The input voltages of the devices, WNP and Wns, are the number of turns of the primary winding and the secondary winding NS of the transformer 1 ,, the forward voltage drop of the VDS rectifier 15, and T 〇 N is the conduction time of the control signal ¥〇. In Fig. 1, the reflected voltage VF is coupled to a controller 2S through a resistor 22, and a voltage vDET for detecting the reflected voltage is generated in the controller. However, a parasitic capacitor 23 and resistor 22 produce a low pass filtering effect on the reflected voltage Vf. Except that the on-time t〇n of the control signal VG and the discharge time TDS of the reflected voltage Vf become short in the light load state, the waveform distortion of the voltage is shown in Fig. 2. Therefore, a lower reflected voltage will be detected. Therefore, the main purpose of this creation is to overcome the above shortcomings. M3 02194 [New content], the age provides a kind of control circuit to detect the _reflection voltage of the transformer to adjust the power converter. Control circuit = bracket-off and - control, where „wire switching change (4), and money margin = secondary side controller includes - detection circuit, - switching circuit and - adjustment circuit. Detection circuit _ to change (four) to detect Transforming (four) reflected voltage, and generating a feedback signal according to the reflected voltage. The switching circuit is used to generate a control No. 2, and controls the switch according to the feedback signal, and adjusts the output of the power converter. The adjustment circuit further generates a feedback signal to generate The signal is adjusted. The inspection path includes a bias circuit to generate a bias signal that is input to the input of the detection circuit. The help side reflects the reflection and the social wave is true. The generated bias voltage is proportional to the chirp signal. The external circuit of the switching circuit generates an obscuration signal according to the control signal. When the control signal is enabled, the obscuration signal ensures the control of the money-minimum conduction time. The minimum pulse width of the reflected voltage of the minimum on-time surface of the signal is It is more helpful to detect the reflected voltage. The above description is only a reduction of the technical solution of this creation, in order to be able to understand the technical means of the creation more clearly, and according to the specification The implementation of the preferred implementation of the company's creation of the company is described in detail below. [Embodiment] - The characteristics of the control circuit of the power converter according to the present invention and its characteristics are described below with reference to the accompanying drawings and preferred embodiments. The detailed description is as follows. Referring to Fig. 1, a control circuit of a power converter includes a switch 2A and a controller 25. The controller 25 generates a control signal to control the switching of the transformer 1〇. Fig. 3 is a block diagram showing the φ controller 25 of an embodiment of the present invention. The controller 25 includes a switching circuit 30, a detecting circuit 50, and an adjusting circuit 55. Referring to Fig. 1, the detecting circuit 50 is coupled. The transformer 10 is connected to detect a reflected voltage Vf of the transformer 1 ,, and generates a feedback signal VFB according to the reflected voltage. The switching circuit 30 generates a control signal Vg ' at the wheel end of the controller 25 and according to the feedback signal. Vfb controls the switch 2〇 and adjusts the output of the power converter. The adjustment circuit 55 further generates an adjustment signal 1B in response to the feedback signal VFB. In Fig. 4, the switching circuit 30 is illustrated, which uses the oscillation circuit 31 to generate the circumference. The pulse signal PLS is coupled to the flip-flop 32 to enable the control signal VG. An output of the flip-flop 32 is coupled to an input of the AND gate 34. Another input of the gate 34 The terminal is coupled to the pulse signal PLS via an inverter 33 to provide a maximum on-time of the control signal Vg. The output of the gate 34 produces a control signal VG at the output out of the controller 25. A current signal vs is higher than the feedback. In the case of the signal Vfb, the flip-flop 32 is disabled by a comparator 36. One output of the comparator 36 is connected to an input of the AND gate 35. The other input of the gate 35 is connected to the M3 02194 of the blanking circuit 40. - Output. The control signal % is supplied to an input of the blanking circuit 4 (). Further, the - output of the gate 3s can be used to reset the flip-flop 32. In Fig. 5, a blanking circuit 4A of an embodiment of the present invention is shown. When the control signal % is enabled, the control signal VG can be turned off the transistor 46 via the inverter 42ff1. When the transistor 46 is turned off, a current source 41 begins to charge a battery 47. The capacitor 47 is further connected via an inverting || 43 to an input of a reverse 45, and the other input of the gate 45 is lightly coupled to the control signal %. Therefore, the output of the inverse gate 45 is generated in accordance with the activation of the control signal w - the blanking signal Vblk. The current value of the current source 41 and the capacitance value of the capacitor 47 determine the pulse width of the blanking signal vBLK. When the control (4) Vg is turned on, the blanking signal Vblk ensures a maximum on time of the control signal Vg. Referring to Figures 1 and 2, the minimum on-time of the control signal vG further ensures a minimum pulse width of the reflected voltage %, which helps to detect the reflected voltage. • Fig. 6 shows a detection circuit 5〇 according to an embodiment of the present creation. The detection circuit 5A includes an error amplifier 67, a waveform check chamber 1GG, and a bias circuit. Referring to Fig. 3, the bias circuit generates a % of the job at the input terminal DET of the detecting circuit 50, and the help side reflects the money, and the waveform of the fine bribe is distorted. The generated bias signal VB is proportional to the adjustment signal iB. The bias circuit includes a transistor 6S having a source terminal coupled to the input terminal DET of the detection circuit so to generate a bias signal VB. Resistor 60 is operative to receive an adjustment signal Ib for generating a bias voltage at a gate terminal of transistor 65. Therefore, the generated bias signal 乂^ is proportional to the bias voltage. In order to compensate the voltage from the gate to the source of the transistor 65, the transistor 61 is connected in series with the resistor 6?. A gate terminal and a terminal of the transistor 61 are connected to the resistor 6A. A source terminal of the transistor 61 is grounded. In addition, current source 62 is used to bias transistor 61. In order to detect the reflected voltage VF, the waveform detector 1 is coupled to the input terminal DET to sense the reflected voltage, and • generates a sampled signal vA based on the reflected voltage VF. The error amplifier 67 having the reference signal VREF generates a feedback signal VFB based on the sampling signal VA. The error amplifier 67 is a trailer-conductance amplifier. An output of the error amplifier 67 is coupled to the COM terminal of the controller 25. Referring to Figure 1, capacitor 24 is coupled to the COM terminal to provide frequency compensation for error amplifier 67. Fig. 7 is a circuit diagram showing the waveform detector 1A of an embodiment of the present invention. A transistor 14A has a terminal that is connected to a current source 105. An amplifier 102 has a positive input coupled to the input terminal DET of the detection circuit 5A for detecting the reflected voltage vF. An output of amplifier 102 is coupled to a gate of transistor 140. A negative input of amplifier 102 is coupled to a source terminal of transistor 140. Capacitor 161 is coupled to a source terminal of electro-conductor 140. A switch 151 is connected in parallel with the capacitor 161 for periodically discharging the capacitor 161. The capacitor 160 generates a sampling signal VA in accordance with the reflected voltage VF. A switch 150 is controlled by the pulse signal PLS, and the voltage on the capacitor 161 is periodically sampled onto the capacitor 160 to store the sample signal vA on the capacitor 6 M302194 160. FIG. 8 shows a circuit diagram of the adjustment circuit 55. An amplifier 8A has a positive input supplied by a threshold voltage Vth. An amplifier 81 has a positive input coupled to the feedback signal Vfb. A negative input terminal of the amplifier 81 is connected to the -output terminal of the amplification H 81 to form a buffer ... the transistor (10) is secreted to an output of the amplifier (10) to generate a current according to the threshold voltage vTH and the feedback signal Vfb. Hey. A resistor 85 is connected from the - source of the transistor 90 to the "output" of the amplifier 81. - The transistor 91 and a transistor form a current mirror so that it depends on the current! 9〇 produces an adjustment signal lB. Therefore, the adjustment health & can be generated according to the feedback signal %, wherein the feedback signal Vfb can be generated according to the reflected voltage vF. The ninth indication is according to the current implementation_electrical rotation (four) under the light load. The bias signal VB is added to the input terminal DET. The voltage vDET is expressed as follows:
(2) (3)(twenty three)
Vdet = Vfx(1_ eRxC )+Vb t = RxCxln(-Vdet = Vfx(1_ eRxC )+Vb t = RxCxln(-
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Vf - Vdet + Vb -------------- 奋雷ill二:電阻器22的電阻值’ C疋寄生電容器23的電容值，且*是將電壓Vmt 充電到反射電料的週期。藉由添加偏壓信號％，可大幅 。 因此，可正確地檢測反射電壓Vf。 电i DET社升時間。 以上所述，僅是本齡驗佳實關Μ，並转本崎餘何 然本創作已以較佳實施例揭露如上，然而並非用 的雖 人員，在不脫離本創作技術方絲圍内，當可_^作任何熟悉本專業的技術 的更動或修飾為等同變化的等效實施例，但是凡賴I的結構及技仙容作出些許 本創作的技術實質對以上實關所作的任何簡單⑱ ㈤作技射案㈣容，依據 作技術方錢範_。 1礼改、相變化鄕飾，_屬於本創 【圖式簡單說明】 M3 02194Vf - Vdet + Vb -------------- Fen Lei ill 2: Resistor 22's resistance value 'C parasitic capacitor 23's capacitance value, and * is charging voltage Vmt to reflected electricity The cycle of the material. By adding the bias signal %, it can be large. Therefore, the reflected voltage Vf can be correctly detected. Electric i DET society rose time. As mentioned above, it is only the age of good practice, and it is said that this creation has been disclosed in the preferred embodiment as above, but the personnel who are not used, without departing from the creation technique, Any modification or modification of the technology of the art may be equivalent to the equivalent embodiment, but the structure and skill of the Lai I make some of the technical essence of the creation of the simple implementation of the above. (5) For the technical shooting case (four) capacity, based on the technical side of the money _. 1 ritual reform, phase change decoration, _ belongs to this creation [Simple diagram description] M3 02194
第1圖繪示傳統電源轉換器的電路圖。 第2圖繪示傳統電源轉在輕载絲下多個信號的電壓波形圖。 第3圖繪示本創作一實施例的一控制器的方塊圖。 第4圖繪示本創作一實施例的一切換電路示意圖。 第5圖繪示本創作一實施例的一遮沒電路示意圖。 第ό圖繪示本創作一實施例的一檢測電路示意圖。 第7圖繪示本創作一實施例的一波形檢測器的電路示竜圖。 第8圖繪示本創作一實施例的一調整電路示意圖。 第9圖繪示根據本創作-實施_電源轉換脉輕载下衫條號電壓波形圖。 【主要元件符號說明】 10 :變壓器 20、150、151 :開關 23 :寄生電容器 2S :控制器 31 :振盪電路 33、42、43 :反相器 35、45:反及閘 40 ··遮沒電路 46、61、65、140 :電晶體 55 :調整電路 67 :誤差放大器 102:放大器 PLS :脈衝信號 15 :整流器 21、22、60 :電阻器24、47、160、161 :電容器 30 :切換電路 32 :正反器 34:及閘 36 :比較器 41 :電流源 50 :檢測電路 62、10S :電流源 100 :波形檢測器 Ιβ:調整信號 Να :輔助繞組 8 M3 02194 NP :初級繞組 Ns :次級繞組 TDS :輸出電壓 T〇n :輸出電壓 VA:取樣信號 Vblk :遮沒信號 Vdet :電壓 VF :反射電壓 VFB :反饋信號 VG :控制信號 νΪΝ :輸入電壓 V〇 :輸出電壓 Vref :參考信號 Vs :電流信號 VTH :門檻電壓Figure 1 is a circuit diagram of a conventional power converter. Figure 2 is a diagram showing voltage waveforms of multiple signals transmitted by a conventional power supply to a light load wire. FIG. 3 is a block diagram showing a controller of an embodiment of the present invention. FIG. 4 is a schematic diagram of a switching circuit of an embodiment of the present invention. FIG. 5 is a schematic diagram of a blanking circuit according to an embodiment of the present invention. The figure is a schematic diagram of a detection circuit of an embodiment of the present invention. FIG. 7 is a circuit diagram showing a waveform detector according to an embodiment of the present invention. FIG. 8 is a schematic diagram showing an adjustment circuit of an embodiment of the present invention. Figure 9 is a diagram showing the voltage waveform of the light-loaded shirt number according to the present creation-implementation_power conversion pulse. [Description of main component symbols] 10: Transformer 20, 150, 151: Switch 23: Parasitic capacitor 2S: Controller 31: Oscillation circuit 33, 42, 43: Inverter 35, 45: Inverting gate 40 · · Masking circuit 46, 61, 65, 140: transistor 55: adjustment circuit 67: error amplifier 102: amplifier PLS: pulse signal 15: rectifier 21, 22, 60: resistors 24, 47, 160, 161: capacitor 30: switching circuit 32 : flip-flop 34: and gate 36: comparator 41: current source 50: detection circuit 62, 10S: current source 100: waveform detector Ι β: adjustment signal Ν α: auxiliary winding 8 M3 02194 NP: primary winding Ns: secondary Winding TDS: output voltage T〇n: output voltage VA: sampling signal Vblk: blanking signal Vdet: voltage VF: reflected voltage VFB: feedback signal VG: control signal νΪΝ: input voltage V〇: output voltage Vref: reference signal Vs: Current signal VTH: threshold voltage