M297529 八、新型說明： 【新型所屬之技術領域】 本創作便於製程管控的封裝晶片結構改良 別、指一種可以確保晶片與其它電性設備的焊接品併 ，並能於焊接完成後簡㈣行品質㈣ = 片結構改良。 了衣日日 【先前技術】 習知的封裝晶片結構係有多種型式，其中一種精 小化的封裝晶片結構如第九圖及第十圖所示，係具= 一裸晶片10，於裸晶片10的底面使用一接著層3〇社 合有複數引腳201呈二排或四排對稱狀排列的一 ^ 線架20,該導線架20的引腳201係呈矩形塊狀，具有 鄰近裸晶片10中間的一内接電端202，及延伸出裸晶 片10外侧的一外接電端203，藉此於内接電端2〇2使 用引線40與裸晶片1〇一面的電性接點1〇1連接，並使 用一封膠體50包覆密封各引線40及引腳2〇1的内接 電端202，即組成精小化的封裝晶片，可利用導線架 20各引腳201的外接電端203透過錫球60或錫膏等焊 接材料與其它電性設備構成電性連接。 因上述導線架20的各引腳201係構成矩形塊狀， 直接利用引腳201外側底面作為外接電端203，若此 ’當錫球60或錫膏等焊接材料係應用交錯位置焊接 方式與其它電性設備構成電性連接時，即無法應用簡 易的檢驗設備進行焊接品質的檢視、控管，必需仰賴 5 M297529 特殊且φ貴的檢驗設備（例如χ光檢驗機等），是以 無法降低封裝晶片的製程及品管成本，影響產品於市 場的競爭力。 【新型内容】 —緣此本創作主要目的，即在於提供一種便於製程 J控的封裝晶片結構改良，特別透過封裝晶片的導線 木構改良使其引腳的外接電端具有一個可供作為 焊接位置的焊接彎折部，藉此達成預防各焊接彎折部 的錫膏相互誤觸，提升焊接品質，並能使關易的檢 驗設備進行焊接品質的檢視及控管，俾增進品管效率 ’並降低品管成本。 省依上述目的，本創作的實施内容係包括裸晶片、 導線架、接著層、引線及封膠體所、组成，其中··該導 線架係為二排或四排矩陣排列的複數引腳呈對稱狀 構成，藉由接著層使導線架的複數引腳結合於裸晶片 =選定面，用以作為裸晶片與外界的導電媒介，^別 令各引腳的外側的外接電端構成有一焊接彎折部，且 各f腳的焊接彎折部排列呈對齊狀或交錯位置狀態 :藉此可供於焊接時預防各引腳的焊錫相互誤觸，並 迠於製成後簡易進行品質檢視及管控。 【實施方式】 紋依附圖實施例將本創作之結構特徵及其他之 作用、目的詳細說明如下·· 如第一圖及第二圖所示，本創作『便於製程管控 的封裝晶片結構改良』，係包括一裸晶片丄、一導線 M297529 架2、一接著層3、複數引線4及-封膠體5所組成 ，其中： 裸S曰片1，參閱第一圖及第二圖所示，係為半導 體材料所製成的習知電子元件，於其—敎面設有複 數電性接點11 ’藉該複數電性接點”與導線架2構成 電性連接； 、導線架2，參閱第一圖及第二圖所示，係固設於 裸晶片1複數電性接點彳彳該面的金屬介質，可採以金 屬材料沖切為複數塊狀引腳21呈二排或矩陣排列所 構成，使導線架2中間形成一鏤空部22可供裸晶片工 複數電性接點11及下述的引線4及封膠體$容置；各 引腳21於内側具有一内接電端211，而其外側具有一 外接電端212，並於外接電端212設有一向下凸出的 焊接彎折部213，並令各引腳21之間的焊接彎折部 213形成交錯位置的排列狀態（如第二圖所示），或使 各引腳21之間的焊接彎折部213呈對齊排列狀態（如 第三圖所示），藉以該焊接彎折部213作為與電路板焊 接的部位； 接著層3,參閱第一圖所示，係黏著於裸晶片工 其電性接點11該面的一黏性物質，可為專用於黏著裸 晶片1與導線架2的膠帶或其他物質，藉該接著層3 使裸晶片1黏固於導線架2的各引腳21上； 複數引線4，參閱第一圖所示，係分別焊接於裸 曰曰片1其電性接點11與各引腳21其内接電端211構 成電性連接的金屬線； M297529 封膠體5，參閱第一圖所示，係為絕緣材料，乃 填充於導線架2的鏤空部22,構成包覆密封裸晶片工 的電性接點11、複數引線4及各引腳21其内接電端 211結構，藉此即組成本創作可方便於製程管控 裝晶片結構。 ' 藉本創作上揭實施例的創作，因該導線架2的各 引腳21外接電知212係分別形成有一向下凸出的焊 接背折部213 ’故可利用各焊接彎折部213的底面與 電路板表面的電性接點對應焊接；由於藉焊接彎折部 213係能提升各引腳21與電路板表面保持一定間距 ，。故使用錫膏進行熱迴風焊接時，熔融的錫膏即不能 誤沾引腳其他部位，特別是各焊接彎折部213形成交 錯位置排列的結構實施方式，係能預防各焊接彎折部 213的熔融錫膏相互接觸短路，故使本創作達成焊接 製程易控管及提升焊接品f等功效。另因本創作各焊 接寫、折部213係構成於預設的位置，於進行焊接時， 較方便用於對齊電路板表面的電性接點，特別是在焊 接完成之後，即能使用簡易的儀器進行焊接品質的檢 視’而不需使用昂貴的、特殊的儀器，是以能藉此獲 致品管效率提升及降低品管成本功效。 次參閱第四圖所示，本創作該導線架2各引腳21 的焊接彎折部213外側，係可向外側設有一凸塊214 ，藉此增進焊接彎折部213底面面積，亦能提供與電 路板表面的電性接點對應焊接，俾達成上述焊接品質 提升，以及品管效率提升與降低品管成本等功效亦 M297529 即便於製程管控者。 另參閱第五圖及第六圖所示，本創作係可於導線 架Μ鄰電路板的各排引腳21底面另設有一接^ 3 ’稭該接著層3’固定一導體層6，該導體層6可 為一金屬板片、金屬膜或導電纖維等導電性材料構成 ，並令稞晶片1其中—個或多個電性接點彳彳應用引線 4焊接於各導體層6;若此#縣w焊接於電路板 上，即運用該導體層6構成隔絕於裸晶片工與電路板 >之間的結構’以及裸晶片丄電性接點”與導體層6電 性連接結構，進一步達成電氣雜訊（Noise)之隔絕 (Electromagnetic Interference, EMI)、強化晶體封裝結構、可作為共通接地迴路， 以及增進散熱速率等功效。 再者本創作該裸晶片1並不限制固著於導線架 2上方的封裝結構’晴參閱第七圖及第八圖所示，該 裸晶片1係可藉所述接著層3黏固於導線架2的引 >腳21下面’並令上述引腳21外接電端212的焊接彎折 部213通過裸晶片1外側延伸至裸晶片1下方，可用 於與電路板表面的電性接點對應焊接，故亦能達成前 述焊接品質提升，以及品管效率提升與降低品管成本 等功效。且亦可在導線架2的各排引腳2彳上面另設有 y接著層3’，同樣藉該接著層3,固定一導體層6， 並7裸曰曰片1其中一個或多個電性接點彳彳應用引線 4焊接於各導體層6 ’亦能獲致上述電氣雜訊（Noise )之隔絕、降低電磁波干擾（E|ectr〇magnetic 9 M297529M297529 VIII. New description: [New technical field] This creation is convenient for process control and control of package wafer structure improvement, which means that it can ensure the soldering of wafers and other electrical equipment, and can be used to improve the quality of the finished (four) line. (4) = Improved film structure. [Previous Technology] Conventional packaged wafer structures are available in a variety of versions, one of which is a reduced packaged wafer structure as shown in the ninth and tenth figures, with a bare die 10 on the bare die. The bottom surface of the 10 is formed by a bonding layer 3, and the plurality of pins 201 are arranged in two rows or four rows of symmetrical lines. The leads 201 of the lead frame 20 are rectangular blocks with adjacent bare chips. An intermediate electrical terminal 202 in the middle of the 10 and an external electrical terminal 203 extending outside the bare die 10, thereby using the electrical contact 1 of the lead 40 and the bare die 1 at the internal electrical terminal 2〇2 〇1 is connected, and a glue 50 is used to cover and seal the inner leads 202 of the lead wires 40 and the pins 2〇1, that is, the packaged wafers which are formed into a small size, and the external power of the pins 201 of the lead frame 20 can be utilized. The terminal 203 is electrically connected to other electrical devices through solder materials such as solder balls 60 or solder paste. Since the pins 201 of the lead frame 20 are formed in a rectangular block shape, the outer bottom surface of the lead 201 is directly used as the external electrical terminal 203. If the solder material such as the solder ball 60 or the solder paste is applied to the staggered position welding method, When electrical equipment is electrically connected, it is impossible to apply simple inspection equipment for inspection and control of welding quality. It is necessary to rely on 5 M297529 special and expensive inspection equipment (such as calender inspection machine). The process and quality control costs of the wafer affect the competitiveness of the product in the market. [New content] - The main purpose of this creation is to provide an improved package structure for process control, especially through the wire structure of the packaged wafer, so that the external terminal of the pin has a soldering position. The welding and bending portion is used to prevent the solder pastes from being accidentally touched by each of the welding and bending portions, thereby improving the welding quality, and enabling the inspection equipment of Guanyi to perform inspection and control of the welding quality, thereby improving the quality of the quality control. Reduce the cost of quality control. According to the above objectives, the implementation of the present invention includes a bare wafer, a lead frame, an adhesive layer, a lead layer, and a sealant, and the composition of the lead frame is symmetrical in a matrix of two rows or four rows. In the form of a bonding layer, the plurality of leads of the lead frame are bonded to the bare die=selected surface to serve as a conductive medium between the bare wafer and the outside, and the external electrical end of each pin is formed with a solder bend. The welding bend portion of each f-foot is arranged in an aligned or staggered position state: thereby preventing the solders of the respective pins from being accidentally touched during welding, and performing quality inspection and control after the manufacture. [Embodiment] The structural features and other functions and purposes of the present invention will be described in detail below with reference to the embodiments of the drawings. As shown in the first and second figures, the creation of the package wafer structure for process control is improved. The system comprises a bare die 丄, a wire M297529 shelf 2, an adhesive layer 3, a plurality of leads 4 and a sealant 5, wherein: the bare S die 1 is shown in the first figure and the second figure, A conventional electronic component made of a semiconductor material is provided with a plurality of electrical contacts 11 'by the plurality of electrical contacts" and electrically connected to the lead frame 2; and the lead frame 2, see the first As shown in the figure and the second figure, the metal medium is fixed on the surface of the plurality of electrical contacts of the bare wafer 1 and can be formed by punching a metal material into a plurality of block pins 21 in two rows or a matrix. A hollow portion 22 is formed in the middle of the lead frame 2 for the bare chip electrical contact 11 and the lead 4 and the encapsulant $ described below; each pin 21 has an internal electrical terminal 211 on the inner side, and The outer side has an external electrical terminal 212, and the external electrical terminal 212 is provided with a direction The protruding soldering portion 213 is protruded, and the soldering and bending portions 213 between the leads 21 are arranged in an interlaced position (as shown in the second figure), or the solder between the leads 21 is bent. The portion 213 is in an aligned state (as shown in the third figure), whereby the soldering bent portion 213 is used as a portion to be soldered to the circuit board; and then the layer 3, as shown in the first figure, is adhered to the bare wafer for electrical properties. A viscous material on the surface of the contact 11 may be a tape or other material dedicated to the adhesion of the bare wafer 1 and the lead frame 2, and the adhesive layer 3 is used to adhere the bare wafer 1 to the pins 21 of the lead frame 2. The plurality of lead wires 4, as shown in the first figure, are respectively soldered to the bare metal piece 1 and the electrical contacts 11 and the metal wires 211 of the respective leads 21 are electrically connected; M297529 Sealant 5 Referring to the first figure, it is an insulating material, which is filled in the hollow portion 22 of the lead frame 2, and constitutes an electrical contact 11 for covering and sealing the bare die, a plurality of leads 4, and each pin 21 is internally connected to electricity. The structure of the end 211, whereby the composition of the creation can facilitate the process control and control of the wafer structure. In the example, the lead pins 21 of the lead frame 2 are electrically connected to each other, and the soldering back portion 213 ′ is formed downwardly. Therefore, the bottom surface of each soldering bent portion 213 and the surface of the circuit board can be utilized. The solder joints correspond to the soldering; since the soldering and bending portions 213 can improve the distance between the pins 21 and the surface of the circuit board, the solder paste can not be mistakenly soldered when the solder paste is used for hot return air soldering. The other parts, in particular, the structural embodiments in which the welding and bending portions 213 are arranged in a staggered position, can prevent the molten solder pastes of the welding and bending portions 213 from being in contact with each other, thereby making the welding process easy to control and lifting welding. The effect of the product f, etc.. Because the welding writes and folds 213 of the creation are formed at preset positions, it is convenient to be used for aligning the electrical contacts on the surface of the circuit board during welding, especially after the welding is completed. That is to say, it is possible to use a simple instrument for inspection of welding quality' without using expensive and special instruments, so as to achieve the efficiency of quality control and reduce the cost of quality control. Referring to the fourth figure, the outer side of the welded bent portion 213 of each lead 21 of the lead frame 2 is provided with a protrusion 214 to the outside, thereby increasing the area of the bottom surface of the welded bent portion 213, and also providing Corresponding to the electrical contact on the surface of the circuit board, the above-mentioned welding quality improvement, quality control efficiency improvement and cost reduction quality control are also achieved. M297529 is convenient for process controllers. Referring to FIG. 5 and FIG. 6 , the creation layer can further fix a conductor layer 6 on the bottom surface of each row of pins 21 of the lead frame adjacent to the circuit board. The conductor layer 6 can be made of a conductive material such as a metal plate, a metal film or a conductive fiber, and the one or more electrical contacts of the silicon wafer 1 are soldered to the respective conductor layers 6; #县w soldered to the circuit board, that is, the conductor layer 6 is used to form a structure between the bare die and the circuit board > and the bare chip electrical contact" and the conductor layer 6 electrical connection structure, further Achieve electrical noise (Electromagnetic Interference (EMI), strengthen the crystal package structure, can be used as a common ground loop, and improve the heat dissipation rate. In addition, the bare die 1 does not limit the fixing to the lead frame. 2 The upper package structure is as shown in the seventh and eighth figures. The bare die 1 can be adhered to the underside of the lead frame 2 by the adhesive layer 3 and the pin 21 is The soldering bent portion 213 of the external electrical terminal 212 passes through the bare wafer 1 Extending to the underside of the bare die 1 can be used for soldering corresponding to the electrical contacts on the surface of the circuit board, so that the above-mentioned welding quality improvement, quality improvement of the quality control and cost reduction of the quality control tube can be achieved, and also in the lead frame 2 Each row of pins 2 另 is further provided with a y back layer 3 ′, and the same layer 3 is used to fix a conductor layer 6 , and 7 bare dies 1 one or more electrical contacts 彳彳 application leads 4 soldering to each conductor layer 6' can also achieve the above-mentioned electrical noise (Noise) isolation, reduce electromagnetic interference (E|ectr〇magnetic 9 M297529
Interference，圓）、強化晶體封裝 通接地迴路，以及增進散熱速铸功效。可作為共 綜上所述，本創作所為之『便於製程管 :結構改良』’已確具實用性與創作性， 已稱合理進步至明。為此，依法提出新型“；：： 准懇凊肖局惠予詳審，並賜准專利為禱，至感德月便 【圖式簡單說明】 第一圖為本創作封裝晶片組成狀態之斷面示 ^二圖為本創作封裝晶片組成狀態之立體“圖。 圖為本創们1腳焊接彎折部呈對⑽列之示意 圖。 第四圖為本創作焊接彎折部外側另設凸塊之示意圖 Ο 第五圖為本創作增設有一導體層之斷面示意圖。 第六圖為本創作增設有一導體層之底面示意圖。 第七圖為本創作裸晶片及導體層組裝方式之另一實 施例斷面示意圖。 第八圖為本創作裸晶片及導體層組裝方式之另一實 施例斷面示意圖。 第九圖為習見精小化封裝晶片之斷面示意圖。 第十圖為習見精小化封裝晶片之正面示意圖。 M297529 【主要元件符號說明】 裸晶片1， 導線架2 ; 内接電端211 ; 焊接彎折部213 ; 鏤空部22 ; 引線4 ; 導體層6 ; 電性接點11 ; 引腳21 ; 外接電端21 2 ; 凸塊21 4 ; 接著層3、3 ’ ； 封膠體5 ;Interference, round), enhanced crystal package through ground loop, and improved heat dissipation and rapid casting efficiency. As a whole, the creation of the “Easy Process Management: Structural Improvement” has indeed been practical and creative, and it has been said to be reasonably progressive. To this end, the new type of ";:: 恳凊 恳凊 局 惠 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详 详The second figure is a three-dimensional "picture" of the composition state of the packaged wafer. The figure shows a schematic diagram of the pair of weld bends in the pair (10). The fourth picture is a schematic view of the other side of the creative welding bending portion. 第五 The fifth figure is a schematic sectional view of the creation of a conductor layer. The sixth figure is a schematic diagram of the bottom surface of the creation of a conductor layer. The seventh figure is a schematic cross-sectional view showing another embodiment of the method of assembling the bare wafer and the conductor layer. The eighth figure is a schematic cross-sectional view showing another embodiment of the method of assembling the bare wafer and the conductor layer. The ninth picture is a schematic cross-sectional view of a small-sized package wafer. The eleventh figure is a front view of the Ximing fine-packaged wafer. M297529 [Description of main component symbols] bare die 1, lead frame 2; internal electrical terminal 211; soldered bent portion 213; hollowed portion 22; lead 4; conductor layer 6; electrical contact 11; pin 21; End 21 2 ; bump 21 4 ; then layer 3 , 3 ' ; sealant 5 ;
1111