M294774 八、新塑說明: 【新型所屬之技術領域】 本創作係關於-種主機板供電保護電路,尤指一種可自動檢列 mKc咖aliwssingUnit,巾央處妨)供物蚊域板供電 保護電路。 【先别技術】 t腦電_頭有-針腳上提供了 —魏控雜號⑽㈣信 •號)’該信號通常為高電平。待電腦之電源開關按紐(P〇werButton) ^ M PSON^fL^ ACPI( Advanced Configuration and PowerM294774 VIII, new plastic description: [New technology field] This creation is about a kind of motherboard power supply protection circuit, especially one can automatically check mKc coffee aliwssingUnit, towel central office) supply mosquito field board power supply protection circuit. [First technology] t brain electricity _ head has - provided on the pin - Wei control miscellaneous (10) (four) letter • number) 'This signal is usually high level. Wait until the computer's power switch button (P〇werButton) ^ M PSON^fL^ ACPI (Advanced Configuration and Power
Interface進階組態及電源介面)控制器控制而轉變為一低電平。電 源之工作狀紐於PS⑽錢由高電平觀為低電平時發生變 化’例如,若電源此時未給電腦供電,# ps〇N#信號由高電平轉變 為低電平時,電源啓動而給電腦供電;若此時電源正給電腦供電, 當PSON#信號由高電平轉變為低電平時,電源則關閉而停止給電腦 φ 供電。Interface advanced configuration and power interface) controller control and transition to a low level. The working status of the power supply is changed when the PS(10) money is low level from the high level view. For example, if the power supply does not supply power to the computer at this time, the #ps〇N# signal changes from a high level to a low level, and the power is turned on. Power the computer; if the power supply is supplying power to the computer at this time, when the PSON# signal changes from high level to low level, the power supply is turned off and the power supply to the computer φ is stopped.
Ik著CPU (Central Processing Unit,中央處理器)運行頻率之 提升,其耗電功率越來越高,因此電腦電源提供了專門為cpu供電 之插頭。目前用戶多趨向於自己動手去解決電腦的一些小問題,例 如在主機板上插裝元件或清潔CPU風扇等,在進行該等操作時,為 方便操作及安全考慮,用戶往往會將電源插接於主機板上之電源線 拔掉,待操作完成後,再將該等電源線插上,但由於CPU電源線不 太醒目,用戶常常僅接上主機板電源線而忘記接上CPU電源線。在 6 M294774 該種情況下,昨開顯,€料能實輯cpu , 機板供電。若該種情況持續―段時間,且由於 -仍然給主 器之初始使能電平有可能為低電平U電平有效),=輪出)控制 之I/O控制器將進入挂起狀能,接 士日守某些主機板 +、 触悲祕彳績發触何“輪士㈣ 电源開關信號將無法被朗,從而導致主機板電源 〜 機板長時間處於帶電非工繼,這樣對主機板^切斷’主 【新型内容】 、“艮大。 馨於以上喊’有必要提供—魏自動檢測咖供電狀 對主機板進行保護之供電保護電路。 / 之蝴r tr刪f顧她f输器電源線 之域板,該主機板供電紐電路包括—輸人輸出控_、一 組恶及電源細控彻、—控繼號産生電路及—使能信號產生^ 路,該控制信號産生電路根據該中央處理器之供電狀況而産生一於 制信號,並被送人_輸人輸出控㈣,同_使能錄產生桃 產生-使能信號’以使該輸入輸出控制器正常處理該控制作號,者 中央處理II魏絲正確連㈣,該控繼舰雜人細控制; 傳达關機錄_進階_及電較面㈣如卿電源停止供 電。 與習知技術概’本主機板供電保護電路具有更高的可靠性及 安全性’能於開機時快速檢測出CPU供電狀況,s CPU供電狀況 出現異常舰確保自麵機,及時祕護主機板。 【實施方式】 M294774 杯閱第一圖,本創作主機板供電保護電路包括-控制伸产 生電路10及一使能信號產生電路30。 & +曰該控制信號産生電路10包括—第—電晶體Q1、-第二場效應 電晶體Q2及-第三場效應電晶體⑺。該第—電晶體以之基極藉 由一第-電阻R1與電源輸出端P1相連,韓工作時,該電源輸出3 端P1輸出-高電平的正常工作信號S1,其集極藉由—第二電阻R2 齡贴上-提供+5V工作電壓之主機板供電端树,其射極與該 弟二場效應電晶體Q2之汲極相連。該第二場效應電晶體Q2之閉極 藉由一第三電阻R3與CPU (CentralPr〇cessingUnit,中央處理器) 工作電壓控制端P2相連,該控制端p2產生—工作電壓指示信號 S2,該第二場效應電晶體Q2源極接地,一第四電阻連接於該第二 場效應電晶體Q2之閘極與源極之間。該第三場效應電晶體Q3之閑 極連接該第-電晶體Q1之射極,其汲極輸出—控制信號,當咖 的供電出現異常時,該控制信號將改變開關信號pwrbt·,同時 該汲極接電腦電源開關6〇,其源極接地,—第五電阻R5連接於該 第三場效應電晶體Q3之閘極與源極之間。 . 該使能信號產生電路30包括一第四場效應電晶體〇4、一第五 電晶體Q5及-第六場效應電晶體Q6。該第四場效應電晶體Q4之 閘極連接該第-電晶體Q1之射極’其源極接地,汲極接該第五電 晶體Q5之集極’該第五電晶體Q5之基極藉由一第六電阻R6接 CPI (Advanced Configuration and Power Interface 進階組態及電源 介面)控制器70之一輸出端P3,其集極藉由一第七電阻尺7接主機 M294774 板+5V供電端’其射極接地。該第六場效應電晶體⑼之間極接該 弟五電晶體Q5之集極,其沒極輸出一使能信號爾励送到㈧ (put/Output輸人輪出)控制^如使能端料,舰極藉由一第八 電謂接主機板+3.3V供電端,其源極接地,—第—電容C連接於 h第/、Μ應電日日體Q6之汲極與源極之間,用於穩定該第六場效 應電晶體Q6汲極輪出之使能信號PWRGD。 下面介紹該電路之工作過程。 。開機時按下電_關6G,通常情況下均保縣高電平之開關信 #u PWRBTN#此時變為低電平,1/〇控制器8〇發送一卿聰號給 A™控制器7〇,藉由ACPI控制器7〇控制電源50啓動’電源5〇 開始給主她供電’纽主機板+5v電壓及其他祕正常工作所· 要之電壓域,並同時産生一正常工作信 上 電平信號。 i為-南 若供電給咖之魏未接,對CPU未正常供電’在第一 =^2信號為低電平,該第二場效應電晶體Q2 _與源極間無 電壓,该第二場效應電晶體〇2截止。該第一電晶體〇 錢及信號S1之高電平個下導通,其射極輪出—高電平^ 效應電晶體q3之閘極與源極之間産生—偏置電壓,而使該 弟二場效應電晶體Q3導通,該第三場效應電晶體Q3没極二 制L龙此時爲低電平,從*與該第三場效應電aaa|| Q3 、工 之開關域PWRBTN#由高電平變為低電平;此時與…°、接Ik is the CPU (Central Processing Unit) operating frequency increase, its power consumption is getting higher and higher, so the computer power supply provides a plug for powering the CPU. At present, users tend to solve some small problems of the computer themselves, such as inserting components on the motherboard or cleaning the CPU fan. When performing such operations, the user often plugs in the power for convenience and safety. Unplug the power cable on the motherboard. After the operation is complete, plug the power cable. However, because the CPU power cable is not very conspicuous, users often connect only the power cable of the motherboard and forget to connect the CPU power cable. In the case of 6 M294774, it was opened yesterday, and the material can be used to make cpu and the board is powered. If this condition persists for a period of time, and because the -the initial enable level of the master is likely to be low level U level is valid, the I/O controller that controls the wheel will enter the pending state. Yes, the stalker keeps some motherboards +, touches the sorrowful performance, and the "wheel" (four) power switch signal will not be able to be lang, resulting in the motherboard power supply ~ the board is in the long-term non-working, so Motherboard ^ cut off 'main [new content], "big. Xin shouted above, it is necessary to provide - Wei automatically detects the power supply protection circuit for the protection of the motherboard. / The butterfly r tr delete f care her f drive power line domain board, the motherboard power supply circuit includes - input output control _, a group of evil and power fine control, - control serial generation circuit and - make The signal generation circuit generates a signal according to the power supply condition of the central processing unit, and is sent to the output controller (four), and the same is enabled to generate the peach generation-enable signal. In order for the input and output controller to properly handle the control number, the central processing II Weiss is connected correctly (four), the control ship is controlled by the miscellaneous person; the transmission is recorded _ advanced _ and the electric surface (four) such as Qing power stop powered by. Compared with the conventional technology, the power supply protection circuit of the motherboard has higher reliability and safety. It can quickly detect the CPU power supply status when the power is turned on. The CPU power supply condition is abnormal. The ship is guaranteed to be self-contained, and the motherboard is promptly protected. . [Embodiment] The M294774 cup is read in the first figure, and the power supply protection circuit of the main board includes a control extension circuit 10 and an enable signal generation circuit 30. & + 曰 The control signal generating circuit 10 includes - a first transistor Q1, a second field effect transistor Q2, and a - third field effect transistor (7). The base of the first transistor is connected to the power output terminal P1 by a first-resistor R1. When the Han is working, the power output 3 terminal P1 outputs a high-level normal working signal S1, and the collector is provided by the collector. The second resistor R2 is affixed with a power supply terminal tree providing a +5V operating voltage, the emitter of which is connected to the drain of the second field effect transistor Q2. The closed end of the second field effect transistor Q2 is connected to the CPU (Central Pr. singing Unit) operating voltage control terminal P2 via a third resistor R3, and the control terminal p2 generates an operating voltage indicating signal S2, which is The source of the two field effect transistor Q2 is grounded, and a fourth resistor is connected between the gate and the source of the second field effect transistor Q2. The idle electrode of the third field effect transistor Q3 is connected to the emitter of the first transistor Q1, and the drain output thereof is a control signal. When the power supply of the coffee is abnormal, the control signal changes the switching signal pwrbt·, and The bungee is connected to the computer power switch 6〇, the source thereof is grounded, and the fifth resistor R5 is connected between the gate and the source of the third field effect transistor Q3. The enable signal generating circuit 30 includes a fourth field effect transistor 〇4, a fifth transistor Q5, and a sixth field effect transistor Q6. The gate of the fourth field effect transistor Q4 is connected to the emitter of the first transistor Q1, the source thereof is grounded, and the drain is connected to the collector of the fifth transistor Q5, and the base of the fifth transistor Q5 is borrowed. A sixth resistor R6 is connected to an output terminal P3 of the CPI (Advanced Configuration and Power Interface) controller 70, and its collector is connected to the host M294774 board + 5V power supply terminal by a seventh resistor 7 'The emitter is grounded. The sixth field effect transistor (9) is connected to the collector of the fifth transistor Q5, and the output of the immersed signal is sent to the (8) (put/output input) control unit, such as the enable terminal. Material, the ship is connected to the main board +3.3V power supply terminal by an eighth power supply, and its source is grounded. The first capacitor C is connected to the bth pole and the source of the h/th, the electric field and the body Q6. For the purpose of stabilizing the enable signal PWRGD of the sixth field effect transistor Q6. The working process of the circuit is described below. . Press _ off 6G when starting up, usually under the condition of high level switch letter #u PWRBTN# at this time becomes low level, 1 / 〇 controller 8 〇 send a Qing Cong number to the ATM controller 7〇, through the ACPI controller 7〇 control power supply 50 start 'power 5 〇 start to power the main her 'new board + 5v voltage and other secrets normal work · the voltage domain, and at the same time generate a normal work letter Level signal. i is - Nan Ruo power supply to the Wei Wei Wei, the CPU is not normally powered 'in the first = ^ 2 signal is low, the second field effect transistor Q2 _ and the source without voltage, the second The field effect transistor 〇2 is turned off. The first transistor saves money and the signal S1 is turned on at a high level, and the emitter is turned off - a high level ^ effect transistor q3 generates a bias voltage between the gate and the source, and the brother The two field effect transistor Q3 is turned on, and the third field effect transistor Q3 is not the second system L dragon is low level at this time, from * and the third field effect electric aaa|| Q3, the switch domain PWRBTN# High level becomes low level; at this time, with...°,
Qi之射極相連之該第四場效應電晶體Q4之問極為高°電1晶體 电卞δ亥第四 M294774 場效應電晶體Q4導通,其沒極輸出一低電平 曰_6閘極為低電平,該第六場效應電晶體Q6截止,由於該= 場效應電MQ6祕與域板提供之3 3¥供電端相連,故其沒極 輸出一高辭使能信號PWRGD,以保證該⑽控制器8g繼續正常 工作’使得該低電平之開關信號pWRBTN#可藉由該⑽控制器⑹ 傳遞關機資訊給該ACPI控制㈣,進而由Acpi控制器死發送指 令給電源50使其停止供電而對主機板進行保護。 右供電給CPU之電源電線已接好,CPU供電正常,信號幻為 高電平,該信號S2藉由該第三電阻幻輸入至該第二場效應電晶體 Q2之閘極,該第二場效應電晶體⑽導通,其汲極輸出—低電平, 即第二電晶體Q3之閘極為低電平,該第三電晶體Q3截止,開關信 號PWRBTN#不受影響,繼續保持高電平。此時該第四場效應電^ 體Q4之閘極亦為低電平,該第四場效應電晶體Q4截止。由於= cpu之供電正常’該信號S2為高電平,電源5〇輸出之&信號與 該高電平信號S2 -同輸入到ACPI控制器、7(),該Α(:ρι㈣^ 輸出端P3輸出-高電平輔助信號%,該輔助信號%藉由該第六電 阻R6輸入到該第五電晶體Q5之基極,該第五電晶體Q5導通,其 集極輸出-低電平,即該第六場效應電晶體Q6閑極為低電平,該 第六場效應電晶體q6截止,其汲極輸出一高電平使能信號 PWRGD ’以保證該1/0控制器8〇繼續正常工作,該開關信號 PWRBTN#保持高電平’藉由該1/〇控制器8〇傳遞正常工作資訊給 該ACPI控制器70 ’進而由ACPI控制器7〇發送指令給電源5〇使 M294774 其繼續正常供電。 >綜上所述,本創作確已符合創作專利要求,羞依法提出 ‘應涵蓋於 二淮’以上所述者僅為本創作之較佳實施例,舉凡熟悉本創作技 蟄之人士’爰依本創作之精神所作之等效修部或變化,皆 以下之申請專利範圍内。 > 【圖式簡單說明】The fourth field effect transistor Q4 connected by the emitter of Qi is extremely high. The electric crystal 1 is electrically connected to the fourth M294774. The field effect transistor Q4 is turned on, and its immersed output is low. 曰6 gate is extremely low. Level, the sixth field effect transistor Q6 is turned off, because the field effect electric MQ6 secret is connected with the 3 3 power supply end provided by the domain board, so the poleless output a high word enable signal PWRGD to ensure the (10) The controller 8g continues to operate normally' such that the low level switching signal pWRBTN# can transmit the shutdown information to the ACPI control (4) by the (10) controller (6), and the Acpi controller dies to send the command to the power source 50 to stop the power supply. Protect the motherboard. The power supply wire for the right power supply to the CPU is connected, the CPU power supply is normal, the signal is phantom high, and the signal S2 is audibly input to the gate of the second field effect transistor Q2 by the third resistor, the second field The effect transistor (10) is turned on, and its drain output is low-level, that is, the gate of the second transistor Q3 is at a low level, the third transistor Q3 is turned off, and the switching signal PWRBTN# is not affected, and remains high. At this time, the gate of the fourth field effect transistor Q4 is also at a low level, and the fourth field effect transistor Q4 is turned off. Since the power supply of = cpu is normal 'the signal S2 is high level, the & output signal of the power supply 5〇 is input to the ACPI controller, 7() with the high level signal S2 - the Α(:ρι(四)^ output terminal P3 output - high level auxiliary signal %, the auxiliary signal % is input to the base of the fifth transistor Q5 through the sixth resistor R6, the fifth transistor Q5 is turned on, and its collector output - low level, That is, the sixth field effect transistor Q6 is idle at a low level, the sixth field effect transistor q6 is turned off, and the drain thereof outputs a high level enable signal PWRGD' to ensure that the 1/0 controller 8 continues normal. Working, the switch signal PWRBTN# remains high' by the 1/〇 controller 8〇 transmitting normal operation information to the ACPI controller 70' and then the ACPI controller 7〇 sends an instruction to the power supply 5, causing the M294774 to continue Normally, the power supply. In summary, the creation has indeed met the requirements for the creation of patents. It is a shame to propose that the above should be covered by the above-mentioned two examples, which is only the preferred embodiment of this creation. The equivalents or changes made by the person's spirit in the spirit of this creation Patent application within the range of >. [Brief Description of the drawings]
第-圖為本創作主機板供魏護較佳實施例之 電路圖 【主要元件符號說明】 控制信號產生電路 10 電源 50 進階組態與電源介面 70 第一電晶體 Q1 第三場效應電晶體 Q3 第五電晶體 Q5 第一電阻 R1 第三電阻 R3 第五電阻 R5 第七電阻 R7 第一電容 C 正常工作信號 S1 工作電壓指示信號 S2 輔助信號 S3 使能信號 PWRGD 開關信號 PWRBTN# 使能信號産生電路 30 電源開關 60 輸入輸出控制器 80 第二場效應電晶體 Q2 第四場效應電晶體 Q4 第六場效應電晶體 Q6 第二電阻 R2 第四電阻 R4 第六電阻 R6 第八電阻 R8 電源輸出端 P1 CPU工作電壓控制端 P2 進階組態與電源介面輸出端 P3 輸入輸出控制器使能端 P4 電源控制信號 PSON#The first figure is a circuit diagram of a preferred embodiment of the authoring motherboard for the maintenance of the main board [main component symbol description] control signal generating circuit 10 power supply 50 advanced configuration and power interface 70 first transistor Q1 third field effect transistor Q3 Fifth transistor Q5 first resistor R1 third resistor R3 fifth resistor R5 seventh resistor R7 first capacitor C normal operation signal S1 operating voltage indication signal S2 auxiliary signal S3 enable signal PWRGD switching signal PWRBTN# enable signal generating circuit 30 Power switch 60 I/O controller 80 Second field effect transistor Q2 Fourth field effect transistor Q4 Sixth field effect transistor Q6 Second resistor R2 Fourth resistor R4 Sixth resistor R6 Eight resistor R8 Power output terminal P1 CPU working voltage control terminal P2 advanced configuration and power interface output terminal P3 input and output controller enable terminal P4 power control signal PSON#
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